soc: Add the MAX32670 SoC

Add MAX32670 Kconfig and dts files

Co-authored-by: Maureen Helm <maureen.helm@analog.com>
Signed-off-by: Sadik Ozer <sadik.ozer@analog.com>

dts/arm/adi/max32/max32670-pinctrl.dtsi

@@ -0,0 +1,367 @@
+/*
+ * Copyright (c) 2024 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/max32-pinctrl.h>
+
+/ {
+	soc {
+		pinctrl: pin-controller@40008000 {
+
+			/omit-if-no-ref/ swdio_p0_0: swdio_p0_0 {
+				pinmux = <MAX32_PINMUX(0, 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ tmr0c_ia_p0_0: tmr0c_ia_p0_0 {
+				pinmux = <MAX32_PINMUX(0, 0, AF3)>;
+			};
+
+			/omit-if-no-ref/ swdclk_p0_1: swdclk_p0_1 {
+				pinmux = <MAX32_PINMUX(0, 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tmr0c_o_p0_1: tmr0c_o_p0_1 {
+				pinmux = <MAX32_PINMUX(0, 1, AF3)>;
+			};
+
+			/omit-if-no-ref/ spi0_miso_p0_2: spi0_miso_p0_2 {
+				pinmux = <MAX32_PINMUX(0, 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ uart1b_rx_p0_2: uart1b_rx_p0_2 {
+				pinmux = <MAX32_PINMUX(0, 2, AF2)>;
+			};
+
+			/omit-if-no-ref/ tmr1c_ia_p0_2: tmr1c_ia_p0_2 {
+				pinmux = <MAX32_PINMUX(0, 2, AF3)>;
+			};
+
+			/omit-if-no-ref/ spi0_mosi_p0_3: spi0_mosi_p0_3 {
+				pinmux = <MAX32_PINMUX(0, 3, AF1)>;
+			};
+
+			/omit-if-no-ref/ uart1b_tx_p0_3: uart1b_tx_p0_3 {
+				pinmux = <MAX32_PINMUX(0, 3, AF2)>;
+			};
+
+			/omit-if-no-ref/ tmr1c_oa_p0_3: tmr1c_oa_p0_3 {
+				pinmux = <MAX32_PINMUX(0, 3, AF3)>;
+			};
+
+			/omit-if-no-ref/ spi0_sck_p0_4: spi0_sck_p0_4 {
+				pinmux = <MAX32_PINMUX(0, 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ uart1b_cts_p0_4: uart1b_cts_p0_4 {
+				pinmux = <MAX32_PINMUX(0, 4, AF2)>;
+			};
+
+			/omit-if-no-ref/ tmr2c_ia_p0_4: tmr2c_ia_p0_4 {
+				pinmux = <MAX32_PINMUX(0, 4, AF3)>;
+			};
+
+			/omit-if-no-ref/ spi0_ss0_p0_5: spi0_ss0_p0_5 {
+				pinmux = <MAX32_PINMUX(0, 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ uart1b_rts_p0_5: uart1b_rts_p0_5 {
+				pinmux = <MAX32_PINMUX(0, 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ tmr2c_oa_p0_5: tmr2c_oa_p0_5 {
+				pinmux = <MAX32_PINMUX(0, 5, AF3)>;
+			};
+
+			/omit-if-no-ref/ div_clk_outa_p0_5: div_clk_outa_p0_5 {
+				pinmux = <MAX32_PINMUX(0, 5, AF4)>;
+			};
+
+			/omit-if-no-ref/ i2c0_scl_p0_6: i2c0_scl_p0_6 {
+				pinmux = <MAX32_PINMUX(0, 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ lptmr0b_ia_p0_6: lptmr0b_ia_p0_6 {
+				pinmux = <MAX32_PINMUX(0, 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tmr3c_ia_p0_6: tmr3c_ia_p0_6 {
+				pinmux = <MAX32_PINMUX(0, 6, AF3)>;
+			};
+
+			/omit-if-no-ref/ i2c0_sda_p0_7: i2c0_sda_p0_7 {
+				pinmux = <MAX32_PINMUX(0, 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ lptmr0b_oa_p0_7: lptmr0b_oa_p0_7 {
+				pinmux = <MAX32_PINMUX(0, 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ tmr3c_oa_p0_7: tmr3c_oa_p0_7 {
+				pinmux = <MAX32_PINMUX(0, 7, AF3)>;
+			};
+
+			/omit-if-no-ref/ uart0a_rx_p0_8: uart0a_rx_p0_8 {
+				pinmux = <MAX32_PINMUX(0, 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ i2s0_sdo_p0_8: i2s0_sdo_p0_8 {
+				pinmux = <MAX32_PINMUX(0, 8, AF2)>;
+			};
+
+			/omit-if-no-ref/ tmr0c_ia_p0_8: tmr0c_ia_p0_8 {
+				pinmux = <MAX32_PINMUX(0, 8, AF3)>;
+			};
+
+			/omit-if-no-ref/ uart0a_tx_p0_9: uart0a_tx_p0_9 {
+				pinmux = <MAX32_PINMUX(0, 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ i2s0_lrclk_p0_9: i2s0_lrclk_p0_9 {
+				pinmux = <MAX32_PINMUX(0, 9, AF2)>;
+			};
+
+			/omit-if-no-ref/ tmr0c_oa_p0_9: tmr0c_oa_p0_9 {
+				pinmux = <MAX32_PINMUX(0, 9, AF3)>;
+			};
+
+			/omit-if-no-ref/ uart0a_cts_p0_10: uart0a_cts_p0_10 {
+				pinmux = <MAX32_PINMUX(0, 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ i2s0_bclk_p0_10: i2s0_bclk_p0_10 {
+				pinmux = <MAX32_PINMUX(0, 10, AF2)>;
+			};
+
+			/omit-if-no-ref/ tmr1c_ia_p0_10: tmr1c_ia_p0_10 {
+				pinmux = <MAX32_PINMUX(0, 10, AF3)>;
+			};
+
+			/omit-if-no-ref/ div_clk_outb_p0_10: div_clk_outb_p0_10 {
+				pinmux = <MAX32_PINMUX(0, 10, AF4)>;
+			};
+
+			/omit-if-no-ref/ uart0a_rts_p0_11: uart0a_rts_p0_11 {
+				pinmux = <MAX32_PINMUX(0, 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ i2s0_sdi_p0_11: i2s0_sdi_p0_11 {
+				pinmux = <MAX32_PINMUX(0, 11, AF2)>;
+			};
+
+			/omit-if-no-ref/ tmr1c_oa_p0_11: tmr1c_oa_p0_11 {
+				pinmux = <MAX32_PINMUX(0, 11, AF3)>;
+			};
+
+			/omit-if-no-ref/ i2c1_scl_p0_12: i2c1_scl_p0_12 {
+				pinmux = <MAX32_PINMUX(0, 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ ext_clk2_p0_12: ext_clk2_p0_12 {
+				pinmux = <MAX32_PINMUX(0, 12, AF2)>;
+			};
+
+			/omit-if-no-ref/ tmr2c_ia_p0_12: tmr2c_ia_p0_12 {
+				pinmux = <MAX32_PINMUX(0, 12, AF3)>;
+			};
+
+			/omit-if-no-ref/ ext_clk1_p0_12: ext_clk1_p0_12 {
+				pinmux = <MAX32_PINMUX(0, 12, AF4)>;
+			};
+
+			/omit-if-no-ref/ i2c1_sda_p0_13: i2c1_sda_p0_13 {
+				pinmux = <MAX32_PINMUX(0, 13, AF1)>;
+			};
+
+			/omit-if-no-ref/ cal32k_p0_13: cal32k_p0_13 {
+				pinmux = <MAX32_PINMUX(0, 13, AF2)>;
+			};
+
+			/omit-if-no-ref/ tmr2c_oa_p0_13: tmr2c_oa_p0_13 {
+				pinmux = <MAX32_PINMUX(0, 13, AF3)>;
+			};
+
+			/omit-if-no-ref/ spi1_ss0_p0_13: spi1_ss0_p0_13 {
+				pinmux = <MAX32_PINMUX(0, 13, AF4)>;
+			};
+
+			/omit-if-no-ref/ spi1_miso_p0_14: spi1_miso_p0_14 {
+				pinmux = <MAX32_PINMUX(0, 14, AF1)>;
+			};
+
+			/omit-if-no-ref/ uart2b_rx_p0_14: uart2b_rx_p0_14 {
+				pinmux = <MAX32_PINMUX(0, 14, AF2)>;
+			};
+
+			/omit-if-no-ref/ tmr3c_ia_p0_14: tmr3c_ia_p0_14 {
+				pinmux = <MAX32_PINMUX(0, 14, AF3)>;
+			};
+
+			/omit-if-no-ref/ spi1_mosi_p0_15: spi1_mosi_p0_15 {
+				pinmux = <MAX32_PINMUX(0, 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ uart2b_tx_p0_15: uart2b_tx_p0_15 {
+				pinmux = <MAX32_PINMUX(0, 15, AF2)>;
+			};
+
+			/omit-if-no-ref/ tmr3c_oa_p0_15: tmr3c_oa_p0_15 {
+				pinmux = <MAX32_PINMUX(0, 15, AF3)>;
+			};
+
+			/omit-if-no-ref/ spi1_sck_p0_16: spi1_sck_p0_16 {
+				pinmux = <MAX32_PINMUX(0, 16, AF1)>;
+			};
+
+			/omit-if-no-ref/ uart2b_cts_p0_16: uart2b_cts_p0_16 {
+				pinmux = <MAX32_PINMUX(0, 16, AF2)>;
+			};
+
+			/omit-if-no-ref/ tmr0c_ia_p0_16: tmr0c_ia_p0_16 {
+				pinmux = <MAX32_PINMUX(0, 16, AF3)>;
+			};
+
+			/omit-if-no-ref/ spi1_ss0_p0_17: spi1_ss0_p0_17 {
+				pinmux = <MAX32_PINMUX(0, 17, AF1)>;
+			};
+
+			/omit-if-no-ref/ uart2b_rts_p0_17: uart2b_rts_p0_17 {
+				pinmux = <MAX32_PINMUX(0, 17, AF2)>;
+			};
+
+			/omit-if-no-ref/ tmr0c_oa_p0_17: tmr0c_oa_p0_17 {
+				pinmux = <MAX32_PINMUX(0, 17, AF3)>;
+			};
+
+			/omit-if-no-ref/ i2c2_scl_p0_18: i2c2_scl_p0_18 {
+				pinmux = <MAX32_PINMUX(0, 18, AF1)>;
+			};
+
+			/omit-if-no-ref/ tmr1c_ia_p0_18: tmr1c_ia_p0_18 {
+				pinmux = <MAX32_PINMUX(0, 18, AF3)>;
+			};
+
+			/omit-if-no-ref/ i2c2_sda_p0_19: i2c2_sda_p0_19 {
+				pinmux = <MAX32_PINMUX(0, 19, AF1)>;
+			};
+
+			/omit-if-no-ref/ tmr1c_oa_p0_19: tmr1c_oa_p0_19 {
+				pinmux = <MAX32_PINMUX(0, 19, AF3)>;
+			};
+
+			/omit-if-no-ref/ cm4_rx_p0_20: cm4_rx_p0_20 {
+				pinmux = <MAX32_PINMUX(0, 20, AF1)>;
+			};
+
+			/omit-if-no-ref/ tmr2c_ia_p0_20: tmr2c_ia_p0_20 {
+				pinmux = <MAX32_PINMUX(0, 20, AF3)>;
+			};
+
+			/omit-if-no-ref/ swdclkb_p0_20: swdclkb_p0_20 {
+				pinmux = <MAX32_PINMUX(0, 20, AF4)>;
+			};
+
+			/omit-if-no-ref/ cm4_tx_p0_21: cm4_tx_p0_21 {
+				pinmux = <MAX32_PINMUX(0, 21, AF1)>;
+			};
+
+			/omit-if-no-ref/ tmr2c_oa_p0_21: tmr2c_oa_p0_21 {
+				pinmux = <MAX32_PINMUX(0, 21, AF3)>;
+			};
+
+			/omit-if-no-ref/ lptmr1a_ia_p0_22: lptmr1a_ia_p0_22 {
+				pinmux = <MAX32_PINMUX(0, 22, AF1)>;
+			};
+
+			/omit-if-no-ref/ tmr3c_ia_p0_22: tmr3c_ia_p0_22 {
+				pinmux = <MAX32_PINMUX(0, 22, AF3)>;
+			};
+
+			/omit-if-no-ref/ swdiob_p0_22: swdiob_p0_22 {
+				pinmux = <MAX32_PINMUX(0, 22, AF4)>;
+			};
+
+			/omit-if-no-ref/ lptmr1a_oa_p0_23: lptmr1a_oa_p0_23 {
+				pinmux = <MAX32_PINMUX(0, 23, AF1)>;
+			};
+
+			/omit-if-no-ref/ tmr3c_oa_p0_23: tmr3c_oa_p0_23 {
+				pinmux = <MAX32_PINMUX(0, 23, AF3)>;
+			};
+
+			/omit-if-no-ref/ lpuart0_cts_p0_24: lpuart0_cts_p0_24 {
+				pinmux = <MAX32_PINMUX(0, 24, AF1)>;
+			};
+
+			/omit-if-no-ref/ uart0b_rx_p0_24: uart0b_rx_p0_24 {
+				pinmux = <MAX32_PINMUX(0, 24, AF2)>;
+			};
+
+			/omit-if-no-ref/ tmr0c_ia_p0_24: tmr0c_ia_p0_24 {
+				pinmux = <MAX32_PINMUX(0, 24, AF3)>;
+			};
+
+			/omit-if-no-ref/ lpuart0_rts_p0_25: lpuart0_rts_p0_25 {
+				pinmux = <MAX32_PINMUX(0, 25, AF1)>;
+			};
+
+			/omit-if-no-ref/ uart0b_tx_p0_25: uart0b_tx_p0_25 {
+				pinmux = <MAX32_PINMUX(0, 25, AF2)>;
+			};
+
+			/omit-if-no-ref/ tmr0c_oa_p0_25: tmr0c_oa_p0_25 {
+				pinmux = <MAX32_PINMUX(0, 25, AF3)>;
+			};
+
+			/omit-if-no-ref/ lpuart0_rx_p0_26: lpuart0_rx_p0_26 {
+				pinmux = <MAX32_PINMUX(0, 26, AF1)>;
+			};
+
+			/omit-if-no-ref/ uart0b_cts_p0_26: uart0b_cts_p0_26 {
+				pinmux = <MAX32_PINMUX(0, 26, AF2)>;
+			};
+
+			/omit-if-no-ref/ tmr1c_ia_p0_26: tmr1c_ia_p0_26 {
+				pinmux = <MAX32_PINMUX(0, 26, AF3)>;
+			};
+
+			/omit-if-no-ref/ lpuart0_tx_p0_27: lpuart0_tx_p0_27 {
+				pinmux = <MAX32_PINMUX(0, 27, AF1)>;
+			};
+
+			/omit-if-no-ref/ uart0b_rts_p0_27: uart0b_rts_p0_27 {
+				pinmux = <MAX32_PINMUX(0, 27, AF2)>;
+			};
+
+			/omit-if-no-ref/ tmr1c_oa_p0_27: tmr1c_oa_p0_27 {
+				pinmux = <MAX32_PINMUX(0, 27, AF3)>;
+			};
+
+			/omit-if-no-ref/ uart1a_rx_p0_28: uart1a_rx_p0_28 {
+				pinmux = <MAX32_PINMUX(0, 28, AF1)>;
+			};
+
+			/omit-if-no-ref/ tmr2c_ia_p0_28: tmr2c_ia_p0_28 {
+				pinmux = <MAX32_PINMUX(0, 28, AF3)>;
+			};
+
+			/omit-if-no-ref/ uart1a_tx_p0_29: uart1a_tx_p0_29 {
+				pinmux = <MAX32_PINMUX(0, 29, AF1)>;
+			};
+
+			/omit-if-no-ref/ tmr2c_oa_p0_29: tmr2c_oa_p0_29 {
+				pinmux = <MAX32_PINMUX(0, 29, AF3)>;
+			};
+
+			/omit-if-no-ref/ uart1a_cts_p0_30: uart1a_cts_p0_30 {
+				pinmux = <MAX32_PINMUX(0, 30, AF1)>;
+			};
+
+			/omit-if-no-ref/ tmr3c_ia_p0_30: tmr3c_ia_p0_30 {
+				pinmux = <MAX32_PINMUX(0, 30, AF3)>;
+			};
+
+		};
+	};
+};

dts/arm/adi/max32/max32670.dtsi

@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2024 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/armv7-m.dtsi>
+#include <adi/max32/max32xxx.dtsi>
+
+&sram0 {
+	reg = <0x20000000 DT_SIZE_K(16)>;
+};
+
+&flash0 {
+	reg = <0x10000000 DT_SIZE_K(384)>;
+};
+
+&clk_inro {
+	clock-frequency = <DT_FREQ_K(80)>;
+};
+
+/* MAX32670 extra peripherals. */
+/ {
+	soc {
+		sram1: memory@20004000 {
+			compatible = "mmio-sram";
+			reg = <0x20004000 DT_SIZE_K(16)>;
+		};
+
+		sram2: memory@20008000 {
+			compatible = "mmio-sram";
+			reg = <0x20008000 DT_SIZE_K(32)>;
+		};
+
+		sram3: memory@20010000 {
+			compatible = "mmio-sram";
+			reg = <0x20010000 DT_SIZE_K(64)>;
+		};
+
+		sram4: memory@20020000 {
+			compatible = "mmio-sram";
+			reg = <0x20020000 DT_SIZE_K(4)>;
+		};
+
+		sram5: memory@20021000 {
+			compatible = "mmio-sram";
+			reg = <0x20021000 DT_SIZE_K(4)>;
+		};
+
+		sram6: memory@20022000 {
+			compatible = "mmio-sram";
+			reg = <0x20022000 DT_SIZE_K(8)>;
+		};
+
+		sram7: memory@20024000 {
+			compatible = "mmio-sram";
+			reg = <0x20024000 DT_SIZE_K(16)>;
+		};
+
+		uart3: serial@40145000 {
+			compatible = "adi,max32-uart";
+			reg = <0x40145000 0x1000>;
+			clocks = <&gcr ADI_MAX32_CLOCK_BUS2 2>;
+			clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
+			interrupts = <88 0>;
+			status = "disabled";
+		};
+	};
+};

soc/adi/max32/Kconfig

@@ -14,6 +14,9 @@ config SOC_FAMILY_MAX32
 config SOC_MAX32655
 	select CPU_CORTEX_M4
 
+config SOC_MAX32670
+	select CPU_CORTEX_M4
+
 config SOC_MAX32672
 	select CPU_CORTEX_M4
 

soc/adi/max32/Kconfig.defconfig.max32670

@@ -0,0 +1,14 @@
+# Analog Devices MAX32670 MCU
+
+# Copyright (c) 2024 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_MAX32670
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,/clocks/clk_ipo,clock-frequency)
+
+config NUM_IRQS
+	default 100
+
+endif # SOC_MAX32670

soc/adi/max32/Kconfig.soc

@@ -17,6 +17,10 @@ config SOC_MAX32655_M4
 	bool
 	select SOC_MAX32655
 
+config SOC_MAX32670
+	bool
+	select SOC_FAMILY_MAX32
+
 config SOC_MAX32672
 	bool
 	select SOC_FAMILY_MAX32
@@ -39,6 +43,7 @@ config SOC_MAX32690_M4
 
 config SOC
 	default "max32655" if SOC_MAX32655
+	default "max32670" if SOC_MAX32670
 	default "max32672" if SOC_MAX32672
 	default "max32680" if SOC_MAX32680
 	default "max32690" if SOC_MAX32690

soc/adi/max32/soc.yml

@@ -7,6 +7,7 @@ family:
   - name: max32655
     cpuclusters:
     - name: m4
+  - name: max32670
   - name: max32672
   - name: max32680
     cpuclusters: