Browse Source

board: infineon: add XMC7200 Eval board support

- Support for kit_xmc72_evk

Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
Signed-off-by: Yurii Lozynskyi <yurii.lozynskyi@infineon.com>
pull/90771/head
Sreeram Tatapudi 1 month ago committed by Benjamin Cabé
parent
commit
b3067bde98
  1. 7
      boards/infineon/kit_xmc72_evk/Kconfig.kit_xmc72_evk
  2. 6
      boards/infineon/kit_xmc72_evk/board.cmake
  3. 6
      boards/infineon/kit_xmc72_evk/board.yml
  4. BIN
      boards/infineon/kit_xmc72_evk/doc/img/kit_xmc72_evk.webp
  5. 146
      boards/infineon/kit_xmc72_evk/doc/index.rst
  6. 109
      boards/infineon/kit_xmc72_evk/kit_xmc72_evk_common.dtsi
  7. 21
      boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m0p-pinctrl.dtsi
  8. 24
      boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m0p.dts
  9. 15
      boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m0p.yaml
  10. 24
      boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m0p_defconfig
  11. 31
      boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m7_0.dts
  12. 18
      boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m7_0.yaml
  13. 25
      boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m7_0_defconfig
  14. 31
      boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m7_1.dts
  15. 18
      boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m7_1.yaml
  16. 25
      boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m7_1_defconfig
  17. 15
      boards/infineon/kit_xmc72_evk/support/openocd.cfg
  18. 10
      dts/arm/infineon/cat1c/mpns/cyt4bf8cde.dtsi
  19. 10
      dts/arm/infineon/cat1c/mpns/cyt4bf8cds.dtsi
  20. 10
      dts/arm/infineon/cat1c/mpns/cyt4bf8cee.dtsi
  21. 10
      dts/arm/infineon/cat1c/mpns/cyt4bf8ces.dtsi
  22. 8
      dts/arm/infineon/cat1c/mpns/cyt4bfbche.dtsi
  23. 8
      dts/arm/infineon/cat1c/mpns/cyt4bfbchs.dtsi
  24. 8
      dts/arm/infineon/cat1c/mpns/cyt4bfbcje.dtsi
  25. 8
      dts/arm/infineon/cat1c/mpns/cyt4bfbcjs.dtsi
  26. 8
      dts/arm/infineon/cat1c/mpns/cyt4bfcche.dtsi
  27. 8
      dts/arm/infineon/cat1c/mpns/cyt4bfcchs.dtsi
  28. 8
      dts/arm/infineon/cat1c/mpns/cyt4bfccje.dtsi
  29. 8
      dts/arm/infineon/cat1c/mpns/cyt4bfccjs.dtsi
  30. 8
      dts/arm/infineon/cat1c/mpns/xmc7200_e272k8384.dtsi
  31. 10
      dts/arm/infineon/cat1c/mpns/xmc7200_f176k8384.dtsi
  32. 8
      dts/arm/infineon/cat1c/mpns/xmc7200d_e272k8384.dtsi
  33. 10
      dts/arm/infineon/cat1c/mpns/xmc7200d_f176k8384.dtsi
  34. 6
      dts/arm/infineon/cat1c/xmc7200/clock_source_def.h
  35. 37
      dts/arm/infineon/cat1c/xmc7200/memory_partition.dtsi
  36. 225
      dts/arm/infineon/cat1c/xmc7200/system_clocks.dtsi
  37. 1172
      dts/arm/infineon/cat1c/xmc7200/xmc7200.176-teqfp.dtsi
  38. 1392
      dts/arm/infineon/cat1c/xmc7200/xmc7200.272-bga.dtsi
  39. 1427
      dts/arm/infineon/cat1c/xmc7200/xmc7200.320-bga.dtsi
  40. 2349
      dts/arm/infineon/cat1c/xmc7200/xmc7200.dtsi
  41. 26
      dts/arm/infineon/cat1c/xmc7200/xmc7200_m0p.dtsi
  42. 38
      dts/arm/infineon/cat1c/xmc7200/xmc7200_m7.dtsi
  43. 7
      dts/bindings/arm/infineon,cat1-scb.yaml
  44. 8
      dts/bindings/counter/infineon,cat1-counter.yaml
  45. 7
      dts/bindings/dma/infineon,cat1-dma.yaml
  46. 7
      dts/bindings/gpio/infineon,cat1-gpio.yaml
  47. 11
      dts/bindings/misc/infineon,system-interrupts.yaml
  48. 9
      dts/bindings/pwm/infineon,cat1-pwm.yaml
  49. 8
      dts/bindings/sdhc/infineon,cat1-sdhc-sdio.yaml
  50. 11
      dts/bindings/serial/infineon,cat1-uart.yaml
  51. 8
      dts/bindings/watchdog/infineon,cat1-watchdog.yaml
  52. 6
      modules/hal_infineon/mtb-hal-cat1/CMakeLists.txt
  53. 21
      modules/hal_infineon/mtb-pdl-cat1/CMakeLists.txt
  54. 12
      modules/hal_infineon/mtb-template-cat1/CMakeLists.txt
  55. 5
      soc/infineon/cat1c/CMakeLists.txt
  56. 9
      soc/infineon/cat1c/Kconfig
  57. 10
      soc/infineon/cat1c/Kconfig.defconfig
  58. 14
      soc/infineon/cat1c/Kconfig.soc
  59. 4
      soc/infineon/cat1c/common/CMakeLists.txt
  60. 129
      soc/infineon/cat1c/common/pinctrl_soc.h
  61. 27
      soc/infineon/cat1c/soc.yml
  62. 15
      soc/infineon/cat1c/xmc7200/CMakeLists.txt
  63. 25
      soc/infineon/cat1c/xmc7200/Kconfig
  64. 20
      soc/infineon/cat1c/xmc7200/Kconfig.defconfig
  65. 139
      soc/infineon/cat1c/xmc7200/Kconfig.soc
  66. 34
      soc/infineon/cat1c/xmc7200/soc.h
  67. 30
      soc/infineon/cat1c/xmc7200/soc_m0p.c
  68. 150
      soc/infineon/cat1c/xmc7200/soc_m7.c
  69. 3
      tests/arch/arm/arm_irq_advanced_features/testcase.yaml
  70. 3
      tests/arch/arm/arm_irq_zero_latency_levels/testcase.yaml
  71. 2
      west.yml

7
boards/infineon/kit_xmc72_evk/Kconfig.kit_xmc72_evk

@ -0,0 +1,7 @@ @@ -0,0 +1,7 @@
# Copyright (c) 2025 Cypress Semiconductor Corporation.
# SPDX-License-Identifier: Apache-2.0
config BOARD_KIT_XMC72_EVK
select SOC_XMC7200D_E272K8384_M0PLUS if BOARD_KIT_XMC72_EVK_XMC7200D_E272K8384_M0P
select SOC_XMC7200D_E272K8384_M7_0 if BOARD_KIT_XMC72_EVK_XMC7200D_E272K8384_M7_0
select SOC_XMC7200D_E272K8384_M7_1 if BOARD_KIT_XMC72_EVK_XMC7200D_E272K8384_M7_1

6
boards/infineon/kit_xmc72_evk/board.cmake

@ -0,0 +1,6 @@ @@ -0,0 +1,6 @@
# Copyright (c) 2025 Cypress Semiconductor Corporation.
# SPDX-License-Identifier: Apache-2.0
# Connect to CM0P core.
board_runner_args(openocd "--target-handle=cat1c.cpu.cm0")
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)

6
boards/infineon/kit_xmc72_evk/board.yml

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board:
name: kit_xmc72_evk
full_name: XMC7200 Evaluation Kit
vendor: infineon
socs:
- name: xmc7200d_e272k8384

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boards/infineon/kit_xmc72_evk/doc/img/kit_xmc72_evk.webp

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146
boards/infineon/kit_xmc72_evk/doc/index.rst

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.. zephyr:board:: kit_xmc72_evk
Overview
********
The XMC7200 evaluation kit enables you to evaluate and develop your applications using the XMC7200D
microcontroller(hereafter called “XMC7200D”). The XMC7200D is designed for industrial applications
and it is a true programmable embedded system-on-chip, integrating up to two 350-MHz Arm® Cortex®-M7
as the primary application processor, a 100-MHz Arm® Cortex®-M0+ that supports the following:
- Low-power operations
- Up to 8 MB flash and 1 MB SRAM
- Gigabit Ethernet
- CAN FD
- Secure Digital Host Controller (SDHC) supporting SD/SDIO/eMMC interfaces
- Programmable analog and digital peripherals that allow faster time-to-market
The evaluation board has a M.2 interface connector for interfacing radio modules-based on
AIROC™ Wi-Fi & Bluetooth combos, SMIF dual header compatible with Digilent Pmod for interfacing
HYPERBUS™ memories, and headers compatible with Arduino for interfacing Arduino shields.
In addition, the board features an onboard programmer/debugger(KitProg3), a 512-Mbit QSPI NOR flash,
CAN FD transceiver, Gigabit Ethernet PHY transceiver with RJ45 connector interface, a micro-B
connector for USB device interface, three user LEDs, one potentiometer, and two push buttons.
The board supports operating voltages from 3.3 V to 5.0 V for XMC7200D.
Hardware
********
For more information about XMC7200D and KIT_XMC72_EVK:
- `XMC7200D SoC Website`_
- `kit_xmc72_evk Board Website`_
Kit Features
=============
- Evaluation board for XMC7200D-E272K8384 in BGA package with 272 pins, dual-core Arm®Cortex® M7 CPUs running at 350-MHz and an Arm® Cortex® M0+ CPU running at 100-MHz
- Full-system approach on the board, featuring Gigabit Ethernet PHY and connector, CAN FD transceiver, user LEDs, buttons, and potentiometer
- M.2 interface connector for interfacing radio modules based on AIROC™ Wi-Fi & Bluetooth®combos (currently not - supported)
- Headers compatible with Arduino for interfacing Arduino shields
- Fully compatible with ModusToolbox™ v3.0
- KitProg3 on-board SWD programmer/debugger, USB-UART, and USB-I2C bridge functionality through USB connector
- Digilent dual PMOD SMIF header for interfacing HYPERBUS™ memories (currently not supported)
- A 512-Mbit external QSPI NOR flash
- Evaluation board supports operating voltages from 3.3 V to 5.0 V for XMC7200D
Kit Contents
=============
- XMC7200 evaluation board
- USB Type-A to Mirco-B cable
- 12V/3A DC power adapter with additional blades
- Six jumper wires (five inches each)
- Quick start guide
Supported Features
==================
.. zephyr:board-supported-hw::
Programming and Debugging
*************************
.. zephyr:board-supported-runners::
Building
========
Here is an example for building the :zephyr:code-sample:`blinky` sample application.
.. zephyr-app-commands::
:zephyr-app: samples/basic/blinky
:board: kit_xmc72_evk
:goals: build
Flashing
========
The KIT_XMC72_EVK includes an onboard programmer/debugger (`KitProg3`_) to provide debugging, flash programming, and serial communication over USB. Flash and debug commands use OpenOCD and require a custom Infineon OpenOCD version, that supports KitProg3, to be installed.
Infineon OpenOCD Installation
=============================
Both the full `ModusToolbox`_ and the `ModusToolbox Programming Tools`_ packages include Infineon OpenOCD.
Installing either of these packages will also install Infineon OpenOCD.
If neither package is installed, a minimal installation can be done by downloading the `Infineon OpenOCD`_ release for your system and manually extract the files to a location of your choice.
.. note:: Linux requires device access rights to be set up for KitProg3. This is handled automatically by the ModusToolbox and ModusToolbox Programming Tools installations. When doing a minimal installation, this can be done manually by executing the script ``openocd/udev_rules/install_rules.sh``.
West Commands
=============
The path to the installed Infineon OpenOCD executable must be available to the ``west`` tool commands. There are multiple ways of doing this. The example below uses a permanent CMake argument to set the CMake variable ``OPENOCD``.
.. tabs::
.. group-tab:: Windows
.. code-block:: shell
# Run west config once to set permanent CMake argument
west config build.cmake-args -- -DOPENOCD=path/to/infineon/openocd/bin/openocd.exe
# Do a pristine build once after setting CMake argument
west build -b kit_xmc72_evk -p always samples/basic/blinky
west flash
west debug
.. group-tab:: Linux
.. code-block:: shell
# Run west config once to set permanent CMake argument
west config build.cmake-args -- -DOPENOCD=path/to/infineon/openocd/bin/openocd
# Do a pristine build once after setting CMake argument
west build -b kit_xmc72_evk -p always samples/basic/blinky
west flash
west debug
Once the gdb console starts after executing the west debug command, you may now set breakpoints and perform other standard GDB debugging.
References
**********
.. target-notes::
.. _XMC7200D SoC Website:
https://www.infineon.com/cms/en/product/microcontroller/32-bit-industrial-microcontroller-based-on-arm-cortex-m/32-bit-xmc7000-industrial-microcontroller-arm-cortex-m7/xmc7200d-e272k8384aa/
.. _kit_xmc72_evk Board Website:
https://www.infineon.com/cms/en/product/evaluation-boards/kit_xmc72_evk
.. _ModusToolbox:
https://softwaretools.infineon.com/tools/com.ifx.tb.tool.modustoolbox
.. _ModusToolbox Programming Tools:
https://softwaretools.infineon.com/tools/com.ifx.tb.tool.modustoolboxprogtools
.. _Infineon OpenOCD:
https://github.com/Infineon/openocd/releases/latest
.. _KitProg3:
https://github.com/Infineon/KitProg3

109
boards/infineon/kit_xmc72_evk/kit_xmc72_evk_common.dtsi

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/*
* Copyright (c) 2025 Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*/
#include <arm/infineon/cat1c/xmc7200/system_clocks.dtsi>
#include <arm/infineon/cat1c/mpns/xmc7200_e272k8384.dtsi>
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
aliases {
uart-3 = &uart3;
led0 = &user_led0;
led1 = &user_led1;
led2 = &user_led2;
sw0 = &user_bt0;
sw1 = &user_bt1;
};
leds {
compatible = "gpio-leds";
user_led0: led_0 {
label = "LED_0";
gpios = <&gpio_prt16 1 GPIO_ACTIVE_LOW>;
};
user_led1: led_1 {
label = "LED_1";
gpios = <&gpio_prt16 2 GPIO_ACTIVE_LOW>;
};
user_led2: led_2 {
label = "LED_2";
gpios = <&gpio_prt16 3 GPIO_ACTIVE_LOW>;
};
};
gpio_keys {
compatible = "gpio-keys";
user_bt0: user_btn0 {
label = "SW_1";
gpios = <&gpio_prt21 4 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
zephyr,code = <INPUT_KEY_0>;
};
user_bt1: user_btn1 {
label = "SW_2";
gpios = <&gpio_prt17 3 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
zephyr,code = <INPUT_KEY_1>;
};
};
};
uart3: &scb3 {
compatible = "infineon,cat1-uart";
status = "okay";
current-speed = <115200>;
/* UART pins */
pinctrl-0 = <&p13_1_scb3_uart_tx &p13_0_scb3_uart_rx
&p13_2_scb3_uart_rts &p13_3_scb3_uart_cts>;
pinctrl-names = "default";
};
&gpio_prt13 {
status = "okay";
};
&gpio_prt16 {
status = "okay";
};
&gpio_prt21 {
status = "okay";
};
&gpio_prt17 {
status = "okay";
};
&path_mux0 {
status = "okay";
};
&path_mux1 {
status = "okay";
};
&path_mux2 {
status = "okay";
};
&path_mux3 {
status = "okay";
};
&clk_mem {
status = "okay";
};
&clk_peri {
status = "okay";
};
&clk_slow {
status = "okay";
};

21
boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m0p-pinctrl.dtsi

@ -0,0 +1,21 @@ @@ -0,0 +1,21 @@
/*
* Copyright (c) 2024 Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*/
/* Configure pin control bias mode for uart2 pins */
&p13_1_scb3_uart_tx {
drive-push-pull;
};
&p13_0_scb3_uart_rx {
input-enable;
};
&p13_2_scb3_uart_rts {
drive-push-pull;
};
&p13_3_scb3_uart_cts {
input-enable;
};

24
boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m0p.dts

@ -0,0 +1,24 @@ @@ -0,0 +1,24 @@
/*
* Copyright (c) 2025 Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*/
/dts-v1/;
#include <arm/infineon/cat1c/mpns/xmc7200_e272k8384.dtsi>
#include <arm/infineon/cat1c/xmc7200/system_clocks.dtsi>
#include <arm/infineon/cat1c/xmc7200/xmc7200_m0p.dtsi>
#include <arm/infineon/cat1c/xmc7200/memory_partition.dtsi>
#include "kit_xmc72_evk_xmc7200d_e272k8384_m0p-pinctrl.dtsi"
#include "kit_xmc72_evk_common.dtsi"
/ {
model = "Infineon Evaluation board for XMC7200D-E272K8384 M0";
compatible = "infineon,kit_xmc72_evk", "infineon,XMC7200";
chosen {
zephyr,sram = &m0p_code;
zephyr,flash = &m0p_data;
zephyr,console = &uart3;
zephyr,shell-uart = &uart3;
};
};

15
boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m0p.yaml

@ -0,0 +1,15 @@ @@ -0,0 +1,15 @@
#
# Copyright (c) 2025 Cypress Semiconductor Corporation.
# SPDX-License-Identifier: Apache-2.0
#
identifier: kit_xmc72_evk/xmc7200d_e272k8384/m0p
name: XMC7200 Evaluation Kit (M0P)
type: mcu
arch: arm
ram: 1024
flash: 8384
toolchain:
- zephyr
- gnuarmemb
vendor: infineon

24
boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m0p_defconfig

@ -0,0 +1,24 @@ @@ -0,0 +1,24 @@
#
# Copyright (c) 2025 Cypress Semiconductor Corporation.
# SPDX-License-Identifier: Apache-2.0
#
# General configuration
CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_BUILD_OUTPUT_BIN=y
CONFIG_ARM_MPU=y
CONFIG_HW_STACK_PROTECTION=y
# Enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# Enable UART driver
CONFIG_SERIAL=y
# Enable GPIO driver
CONFIG_GPIO=y
# Enable clock controller
CONFIG_CLOCK_CONTROL=y

31
boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m7_0.dts

@ -0,0 +1,31 @@ @@ -0,0 +1,31 @@
/*
* Copyright (c) 2021 Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*/
/dts-v1/;
#include <arm/infineon/cat1c/mpns/xmc7200_e272k8384.dtsi>
#include <arm/infineon/cat1c/xmc7200/system_clocks.dtsi>
#include <arm/infineon/cat1c/xmc7200/xmc7200_m7.dtsi>
#include <arm/infineon/cat1c/xmc7200/memory_partition.dtsi>
#include "kit_xmc72_evk_xmc7200d_e272k8384_m0p-pinctrl.dtsi"
#include "kit_xmc72_evk_common.dtsi"
/ {
model = "Infineon Evaluation board for XMC7200D-E272K8384 M7";
compatible = "infineon,kit_xmc72_evk", "infineon,XMC7200";
aliases {
uart-3 = &uart3;
};
chosen {
zephyr,sram = &cm7_0_code;
zephyr,flash = &cm7_0_data;
zephyr,dtcm = &dtcm;
zephyr,itcm = &itcm;
zephyr,console = &uart3;
zephyr,shell-uart = &uart3;
};
};

18
boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m7_0.yaml

@ -0,0 +1,18 @@ @@ -0,0 +1,18 @@
#
# Copyright (c) 2025 Cypress Semiconductor Corporation.
# SPDX-License-Identifier: Apache-2.0
#
identifier: kit_xmc72_evk/xmc7200d_e272k8384/m7_0
name: XMC7200 Evaluation Kit (M7_0)
type: mcu
arch: arm
ram: 1024
flash: 8384
toolchain:
- zephyr
- gnuarmemb
supported:
- gpio
- uart
vendor: infineon

25
boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m7_0_defconfig

@ -0,0 +1,25 @@ @@ -0,0 +1,25 @@
#
# Copyright (c) 2025 Cypress Semiconductor Corporation.
# SPDX-License-Identifier: Apache-2.0
#
# General configuration
CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_BUILD_OUTPUT_BIN=y
CONFIG_ARM_MPU=y
CONFIG_HW_STACK_PROTECTION=y
CONFIG_CACHE_MANAGEMENT=y
# Enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# Enable UART driver
CONFIG_SERIAL=y
# Enable GPIO driver
CONFIG_GPIO=y
# Enable clock controller
CONFIG_CLOCK_CONTROL=y

31
boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m7_1.dts

@ -0,0 +1,31 @@ @@ -0,0 +1,31 @@
/*
* Copyright (c) 2021 Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*/
/dts-v1/;
#include <arm/infineon/cat1c/mpns/xmc7200_e272k8384.dtsi>
#include <arm/infineon/cat1c/xmc7200/system_clocks.dtsi>
#include <arm/infineon/cat1c/xmc7200/xmc7200_m7.dtsi>
#include <arm/infineon/cat1c/xmc7200/memory_partition.dtsi>
#include "kit_xmc72_evk_xmc7200d_e272k8384_m0p-pinctrl.dtsi"
#include "kit_xmc72_evk_common.dtsi"
/ {
model = "Infineon Evaluation board for XMC7200D-E272K8384 M7";
compatible = "infineon,kit_xmc72_evk", "infineon,XMC7200";
aliases {
uart-3 = &uart3;
};
chosen {
zephyr,sram = &cm7_1_code;
zephyr,flash = &cm7_1_data;
zephyr,dtcm = &dtcm;
zephyr,itcm = &itcm;
zephyr,console = &uart3;
zephyr,shell-uart = &uart3;
};
};

18
boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m7_1.yaml

@ -0,0 +1,18 @@ @@ -0,0 +1,18 @@
#
# Copyright (c) 2025 Cypress Semiconductor Corporation.
# SPDX-License-Identifier: Apache-2.0
#
identifier: kit_xmc72_evk/xmc7200d_e272k8384/m7_1
name: XMC7200 Evaluation Kit (M7_1)
type: mcu
arch: arm
ram: 1024
flash: 2048
toolchain:
- zephyr
- gnuarmemb
supported:
- gpio
- uart
vendor: infineon

25
boards/infineon/kit_xmc72_evk/kit_xmc72_evk_xmc7200d_e272k8384_m7_1_defconfig

@ -0,0 +1,25 @@ @@ -0,0 +1,25 @@
#
# Copyright (c) 2025 Cypress Semiconductor Corporation.
# SPDX-License-Identifier: Apache-2.0
#
# General configuration
CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_BUILD_OUTPUT_BIN=y
CONFIG_ARM_MPU=y
CONFIG_HW_STACK_PROTECTION=y
CONFIG_CACHE_MANAGEMENT=y
# Enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# Enable UART driver
CONFIG_SERIAL=y
# Enable GPIO driver
CONFIG_GPIO=y
# Enable clock controller
CONFIG_CLOCK_CONTROL=y

15
boards/infineon/kit_xmc72_evk/support/openocd.cfg

@ -0,0 +1,15 @@ @@ -0,0 +1,15 @@
# Copyright (c) 2025 Cypress Semiconductor Corporation.
# SPDX-License-Identifier: Apache-2.0
if {[info exists env(OPENOCD_INTERFACE)]} {
set INTERFACE $env(OPENOCD_INTERFACE)
} else {
#default connect over Debug USB port
set INTERFACE "cmsis-dap"
}
source [find interface/$INTERFACE.cfg]
transport select swd
source [find target/cat1c.cfg]

10
dts/arm/infineon/cat1c/mpns/cyt4bf8cde.dtsi

@ -0,0 +1,10 @@ @@ -0,0 +1,10 @@
/*
* Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "../xmc7200/xmc7200.176-teqfp.dtsi"
/delete-node/ &scb10;

10
dts/arm/infineon/cat1c/mpns/cyt4bf8cds.dtsi

@ -0,0 +1,10 @@ @@ -0,0 +1,10 @@
/*
* Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "../xmc7200/xmc7200.176-teqfp.dtsi"
/delete-node/ &scb10;

10
dts/arm/infineon/cat1c/mpns/cyt4bf8cee.dtsi

@ -0,0 +1,10 @@ @@ -0,0 +1,10 @@
/*
* Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "../xmc7200/xmc7200.176-teqfp.dtsi"
/delete-node/ &scb10;

10
dts/arm/infineon/cat1c/mpns/cyt4bf8ces.dtsi

@ -0,0 +1,10 @@ @@ -0,0 +1,10 @@
/*
* Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "../xmc7200/xmc7200.176-teqfp.dtsi"
/delete-node/ &scb10;

8
dts/arm/infineon/cat1c/mpns/cyt4bfbche.dtsi

@ -0,0 +1,8 @@ @@ -0,0 +1,8 @@
/*
* Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "../xmc7200/xmc7200.272-bga.dtsi"

8
dts/arm/infineon/cat1c/mpns/cyt4bfbchs.dtsi

@ -0,0 +1,8 @@ @@ -0,0 +1,8 @@
/*
* Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "../xmc7200/xmc7200.272-bga.dtsi"

8
dts/arm/infineon/cat1c/mpns/cyt4bfbcje.dtsi

@ -0,0 +1,8 @@ @@ -0,0 +1,8 @@
/*
* Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "../xmc7200/xmc7200.272-bga.dtsi"

8
dts/arm/infineon/cat1c/mpns/cyt4bfbcjs.dtsi

@ -0,0 +1,8 @@ @@ -0,0 +1,8 @@
/*
* Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "../xmc7200/xmc7200.272-bga.dtsi"

8
dts/arm/infineon/cat1c/mpns/cyt4bfcche.dtsi

@ -0,0 +1,8 @@ @@ -0,0 +1,8 @@
/*
* Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "../xmc7200/xmc7200.320-bga.dtsi"

8
dts/arm/infineon/cat1c/mpns/cyt4bfcchs.dtsi

@ -0,0 +1,8 @@ @@ -0,0 +1,8 @@
/*
* Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "../xmc7200/xmc7200.320-bga.dtsi"

8
dts/arm/infineon/cat1c/mpns/cyt4bfccje.dtsi

@ -0,0 +1,8 @@ @@ -0,0 +1,8 @@
/*
* Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "../xmc7200/xmc7200.320-bga.dtsi"

8
dts/arm/infineon/cat1c/mpns/cyt4bfccjs.dtsi

@ -0,0 +1,8 @@ @@ -0,0 +1,8 @@
/*
* Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "../xmc7200/xmc7200.320-bga.dtsi"

8
dts/arm/infineon/cat1c/mpns/xmc7200_e272k8384.dtsi

@ -0,0 +1,8 @@ @@ -0,0 +1,8 @@
/*
* Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "../xmc7200/xmc7200.272-bga.dtsi"

10
dts/arm/infineon/cat1c/mpns/xmc7200_f176k8384.dtsi

@ -0,0 +1,10 @@ @@ -0,0 +1,10 @@
/*
* Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "../xmc7200/xmc7200.176-teqfp.dtsi"
/delete-node/ &scb10;

8
dts/arm/infineon/cat1c/mpns/xmc7200d_e272k8384.dtsi

@ -0,0 +1,8 @@ @@ -0,0 +1,8 @@
/*
* Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "../xmc7200/xmc7200.272-bga.dtsi"

10
dts/arm/infineon/cat1c/mpns/xmc7200d_f176k8384.dtsi

@ -0,0 +1,10 @@ @@ -0,0 +1,10 @@
/*
* Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "../xmc7200/xmc7200.176-teqfp.dtsi"
/delete-node/ &scb10;

6
dts/arm/infineon/cat1c/xmc7200/clock_source_def.h

@ -0,0 +1,6 @@ @@ -0,0 +1,6 @@
/*
* Copyright (c) 2024, Cypress Semiconductor
* SPDX-License-Identifier: Apache-2.0
*/
#define CLK_SOURCE_IMO

37
dts/arm/infineon/cat1c/xmc7200/memory_partition.dtsi

@ -0,0 +1,37 @@ @@ -0,0 +1,37 @@
/ {
m0p_code: m0p_code@28000800 {
compatible = "mmio-sram";
reg = <0x28000800 DT_SIZE_K(16)>;
};
m0p_data: m0p_data@10000000 {
compatible = "soc-nv-flash";
reg = <0x10000000 DT_SIZE_K(512)>;
write-block-size = <512>;
erase-block-size = <512>;
};
cm7_0_code: cm7_0_code@28004000 {
compatible = "mmio-sram";
reg = <0x28004000 DT_SIZE_K(816)>;
};
cm7_0_data: cm7_0_data@10080000 {
compatible = "soc-nv-flash";
reg = <0x10080000 DT_SIZE_K(2048)>;
write-block-size = <512>;
erase-block-size = <512>;
};
cm7_1_code: cm7_1_code@280d0000 {
compatible = "mmio-sram";
reg = <0x280d0000 DT_SIZE_K(64)>;
};
cm7_1_data: cm7_1_data@10280000 {
compatible = "soc-nv-flash";
reg = <0x10280000 DT_SIZE_K(5824)>;
write-block-size = <512>;
erase-block-size = <512>;
};
};

225
dts/arm/infineon/cat1c/xmc7200/system_clocks.dtsi

@ -0,0 +1,225 @@ @@ -0,0 +1,225 @@
/*
* Copyright (c) 2024 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "clock_source_def.h"
/ {
clocks {
/* imo */
clk_imo: clk_imo {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <8000000>;
status = "okay";
};
/* eco */
clk_eco: clk_eco {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <16000000>;
status = "okay";
};
/* fll */
fll0: fll0 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <100000000>;
status = "okay";
};
/* pll400m0 */
clk_pll400m0: clk_pll400m0 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <350000000>;
status = "okay";
};
/* pll400m1 */
clk_pll400m1: clk_pll400m1 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <250000000>;
status = "okay";
};
/* pll200m0 */
clk_pll200m0: clk_pll200m0 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <200000000>;
status = "okay";
};
/* pll200m1 */
clk_pll200m1: clk_pll200m1 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <100000000>;
status = "okay";
};
/* path mux0 */
path_mux0: path_mux0 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&clk_eco>;
status = "disabled";
};
/* path mux1 */
path_mux1: path_mux1 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&clk_eco>;
status = "disabled";
};
/* path mux2 */
path_mux2: path_mux2 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&clk_eco>;
status = "disabled";
};
/* path mux3 */
path_mux3: path_mux3 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&clk_eco>;
status = "disabled";
};
/* path mux4 */
path_mux4: path_mux4 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&clk_eco>;
status = "disabled";
};
/* clk_hf0 */
clk_hf0: clk_hf0 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <1>;
clocks = <&clk_pll200m0>;
status = "okay";
};
/* clk_hf1 */
clk_hf1: clk_hf1 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <1>;
clocks = <&clk_pll400m0>;
status = "okay";
};
/* clk_hf2 */
clk_hf2: clk_hf2 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <1>;
clocks = <&clk_pll200m1>;
status = "okay";
};
/* clk_hf3 */
clk_hf3: clk_hf3 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <1>;
clocks = <&path_mux3>;
status = "disabled";
};
/* clk_hf4 */
clk_hf4: clk_hf4 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <1>;
clocks = <&path_mux4>;
status = "disabled";
};
/* clk_hf5 */
clk_hf5: clk_hf5 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <1>;
clocks = <&path_mux3>;
status = "disabled";
};
/* clk_hf6 */
clk_hf6: clk_hf6 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <1>;
clocks = <&path_mux4>;
status = "disabled";
};
/* clk_hf7 */
clk_hf7: clk_hf7 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <1>;
clocks = <&path_mux4>;
status = "disabled";
};
/* clk_fast0 */
clk_fast0: clk_fast0 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <1>;
clocks = <&clk_hf1>;
status = "okay";
};
/* clk_fast1 */
clk_fast1: clk_fast1 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <1>;
clocks = <&clk_hf1>;
status = "okay";
};
/* clk_mem */
clk_mem: clk_mem {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <1>;
clocks = <&clk_hf0>;
status = "disabled";
};
/* clk_peri */
clk_peri: clk_peri {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <2>;
clocks = <&clk_hf0>;
status = "disabled";
};
/* clk_slow */
clk_slow: clk_slow {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <2>;
clocks = <&clk_mem>;
status = "disabled";
};
};
};

1172
dts/arm/infineon/cat1c/xmc7200/xmc7200.176-teqfp.dtsi

File diff suppressed because it is too large Load Diff

1392
dts/arm/infineon/cat1c/xmc7200/xmc7200.272-bga.dtsi

File diff suppressed because it is too large Load Diff

1427
dts/arm/infineon/cat1c/xmc7200/xmc7200.320-bga.dtsi

File diff suppressed because it is too large Load Diff

2349
dts/arm/infineon/cat1c/xmc7200/xmc7200.dtsi

File diff suppressed because it is too large Load Diff

26
dts/arm/infineon/cat1c/xmc7200/xmc7200_m0p.dtsi

@ -0,0 +1,26 @@ @@ -0,0 +1,26 @@
/*
* Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <arm/armv6-m.dtsi>
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m0+";
reg = <0>;
clock-frequency = <100000000>;
};
};
};
&nvic {
arm,num-irq-priority-bits = <2>;
};

38
dts/arm/infineon/cat1c/xmc7200/xmc7200_m7.dtsi

@ -0,0 +1,38 @@ @@ -0,0 +1,38 @@
/*
* Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <arm/armv7-m.dtsi>
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m7";
reg = <0>;
clock-frequency = <350000000>;
};
};
dtcm: dtcm@20000000 {
compatible = "zephyr,memory-region", "arm,dtcm";
reg = <0x20000000 DT_SIZE_K(16)>;
zephyr,memory-region = "DTCM";
};
itcm: itcm@0 {
compatible = "zephyr,memory-region", "arm,itcm";
reg = <0x00000000 DT_SIZE_K(16)>;
zephyr,memory-region = "ITCM";
};
};
&nvic {
arm,num-irq-priority-bits = <3>;
};

7
dts/bindings/arm/infineon,cat1-scb.yaml

@ -7,11 +7,14 @@ description: Infineon Serial Communication Blocks (SCB) node @@ -7,11 +7,14 @@ description: Infineon Serial Communication Blocks (SCB) node
compatible: "infineon,cat1-scb"
include: [base.yaml]
include: [base.yaml, "infineon,system-interrupts.yaml"]
properties:
reg:
required: true
interrupts:
required: true
description: Required for non-cat1c devices
system-interrupts:
description: Required for cat1c devices

8
dts/bindings/counter/infineon,cat1-counter.yaml

@ -7,7 +7,7 @@ description: Infineon counters @@ -7,7 +7,7 @@ description: Infineon counters
compatible: "infineon,cat1-counter"
include: base.yaml
include: [base.yaml, "infineon,system-interrupts.yaml"]
properties:
resolution:
@ -25,3 +25,9 @@ properties: @@ -25,3 +25,9 @@ properties:
type: phandle-array
description: |
External trigger that runs counter
interrupts:
description: Required for non-cat1c devices
system-interrupts:
description: Required for cat1c devices

7
dts/bindings/dma/infineon,cat1-dma.yaml

@ -7,14 +7,17 @@ description: Infineon CAT1 DMA @@ -7,14 +7,17 @@ description: Infineon CAT1 DMA
compatible: "infineon,cat1-dma"
include: dma-controller.yaml
include: [dma-controller.yaml, "infineon,system-interrupts.yaml"]
properties:
reg:
required: true
interrupts:
required: true
description: Required for non-cat1c devices
system-interrupts:
description: Required for cat1c devices
"#dma-cells":
const: 1

7
dts/bindings/gpio/infineon,cat1-gpio.yaml

@ -8,14 +8,17 @@ description: Infineon CAT1 GPIO Port @@ -8,14 +8,17 @@ description: Infineon CAT1 GPIO Port
compatible: "infineon,cat1-gpio"
include: ["gpio-controller.yaml", "base.yaml"]
include: [gpio-controller.yaml, base.yaml, "infineon,system-interrupts.yaml"]
properties:
reg:
required: true
interrupts:
required: true
description: Required for non-cat1c devices
system-interrupts:
description: Required for cat1c devices
"#gpio-cells":
const: 2

11
dts/bindings/misc/infineon,system-interrupts.yaml

@ -0,0 +1,11 @@ @@ -0,0 +1,11 @@
# Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
# an affiliate of Cypress Semiconductor Corporation
#
# SPDX-License-Identifier: Apache-2.0
properties:
system-interrupts:
type: array
description: |
Information about system interrupts generated by the device (peripherals, etc), encoded
as an array of one or more interrupt specifiers.

9
dts/bindings/pwm/infineon,cat1-pwm.yaml

@ -3,11 +3,11 @@ @@ -3,11 +3,11 @@
#
# SPDX-License-Identifier: Apache-2.0
description: Infineon Cat1 PWM
description: Infineon CAT1 PWM
compatible: "infineon,cat1-pwm"
include: [pwm-controller.yaml, pinctrl-device.yaml]
include: [pwm-controller.yaml, pinctrl-device.yaml, "infineon,system-interrupts.yaml"]
properties:
reg:
@ -16,7 +16,10 @@ properties: @@ -16,7 +16,10 @@ properties:
interrupts:
type: array
required: true
description: Required for non-cat1c devices
system-interrupts:
description: Required for cat1c devices
pinctrl-0:
description: |

8
dts/bindings/sdhc/infineon,cat1-sdhc-sdio.yaml

@ -7,7 +7,7 @@ description: Infineon CAT1 SDHC/SDIO controller @@ -7,7 +7,7 @@ description: Infineon CAT1 SDHC/SDIO controller
compatible: "infineon,cat1-sdhc-sdio"
include: [sdhc.yaml, pinctrl-device.yaml]
include: [sdhc.yaml, pinctrl-device.yaml, "infineon,system-interrupts.yaml"]
properties:
reg:
@ -18,3 +18,9 @@ properties: @@ -18,3 +18,9 @@ properties:
pinctrl-names:
required: true
interrupts:
description: Required for non-cat1c devices
system-interrupts:
description: Required for cat1c devices

11
dts/bindings/serial/infineon,cat1-uart.yaml

@ -9,14 +9,21 @@ description: Infineon CAT1 UART @@ -9,14 +9,21 @@ description: Infineon CAT1 UART
compatible: "infineon,cat1-uart"
include: [uart-controller.yaml, pinctrl-device.yaml, "infineon,cat1-scb.yaml"]
include:
- name: uart-controller.yaml
- name: pinctrl-device.yaml
- name: "infineon,cat1-scb.yaml"
- name: "infineon,system-interrupts.yaml"
properties:
reg:
required: true
interrupts:
required: true
description: Required for non-cat1c devices
system-interrupts:
description: Required for cat1c devices
pinctrl-0:
description: |

8
dts/bindings/watchdog/infineon,cat1-watchdog.yaml

@ -7,8 +7,14 @@ description: Infineon CAT1 Watchdog @@ -7,8 +7,14 @@ description: Infineon CAT1 Watchdog
compatible: "infineon,cat1-watchdog"
include: base.yaml
include: [base.yaml, "infineon,system-interrupts.yaml"]
properties:
reg:
required: true
interrupts:
description: Required for non-cat1c devices
system-interrupts:
description: Required for cat1c devices

6
modules/hal_infineon/mtb-hal-cat1/CMakeLists.txt

@ -6,10 +6,12 @@ @@ -6,10 +6,12 @@
set(hal_dir ${ZEPHYR_HAL_INFINEON_MODULE_DIR}/mtb-hal-cat1)
set(hal_cat1a_dir ${hal_dir}/COMPONENT_CAT1A)
set(hal_cat1b_dir ${hal_dir}/COMPONENT_CAT1B)
set(hal_cat1c_dir ${hal_dir}/COMPONENT_CAT1C)
# PSOC 6 family defines
zephyr_compile_definitions_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1A COMPONENT_CAT1A)
zephyr_compile_definitions_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1B COMPONENT_CAT1B)
zephyr_compile_definitions_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1C COMPONENT_CAT1C)
zephyr_compile_definitions_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1 COMPONENT_CAT1)
zephyr_compile_definitions_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1 CY_USING_HAL)
@ -18,6 +20,7 @@ zephyr_include_directories(${hal_dir}/include) @@ -18,6 +20,7 @@ zephyr_include_directories(${hal_dir}/include)
zephyr_include_directories(${hal_dir}/include_pvt)
zephyr_include_directories_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1A ${hal_cat1a_dir}/include)
zephyr_include_directories_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1B ${hal_cat1b_dir}/include)
zephyr_include_directories_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1C ${hal_cat1c_dir}/include)
# Packages sources
zephyr_library_sources_ifdef(CONFIG_SOC_PACKAGE_PSOC6_01_104_M_CSP_BLE
@ -60,6 +63,9 @@ zephyr_library_sources_ifdef(CONFIG_SOC_PACKAGE_PSOC6_04_80_TQFP @@ -60,6 +63,9 @@ zephyr_library_sources_ifdef(CONFIG_SOC_PACKAGE_PSOC6_04_80_TQFP
zephyr_library_sources_ifdef(CONFIG_SOC_PACKAGE_CYW20829_56_QFN
${hal_cat1b_dir}/source/pin_packages/cyhal_cyw20829_56_qfn.c)
zephyr_library_sources_ifdef(CONFIG_SOC_PACKAGE_XMC7200_272_BGA
${hal_cat1c_dir}/source/pin_packages/cyhal_xmc7200_272_bga.c)
zephyr_library_sources_ifdef(CONFIG_SOC_DIE_CYW20829
${hal_cat1b_dir}/source/triggers/cyhal_triggers_cyw20829.c)

21
modules/hal_infineon/mtb-pdl-cat1/CMakeLists.txt

@ -7,6 +7,7 @@ set(pdl_dir ${ZEPHYR_HAL_INFINEON_MODULE_DIR}/mtb-pdl-cat1) @@ -7,6 +7,7 @@ set(pdl_dir ${ZEPHYR_HAL_INFINEON_MODULE_DIR}/mtb-pdl-cat1)
set(pdl_drv_dir ${ZEPHYR_HAL_INFINEON_MODULE_DIR}/mtb-pdl-cat1/drivers)
set(pdl_dev_cat1a_dir ${ZEPHYR_HAL_INFINEON_MODULE_DIR}/mtb-pdl-cat1/devices/COMPONENT_CAT1A)
set(pdl_dev_cat1b_dir ${ZEPHYR_HAL_INFINEON_MODULE_DIR}/mtb-pdl-cat1/devices/COMPONENT_CAT1B)
set(pdl_dev_cat1c_dir ${ZEPHYR_HAL_INFINEON_MODULE_DIR}/mtb-pdl-cat1/devices/COMPONENT_CAT1C)
# Generate PDL specific SOC defines
@ -23,16 +24,21 @@ zephyr_include_directories_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1A ${pdl_dev_cat1 @@ -23,16 +24,21 @@ zephyr_include_directories_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1A ${pdl_dev_cat1
zephyr_include_directories_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1A ${pdl_dev_cat1a_dir}/include/ip)
zephyr_library_sources_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1A ${pdl_dev_cat1a_dir}/source/cy_device.c)
zephyr_include_directories(${pdl_drv_dir}/include)
zephyr_include_directories_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1B ${pdl_dev_cat1b_dir}/include)
zephyr_include_directories_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1B ${pdl_dev_cat1b_dir}/include/ip)
zephyr_library_sources_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1B ${pdl_dev_cat1b_dir}/source/cy_device.c)
zephyr_include_directories_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1C ${pdl_dev_cat1c_dir}/include)
zephyr_include_directories_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1C ${pdl_dev_cat1c_dir}/include/ip)
zephyr_library_sources_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1C ${pdl_dev_cat1c_dir}/source/cy_device.c)
zephyr_library_sources(${pdl_drv_dir}/source/TOOLCHAIN_GCC_ARM/cy_syslib_ext.S)
# Peripheral drivers
zephyr_library_sources_ifdef(CONFIG_SOC_FAMILY_PSOC6_LEGACY ${pdl_drv_dir}/source/cy_sysint.c)
if(CONFIG_SOC_FAMILY_INFINEON_CAT1C)
zephyr_library_sources(${pdl_drv_dir}/source/cy_sysint.c)
endif()
zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_I2C ${pdl_drv_dir}/source/cy_scb_i2c.c)
zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_LPTIMER ${pdl_drv_dir}/source/cy_mcwdt.c)
zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_PWM ${pdl_drv_dir}/source/cy_tcpwm_pwm.c)
@ -84,8 +90,13 @@ zephyr_library_sources(${pdl_drv_dir}/source/cy_ipc_pipe.c) @@ -84,8 +90,13 @@ zephyr_library_sources(${pdl_drv_dir}/source/cy_ipc_pipe.c)
zephyr_library_sources(${pdl_drv_dir}/source/cy_ipc_sema.c)
zephyr_library_sources(${pdl_drv_dir}/source/cy_prot.c)
zephyr_library_sources(${pdl_drv_dir}/source/cy_sysclk.c)
if(CONFIG_SOC_FAMILY_INFINEON_CAT1B)
if(CONFIG_SOC_FAMILY_INFINEON_CAT1B OR CONFIG_SOC_FAMILY_INFINEON_CAT1C)
zephyr_library_sources(${pdl_drv_dir}/source/cy_sysclk_v2.c)
zephyr_library_sources(${pdl_drv_dir}/source/cy_wdt_b.c)
endif()
if(CONFIG_SOC_FAMILY_INFINEON_CAT1B)
zephyr_library_sources(${pdl_drv_dir}/source/cy_systick_v2.c)
zephyr_library_sources(${pdl_drv_dir}/source/cy_syspm_v2.c)
zephyr_library_sources(${pdl_drv_dir}/source/cy_syspm_btss.c)
@ -93,12 +104,14 @@ if(CONFIG_SOC_FAMILY_INFINEON_CAT1B) @@ -93,12 +104,14 @@ if(CONFIG_SOC_FAMILY_INFINEON_CAT1B)
zephyr_library_sources(${pdl_drv_dir}/source/ppu_v1.c)
endif()
zephyr_library_sources(${pdl_drv_dir}/source/cy_syslib.c)
zephyr_library_sources(${pdl_drv_dir}/source/cy_syspm.c)
zephyr_library_sources(${pdl_drv_dir}/source/cy_systick.c)
zephyr_library_sources(${pdl_drv_dir}/source/cy_trigmux.c)
zephyr_library_sources(${pdl_drv_dir}/source/cy_wdt.c)
zephyr_library_sources(${pdl_drv_dir}/source/cy_tcpwm_pwm.c)
zephyr_library_sources(${pdl_drv_dir}/source/cy_syspm.c)
zephyr_library_sources_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1C ${pdl_drv_dir}/source/cy_syspm_v3.c)
# add IPC_BT driver for CYW208XX devices
zephyr_library_sources_ifdef(CONFIG_BT_CYW208XX ${pdl_drv_dir}/source/cy_ipc_bt.c)
zephyr_library_sources_ifdef(CONFIG_BT_CYW208XX ${pdl_drv_dir}/source/cy_syspm_pdcm.c)

12
modules/hal_infineon/mtb-template-cat1/CMakeLists.txt

@ -6,6 +6,7 @@ @@ -6,6 +6,7 @@
set(template_dir ${ZEPHYR_HAL_INFINEON_MODULE_DIR}/mtb-template-cat1)
set(cat1a_dir ${template_dir}/files/templates/cat1a)
set(cat1b_dir ${template_dir}/files/templates/cat1b)
set(cat1c_dir ${template_dir}/files/templates/cat1c)
if(CONFIG_SOC_FAMILY_INFINEON_CAT1A)
zephyr_include_directories(${cat1a_dir}/COMPONENT_MTB)
@ -17,10 +18,17 @@ if(CONFIG_SOC_FAMILY_INFINEON_CAT1A) @@ -17,10 +18,17 @@ if(CONFIG_SOC_FAMILY_INFINEON_CAT1A)
${cat1a_dir}/COMPONENT_MTB/COMPONENT_CM0P/system_psoc6_cm0plus.c)
endif()
# Add support cyw20829 (cat1b)
# Add support for CYW20829 (CAT1B)
if(CONFIG_SOC_FAMILY_INFINEON_CAT1B)
zephyr_include_directories(${cat1b_dir}/COMPONENT_MTB)
zephyr_include_directories(${cat1b_dir}/COMPONENT_MTB/COMPONENT_CM33/HEADER_FILES)
zephyr_library_sources(${cat1b_dir}/COMPONENT_MTB/COMPONENT_CM33/system_cyw20829.c)
endif()
# Add support for XMC7x (CAT1C)
if(CONFIG_SOC_FAMILY_INFINEON_CAT1C)
zephyr_include_directories(${cat1c_dir}/COMPONENT_MTB)
zephyr_include_directories(${cat1c_dir}/COMPONENT_MTB/HEADER_FILES)
zephyr_library_sources_ifdef(CONFIG_CPU_CORTEX_M0PLUS ${cat1c_dir}/COMPONENT_MTB/COMPONENT_CM0P/system_cm0plus.c)
zephyr_library_sources_ifdef(CONFIG_CPU_CORTEX_M7 ${cat1c_dir}/COMPONENT_MTB/COMPONENT_CM7/system_cm7.c)
endif()

5
soc/infineon/cat1c/CMakeLists.txt

@ -0,0 +1,5 @@ @@ -0,0 +1,5 @@
# Copyright (c) 2024 Cypress Semiconductor Corporation.
# SPDX-License-Identifier: Apache-2.0
add_subdirectory(common)
add_subdirectory(${SOC_SERIES})

9
soc/infineon/cat1c/Kconfig

@ -0,0 +1,9 @@ @@ -0,0 +1,9 @@
# Copyright (c) 2024 Cypress Semiconductor Corporation (an Infineon company) or
# an affiliate of Cypress Semiconductor Corporation
# SPDX-License-Identifier: Apache-2.0
if SOC_FAMILY_INFINEON_CAT1C
rsource "*/Kconfig"
endif # SOC_FAMILY_INFINEON_CAT1C

10
soc/infineon/cat1c/Kconfig.defconfig

@ -0,0 +1,10 @@ @@ -0,0 +1,10 @@
# PSOC CAT1B Configuration
# Copyright (c) 2024 Cypress Semiconductor Corporation.
# SPDX-License-Identifier: Apache-2.0
if SOC_FAMILY_INFINEON_CAT1C
rsource "*/Kconfig.defconfig"
endif # SOC_FAMILY_INFINEON_CAT1C

14
soc/infineon/cat1c/Kconfig.soc

@ -0,0 +1,14 @@ @@ -0,0 +1,14 @@
# Copyright (c) 2024 Cypress Semiconductor Corporation (an Infineon company) or
# an affiliate of Cypress Semiconductor Corporation
# SPDX-License-Identifier: Apache-2.0
# Family definitions
config SOC_FAMILY_INFINEON_CAT1
bool
config SOC_FAMILY_INFINEON_CAT1C
bool
select SOC_FAMILY_INFINEON_CAT1
# MPNs definitions
rsource "*/Kconfig.soc"

4
soc/infineon/cat1c/common/CMakeLists.txt

@ -0,0 +1,4 @@ @@ -0,0 +1,4 @@
# Copyright (c) 2024 Cypress Semiconductor Corporation.
# SPDX-License-Identifier: Apache-2.0
zephyr_include_directories(.)

129
soc/infineon/cat1c/common/pinctrl_soc.h

@ -0,0 +1,129 @@ @@ -0,0 +1,129 @@
/*
* Copyright (c) 2016-2017 Piotr Mienkowski
* Copyright (c) 2021 ATL Electronics
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*
*/
/**
* @brief Infineon CAT1 SoC specific helpers for pinctrl driver.
*/
#ifndef ZEPHYR_SOC_ARM_INFINEON_CAT1_COMMON_PINCTRL_SOC_H_
#define ZEPHYR_SOC_ARM_INFINEON_CAT1_COMMON_PINCTRL_SOC_H_
#include <stdint.h>
#include <zephyr/devicetree.h>
#ifdef __cplusplus
extern "C" {
#endif
/** @cond INTERNAL_HIDDEN */
/**
* Bit definition in PINMUX field
*/
#define SOC_PINMUX_PORT_POS (0)
#define SOC_PINMUX_PORT_MASK (0xFFul << SOC_PINMUX_PORT_POS)
#define SOC_PINMUX_PIN_POS (8)
#define SOC_PINMUX_PIN_MASK (0xFFul << SOC_PINMUX_PIN_POS)
#define SOC_PINMUX_HSIOM_FUNC_POS (16)
#define SOC_PINMUX_HSIOM_MASK (0xFFul << SOC_PINMUX_HSIOM_FUNC_POS)
#define SOC_PINMUX_SIGNAL_POS (24)
#define SOC_PINMUX_SIGNAL_MASK (0xFFul << SOC_PINMUX_SIGNAL_POS)
/*
* Pin flags/attributes
*/
#define SOC_GPIO_DEFAULT (0)
#define SOC_GPIO_FLAGS_POS (0)
#define SOC_GPIO_FLAGS_MASK (0x3F << SOC_GPIO_FLAGS_POS)
#define SOC_GPIO_PULLUP_POS (0)
#define SOC_GPIO_PULLUP (1 << SOC_GPIO_PULLUP_POS)
#define SOC_GPIO_PULLDOWN_POS (1)
#define SOC_GPIO_PULLDOWN (1 << SOC_GPIO_PULLDOWN_POS)
#define SOC_GPIO_OPENDRAIN_POS (2)
#define SOC_GPIO_OPENDRAIN (1 << SOC_GPIO_OPENDRAIN_POS)
#define SOC_GPIO_OPENSOURCE_POS (3)
#define SOC_GPIO_OPENSOURCE (1 << SOC_GPIO_OPENSOURCE_POS)
/* Push-Pull means Strong, see dts/pinctrl/pincfg-node.yaml */
#define SOC_GPIO_PUSHPULL_POS (4)
#define SOC_GPIO_PUSHPULL (1 << SOC_GPIO_PUSHPULL_POS)
/* Input-Enable means Input-Buffer, see dts/pinctrl/pincfg-node.yaml */
#define SOC_GPIO_INPUTENABLE_POS (5)
#define SOC_GPIO_INPUTENABLE (1 << SOC_GPIO_INPUTENABLE_POS)
#define SOC_GPIO_HIGHZ_POS (6)
#define SOC_GPIO_HIGHZ (1 << SOC_GPIO_HIGHZ_POS)
/** Type for CAT1 Soc pin. */
typedef struct {
/**
* Pinmux settings (port, pin and function).
* [0..7] - Port nunder
* [8..15] - Pin number
* [16..23]- HSIOM function
*/
uint32_t pinmux;
/** Pin configuration (bias, drive and slew rate). */
uint32_t pincfg;
} pinctrl_soc_pin_t;
#define CAT1_PINMUX_GET_PORT_NUM(pinmux) (((pinmux) & SOC_PINMUX_PORT_MASK) >> SOC_PINMUX_PORT_POS)
#define CAT1_PINMUX_GET_PIN_NUM(pinmux) (((pinmux) & SOC_PINMUX_PIN_MASK) >> SOC_PINMUX_PIN_POS)
#define CAT1_PINMUX_GET_HSIOM_FUNC(pinmux) \
(((pinmux) & SOC_PINMUX_HSIOM_MASK) >> SOC_PINMUX_HSIOM_FUNC_POS)
/**
* @brief Utility macro to initialize pinmux field in #pinctrl_pin_t.
* @param node_id Node identifier.
*/
#define Z_PINCTRL_CAT1_PINMUX_INIT(node_id) DT_PROP(node_id, pinmux)
/**
* @brief Utility macro to initialize pincfg field in #pinctrl_pin_t.
* @param node_id Node identifier.
*/
#define Z_PINCTRL_CAT1_PINCFG_INIT(node_id) \
((DT_PROP(node_id, bias_pull_up) << SOC_GPIO_PULLUP_POS) | \
(DT_PROP(node_id, bias_pull_down) << SOC_GPIO_PULLDOWN_POS) | \
(DT_PROP(node_id, drive_open_drain) << SOC_GPIO_OPENDRAIN_POS) | \
(DT_PROP(node_id, drive_open_source) << SOC_GPIO_OPENSOURCE_POS) | \
(DT_PROP(node_id, drive_push_pull) << SOC_GPIO_PUSHPULL_POS) | \
(DT_PROP(node_id, input_enable) << SOC_GPIO_INPUTENABLE_POS) | \
(DT_PROP(node_id, bias_high_impedance) << SOC_GPIO_HIGHZ_POS))
/**
* @brief Utility macro to initialize each pin.
*
* @param node_id Node identifier.
* @param state_prop State property name.
* @param idx State property entry index.
*/
#define Z_PINCTRL_STATE_PIN_INIT(node_id, state_prop, idx) \
{.pinmux = Z_PINCTRL_CAT1_PINMUX_INIT(DT_PROP_BY_IDX(node_id, state_prop, idx)), \
.pincfg = Z_PINCTRL_CAT1_PINCFG_INIT(DT_PROP_BY_IDX(node_id, state_prop, idx))},
/**
* @brief Utility macro to initialize state pins contained in a given property.
*
* @param node_id Node identifier.
* @param prop Property name describing state pins.
*/
#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
{DT_FOREACH_PROP_ELEM(node_id, prop, Z_PINCTRL_STATE_PIN_INIT)}
/** @endcond */
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_SOC_ARM_INFINEON_CAT1_COMMON_PINCTRL_SOC_H_ */

27
soc/infineon/cat1c/soc.yml

@ -0,0 +1,27 @@ @@ -0,0 +1,27 @@
family:
- name: cat1c
series:
- name: xmc7200
socs:
- name: xmc7200_f176k8384
- name: xmc7200d_f176k8384
- name: xmc7200_e272k8384
- name: xmc7200d_e272k8384
cpuclusters:
- name: m0p
- name: m7_0
- name: m7_1
- name: cyt4bf
socs:
- name: cyt4bf8ces
- name: cyt4bf8cee
- name: cyt4bf8cds
- name: cyt4bf8cde
- name: cyt4bfbcjs
- name: cyt4bfbcje
- name: cyt4bfbchs
- name: cyt4bfbche
- name: cyt4bfccjs
- name: cyt4bfccje
- name: cyt4bfcchs
- name: cyt4bfcche

15
soc/infineon/cat1c/xmc7200/CMakeLists.txt

@ -0,0 +1,15 @@ @@ -0,0 +1,15 @@
# Copyright (c) 2025 Cypress Semiconductor Corporation.
# SPDX-License-Identifier: Apache-2.0
zephyr_compile_definitions_ifdef(CONFIG_SOC_XMC7200D_E272K8384_M7_0 CORE_NAME_CM7_0)
zephyr_compile_definitions_ifdef(CONFIG_SOC_XMC7200D_E272K8384_M7_1 CORE_NAME_CM7_1)
zephyr_sources_ifdef(CONFIG_CPU_CORTEX_M0PLUS soc_m0p.c)
zephyr_sources_ifdef(CONFIG_CPU_CORTEX_M7 soc_m7.c)
zephyr_include_directories(.)
set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
# CAT1C family defines
zephyr_compile_definitions_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1 CY_USING_HAL)
zephyr_compile_definitions_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1C COMPONENT_CAT1C)

25
soc/infineon/cat1c/xmc7200/Kconfig

@ -0,0 +1,25 @@ @@ -0,0 +1,25 @@
# Copyright (c) 2024 Cypress Semiconductor Corporation (an Infineon company) or
# an affiliate of Cypress Semiconductor Corporation
# SPDX-License-Identifier: Apache-2.0
# Infineon CAT1C devices
# Series definitions
config SOC_SERIES_XMC7200
select ARM
select CPU_CORTEX_M_HAS_SYSTICK
select CPU_HAS_ARM_MPU
select CPU_CORTEX_M_HAS_VTOR
select CPU_HAS_ICACHE if CPU_CORTEX_M7
select CPU_HAS_DCACHE if CPU_CORTEX_M7
select CPU_HAS_FPU if CPU_CORTEX_M7
select SOC_PREP_HOOK
config SOC_XMC7200D_E272K8384_M0PLUS
select CPU_CORTEX_M0PLUS
config SOC_XMC7200D_E272K8384_M7_0
select CPU_CORTEX_M7
config SOC_XMC7200D_E272K8384_M7_1
select CPU_CORTEX_M7

20
soc/infineon/cat1c/xmc7200/Kconfig.defconfig

@ -0,0 +1,20 @@ @@ -0,0 +1,20 @@
# Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
# an affiliate of Cypress Semiconductor Corporation
# SPDX-License-Identifier: Apache-2.0
# Infineon XMC7200 based MCU default configuration
if SOC_DIE_XMC7200
config NUM_IRQS
default 16
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
config BUILD_OUTPUT_HEX
default y
# add additional die specific params
endif # SOC_DIE_XMC7200

139
soc/infineon/cat1c/xmc7200/Kconfig.soc

@ -0,0 +1,139 @@ @@ -0,0 +1,139 @@
# Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
# an affiliate of Cypress Semiconductor Corporation
# SPDX-License-Identifier: Apache-2.0
# SOC series
config SOC_SERIES_XMC7200
bool
config SOC_SERIES
default "xmc7200" if SOC_SERIES_XMC7200
# SOC die
config SOC_DIE_XMC7200
bool
select SOC_FAMILY_INFINEON_CAT1C
# SOC packages
config SOC_PACKAGE_XMC7200_176_TEQFP
bool
config SOC_PACKAGE_XMC7200_272_BGA
bool
config SOC_PACKAGE_XMC7200_320_BGA
bool
# Infineon XMC7200 series MCUs
config SOC_XMC7200_F176K8384
bool
select SOC_DIE_XMC7200
select SOC_PACKAGE_XMC7200_176_TEQFP
select SOC_SERIES_XMC7200
config SOC_XMC7200D_F176K8384
bool
select SOC_DIE_XMC7200
select SOC_PACKAGE_XMC7200_176_TEQFP
select SOC_SERIES_XMC7200
config SOC_XMC7200_E272K8384
bool
select SOC_DIE_XMC7200
select SOC_PACKAGE_XMC7200_272_BGA
select SOC_SERIES_XMC7200
config SOC_XMC7200D_E272K8384_M0PLUS
bool
select SOC_DIE_XMC7200
select SOC_PACKAGE_XMC7200_272_BGA
select SOC_SERIES_XMC7200
config SOC_XMC7200D_E272K8384_M7_0
bool
select SOC_DIE_XMC7200
select SOC_PACKAGE_XMC7200_272_BGA
select SOC_SERIES_XMC7200
config SOC_XMC7200D_E272K8384_M7_1
bool
select SOC_DIE_XMC7200
select SOC_PACKAGE_XMC7200_272_BGA
select SOC_SERIES_XMC7200
config SOC_CYT4BF8CES
bool
select SOC_DIE_XMC7200
select SOC_PACKAGE_XMC7200_176_TEQFP
config SOC_CYT4BF8CEE
bool
select SOC_DIE_XMC7200
select SOC_PACKAGE_XMC7200_176_TEQFP
config SOC_CYT4BF8CDS
bool
select SOC_DIE_XMC7200
select SOC_PACKAGE_XMC7200_176_TEQFP
config SOC_CYT4BF8CDE
bool
select SOC_DIE_XMC7200
select SOC_PACKAGE_XMC7200_176_TEQFP
config SOC_CYT4BFBCJS
bool
select SOC_DIE_XMC7200
select SOC_PACKAGE_XMC7200_272_BGA
config SOC_CYT4BFBCJE
bool
select SOC_DIE_XMC7200
select SOC_PACKAGE_XMC7200_272_BGA
config SOC_CYT4BFBCHS
bool
select SOC_DIE_XMC7200
select SOC_PACKAGE_XMC7200_272_BGA
config SOC_CYT4BFBCHE
bool
select SOC_DIE_XMC7200
select SOC_PACKAGE_XMC7200_272_BGA
config SOC_CYT4BFCCJS
bool
select SOC_DIE_XMC7200
select SOC_PACKAGE_XMC7200_320_BGA
config SOC_CYT4BFCCJE
bool
select SOC_DIE_XMC7200
select SOC_PACKAGE_XMC7200_320_BGA
config SOC_CYT4BFCCHS
bool
select SOC_DIE_XMC7200
select SOC_PACKAGE_XMC7200_320_BGA
config SOC_CYT4BFCCHE
bool
select SOC_DIE_XMC7200
select SOC_PACKAGE_XMC7200_320_BGA
config SOC
default "xmc7200_f176k8384" if SOC_XMC7200_F176K8384
default "xmc7200d_f176k8384" if SOC_XMC7200D_F176K8384
default "xmc7200_e272k8384" if SOC_XMC7200_E272K8384
default "xmc7200d_e272k8384" if SOC_XMC7200D_E272K8384_M0PLUS || SOC_XMC7200D_E272K8384_M7_0 || SOC_XMC7200D_E272K8384_M7_1
default "cyt4bf8ces" if SOC_CYT4BF8CES
default "cyt4bf8cee" if SOC_CYT4BF8CEE
default "cyt4bf8cds" if SOC_CYT4BF8CDS
default "cyt4bf8cde" if SOC_CYT4BF8CDE
default "cyt4bfbcjs" if SOC_CYT4BFBCJS
default "cyt4bfbcje" if SOC_CYT4BFBCJE
default "cyt4bfbchs" if SOC_CYT4BFBCHS
default "cyt4bfbche" if SOC_CYT4BFBCHE
default "cyt4bfccjs" if SOC_CYT4BFCCJS
default "cyt4bfccje" if SOC_CYT4BFCCJE
default "cyt4bfcchs" if SOC_CYT4BFCCHS
default "cyt4bfcche" if SOC_CYT4BFCCHE

34
soc/infineon/cat1c/xmc7200/soc.h

@ -0,0 +1,34 @@ @@ -0,0 +1,34 @@
/*
* Copyright (c) 2021 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @brief Infineon XMC7200 SOC.
*/
#ifndef _SOC__H_
#define _SOC__H_
#ifndef _ASMLANGUAGE
#include <cy_device_headers.h>
#include <cy_sysint.h>
/* Used to pull values from the device tree array */
#define SYS_INT_NUM 0
#define SYS_INT_PRI 1
#define ENABLE_SYS_INT(n, isr_handler) \
enable_sys_int(DT_INST_PROP_BY_IDX(n, system_interrupts, SYS_INT_NUM), \
DT_INST_PROP_BY_IDX(n, system_interrupts, SYS_INT_PRI), \
(void (*)(const void *))(void *)isr_handler, \
DEVICE_DT_INST_GET(n));
void enable_sys_int(uint32_t int_num, uint32_t priority, void(*isr)(const void *),
const void *arg);
#endif /* !_ASMLANGUAGE */
#endif /* _SOC__H_ */

30
soc/infineon/cat1c/xmc7200/soc_m0p.c

@ -0,0 +1,30 @@ @@ -0,0 +1,30 @@
/*
* Copyright (c) 2021 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @brief Infineon XMC7200 SOC.
*/
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/kernel.h>
#include <cy_sysint.h>
#include <cy_wdt.h>
void soc_prep_hook(void)
{
Cy_WDT_Unlock();
Cy_WDT_Disable();
SystemCoreClockUpdate();
}
void enable_sys_int(uint32_t int_num, uint32_t priority, void (*isr)(const void *), const void *arg)
{
/* Interrupts are not supported on cm0p */
k_fatal_halt(K_ERR_CPU_EXCEPTION);
}

150
soc/infineon/cat1c/xmc7200/soc_m7.c

@ -0,0 +1,150 @@ @@ -0,0 +1,150 @@
/*
* Copyright (c) 2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @brief Infineon XMC7200 SOC.
*/
#include <zephyr/cache.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/kernel.h>
#include <cy_sysclk.h>
__attribute__((section(".dtcm_bss"))) struct _isr_table_entry sys_int_table[CPUSS_SYSTEM_INT_NR];
void enable_sys_int(uint32_t int_num, uint32_t priority, void (*isr)(const void *), const void *arg)
{
/* IRQ_PRIO_LOWEST = 6 */
if (priority <= IRQ_PRIO_LOWEST) {
Cy_SysInt_SetInterruptSource(priority, int_num);
} else {
Cy_SysInt_SetInterruptSource(IRQ_PRIO_LOWEST + 1, int_num);
}
if (int_num < CPUSS_SYSTEM_INT_NR) {
sys_int_table[int_num].arg = arg;
sys_int_table[int_num].isr = isr;
} else {
k_fatal_halt(K_ERR_CPU_EXCEPTION);
}
}
__attribute__((section(".itcm"))) void sys_int_handler(uint32_t intrNum)
{
uint32_t system_int_idx;
#ifdef CORE_NAME_CM7_0
if ((_FLD2VAL(CPUSS_CM7_0_INT_STATUS_SYSTEM_INT_VALID, CPUSS_CM7_0_INT_STATUS[intrNum]))) {
system_int_idx = _FLD2VAL(CPUSS_CM7_0_INT_STATUS_SYSTEM_INT_IDX,
CPUSS_CM7_0_INT_STATUS[intrNum]);
struct _isr_table_entry *entry = &sys_int_table[system_int_idx];
(entry->isr)(entry->arg);
}
#endif
#ifdef CORE_NAME_CM7_1
if ((_FLD2VAL(CPUSS_CM7_1_INT_STATUS_SYSTEM_INT_VALID, CPUSS_CM7_1_INT_STATUS[intrNum]))) {
system_int_idx = _FLD2VAL(CPUSS_CM7_1_INT_STATUS_SYSTEM_INT_IDX,
CPUSS_CM7_1_INT_STATUS[intrNum]);
struct _isr_table_entry *entry = &sys_int_table[system_int_idx];
(entry->isr)(entry->arg);
}
#endif
NVIC_ClearPendingIRQ((IRQn_Type)intrNum);
}
void system_irq_init(void)
{
/* Set system interrupt table defaults */
for (uint32_t index = 0; index < CPUSS_SYSTEM_INT_NR; index++) {
sys_int_table[index].arg = (const void *)0x0;
sys_int_table[index].isr = z_irq_spurious;
}
/* Connect System Interrupts (IRQ0-IRQ7) to handler */
/* irq priority handler arg flags */
IRQ_CONNECT(0, 0, sys_int_handler, 0, 0);
IRQ_CONNECT(1, 1, sys_int_handler, 1, 0);
IRQ_CONNECT(2, 2, sys_int_handler, 2, 0);
IRQ_CONNECT(3, 3, sys_int_handler, 3, 0);
IRQ_CONNECT(4, 4, sys_int_handler, 4, 0);
IRQ_CONNECT(5, 5, sys_int_handler, 5, 0);
IRQ_CONNECT(6, 6, sys_int_handler, 6, 0);
/* Priority 0 is reserved for processor faults. So, the priority number here
* is incremented by 1 in the code associated with IRQ_CONNECT. Which means that
* can not select priority 7, because that gets converted to 8, and doesn't fit
* in the 3-bit priority encoding.
*
* We will use this for additional interrupts that have any priority lower than
* the lowest level.
*/
IRQ_CONNECT(7, IRQ_PRIO_LOWEST, sys_int_handler, 7, 0);
/* Enable System Interrupts (IRQ0-IRQ7) */
irq_enable(0);
irq_enable(1);
irq_enable(2);
irq_enable(3);
irq_enable(4);
irq_enable(5);
irq_enable(6);
irq_enable(7);
}
void soc_prep_hook(void)
{
/* disable global interrupt */
__disable_irq();
/* Allow write access to Vector Table Offset Register and ITCM/DTCM configuration register
* (CPUSS_CM7_X_CTL.PPB_LOCK[3] and CPUSS_CM7_X_CTL.PPB_LOCK[1:0])
*/
#ifdef CORE_NAME_CM7_1
CPUSS->CM7_1_CTL &= ~(0xB);
#elif CORE_NAME_CM7_0
CPUSS->CM7_0_CTL &= ~(0xB);
#else
#error "Not valid"
#endif
__DSB();
__ISB();
/* Enable ITCM and DTCM */
SCB->ITCMCR = SCB->ITCMCR | 0x7; /* Set ITCMCR.EN, .RMW and .RETEN fields */
SCB->DTCMCR = SCB->DTCMCR | 0x7; /* Set DTCMCR.EN, .RMW and .RETEN fields */
#ifdef CORE_NAME_CM7_0
CPUSS_CM7_0_CTL |= (0x1 << CPUSS_CM7_0_CTL_INIT_TCM_EN_Pos);
CPUSS_CM7_0_CTL |= (0x2 << CPUSS_CM7_0_CTL_INIT_TCM_EN_Pos);
CPUSS_CM7_0_CTL |= (0x1 << CPUSS_CM7_0_CTL_INIT_RMW_EN_Pos);
CPUSS_CM7_0_CTL |= (0x2 << CPUSS_CM7_0_CTL_INIT_RMW_EN_Pos);
#elif CORE_NAME_CM7_1
CPUSS_CM7_1_CTL |= (0x1 << CPUSS_CM7_1_CTL_INIT_TCM_EN_Pos);
CPUSS_CM7_1_CTL |= (0x2 << CPUSS_CM7_1_CTL_INIT_TCM_EN_Pos);
CPUSS_CM7_1_CTL |= (0x1 << CPUSS_CM7_1_CTL_INIT_RMW_EN_Pos);
CPUSS_CM7_1_CTL |= (0x2 << CPUSS_CM7_1_CTL_INIT_RMW_EN_Pos);
#else
#error "Not valid"
#endif
/* ITCMCR EN/RMW/RETEN enabled to access ITCM */
__UNALIGNED_UINT32_WRITE(((void const *)0xE000EF90), 0x2F);
/* DTCMCR EN/RMW/RETEN enabled to access DTCM */
__UNALIGNED_UINT32_WRITE(((void const *)0xE000EF94), 0x2F);
__DSB();
__ISB();
}
void soc_early_init_hook(void)
{
sys_cache_instr_enable();
sys_cache_data_enable();
system_irq_init();
}

3
tests/arch/arm/arm_irq_advanced_features/testcase.yaml

@ -7,5 +7,8 @@ common: @@ -7,5 +7,8 @@ common:
tests:
arch.arm.irq_advanced_features:
filter: not CONFIG_TRUSTED_EXECUTION_NONSECURE
platform_exclude:
- kit_xmc72_evk/xmc7200d_e272k8384/m7_0
- kit_xmc72_evk/xmc7200d_e272k8384/m7_1
arch.arm.irq_advanced_features.secure_fw:
filter: CONFIG_TRUSTED_EXECUTION_SECURE

3
tests/arch/arm/arm_irq_zero_latency_levels/testcase.yaml

@ -10,6 +10,9 @@ tests: @@ -10,6 +10,9 @@ tests:
filter: not CONFIG_TRUSTED_EXECUTION_NONSECURE
integration_platforms:
- mps2/an521/cpu1
platform_exclude:
- kit_xmc72_evk/xmc7200d_e272k8384/m7_0
- kit_xmc72_evk/xmc7200d_e272k8384/m7_1
arch.arm.irq_zero_latency_levels.secure_fw:
filter: CONFIG_TRUSTED_EXECUTION_SECURE
integration_platforms:

2
west.yml

@ -185,7 +185,7 @@ manifest: @@ -185,7 +185,7 @@ manifest:
groups:
- hal
- name: hal_infineon
revision: e0a50ce02c7cee59b7ce6fe8a3e0e6625f0891a9
revision: 0fe4f3aee9c8f7002996a94d91299b2c28d6a8fa
path: modules/hal/infineon
groups:
- hal

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