diff --git a/soc/ite/ec/common/soc_espi.h b/soc/ite/ec/common/soc_espi.h
index 0b88f9473ac..5f7c4197c25 100644
--- a/soc/ite/ec/common/soc_espi.h
+++ b/soc/ite/ec/common/soc_espi.h
@@ -14,7 +14,10 @@
 extern "C" {
 #endif
 
-#define ESPI_IT8XXX2_SOC_DEV DEVICE_DT_GET(DT_NODELABEL(espi0))
+#define ESPI_IT8XXX2_SOC_DEV         DEVICE_DT_GET(DT_NODELABEL(espi0))
+#define ESPI_ITE_SOC_DEV             ESPI_IT8XXX2_SOC_DEV
+#define espi_ite_ec_enable_pad_ctrl  espi_it8xxx2_enable_pad_ctrl
+#define espi_ite_ec_enable_trans_irq espi_it8xxx2_enable_trans_irq
 
 /**
  * @brief eSPI input pad gating
@@ -22,7 +25,7 @@ extern "C" {
  * @param dev pointer to eSPI device
  * @param enable/disable eSPI pad
  */
-void espi_it8xxx2_enable_pad_ctrl(const struct device *dev, bool enable);
+void espi_ite_ec_enable_pad_ctrl(const struct device *dev, bool enable);
 
 /**
  * @brief eSPI transaction interrupt control
@@ -30,7 +33,7 @@ void espi_it8xxx2_enable_pad_ctrl(const struct device *dev, bool enable);
  * @param dev pointer to eSPI device
  * @param enable/disable eSPI transaction interrupt
  */
-void espi_it8xxx2_enable_trans_irq(const struct device *dev, bool enable);
+void espi_ite_ec_enable_trans_irq(const struct device *dev, bool enable);
 
 #ifdef __cplusplus
 }
diff --git a/soc/ite/ec/it8xxx2/soc.c b/soc/ite/ec/it8xxx2/soc.c
index e8a9b7fb3d7..8a97549c570 100644
--- a/soc/ite/ec/it8xxx2/soc.c
+++ b/soc/ite/ec/it8xxx2/soc.c
@@ -220,13 +220,13 @@ static void chip_configure_pll(const struct pll_config_t *pll)
 		 * We have to disable eSPI pad before changing
 		 * PLL sequence or sequence will fail if CS# pin is low.
 		 */
-		espi_it8xxx2_enable_pad_ctrl(ESPI_IT8XXX2_SOC_DEV, false);
+		espi_ite_ec_enable_pad_ctrl(ESPI_ITE_SOC_DEV, false);
 #endif
 		/* Run change PLL sequence */
 		chip_run_pll_sequence(pll);
 #ifdef CONFIG_ESPI
 		/* Enable eSPI pad after changing PLL sequence */
-		espi_it8xxx2_enable_pad_ctrl(ESPI_IT8XXX2_SOC_DEV, true);
+		espi_ite_ec_enable_pad_ctrl(ESPI_ITE_SOC_DEV, true);
 #endif
 	}
 }
@@ -307,7 +307,7 @@ void riscv_idle(enum chip_pll_mode mode, unsigned int key)
 	 * interrupt to restore clocks. With this interrupt, EC will not defer
 	 * eSPI bus while transaction is accepted.
 	 */
-	espi_it8xxx2_enable_trans_irq(ESPI_IT8XXX2_SOC_DEV, true);
+	espi_ite_ec_enable_trans_irq(ESPI_ITE_SOC_DEV, true);
 #endif
 	/* Chip doze after wfi instruction */
 	chip_pll_ctrl(mode);
@@ -335,7 +335,7 @@ void riscv_idle(enum chip_pll_mode mode, unsigned int key)
 
 #ifdef CONFIG_ESPI
 	/* CPU has been woken up, the interrupt is no longer needed */
-	espi_it8xxx2_enable_trans_irq(ESPI_IT8XXX2_SOC_DEV, false);
+	espi_ite_ec_enable_trans_irq(ESPI_ITE_SOC_DEV, false);
 #endif
 	/*
 	 * Enable M-mode external interrupt