From a8647d3af9db199ef1f586f57a8553f17fa36e8b Mon Sep 17 00:00:00 2001 From: Emilio Benavente Date: Mon, 9 Dec 2024 13:07:42 -0600 Subject: [PATCH] soc: nxp: mcx: Updating Clock Code Updating clock code to mcxw71. Adding some missing clock setups. Signed-off-by: Emilio Benavente --- soc/nxp/mcx/mcxw/soc.c | 22 ++++++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/soc/nxp/mcx/mcxw/soc.c b/soc/nxp/mcx/mcxw/soc.c index 34f678199a1..f020a0f1352 100644 --- a/soc/nxp/mcx/mcxw/soc.c +++ b/soc/nxp/mcx/mcxw/soc.c @@ -1,5 +1,5 @@ /* - * Copyright 2023 NXP + * Copyright 2023-2024 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -40,8 +40,12 @@ static ALWAYS_INLINE void clock_init(void) CCM32K_Set32kOscConfig(CCM32K, kCCM32K_Enable32kHzCrystalOsc, &ccm32k_osc_config); /* Disable ROSC Monitor, because switching the source would generate an expected error */ CLOCK_SetRoscMonitorMode(kSCG_RoscMonitorDisable); + /* Select the Real Time Clock (RTC) source as OSC32K */ + while ((CCM32K_GetStatusFlag(CCM32K) & CCM32K_STATUS_OSC32K_RDY_MASK) == 0UL) { + } CCM32K_SelectClockSource(CCM32K, kCCM32K_ClockSourceSelectOsc32k); + /* Wait for RTC Oscillator to be Valid */ while (!CLOCK_IsRoscValid()) ; @@ -50,6 +54,8 @@ static ALWAYS_INLINE void clock_init(void) /* Disable the FRO32K to save power */ CCM32K_Enable32kFro(CCM32K, false); + CLOCK_SetXtal32Freq(32768U); + /* Configuration to set FIRC to maximum frequency */ scg_firc_config_t scg_firc_config = { .enableMode = kSCG_FircEnable, /* Fast IRC is enabled */ @@ -90,7 +96,7 @@ static ALWAYS_INLINE void clock_init(void) /* OSC-RF / System Oscillator Configuration */ scg_sosc_config_t sosc_config = { - .freq = 32000U, + .freq = 32000000U, .monitorMode = kSCG_SysOscMonitorDisable, .enableMode = kSCG_SoscEnable, }; @@ -125,11 +131,19 @@ static ALWAYS_INLINE void clock_init(void) CLOCK_SetIpSrcDiv(kCLOCK_Lpadc0, kSCG_SysClkDivBy10); /* Ungate clocks if the peripheral is enabled in devicetree */ - if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(lpuart0), nxp_lpc_lpuart, okay)) { + if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(gpioa), nxp_kinetis_gpio, okay)) { + CLOCK_EnableClock(kCLOCK_PortA); + } + + if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(gpioc), nxp_kinetis_gpio, okay)) { + CLOCK_EnableClock(kCLOCK_PortC); + } + + if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(lpuart0), nxp_kinetis_lpuart, okay)) { CLOCK_EnableClock(kCLOCK_Lpuart0); } - if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(lpuart1), nxp_lpc_lpuart, okay)) { + if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(lpuart1), nxp_kinetis_lpuart, okay)) { CLOCK_EnableClock(kCLOCK_Lpuart1); }