From a7f9ebe9d50ce6f2fc2b7de19ee5fe6c8c7b85fe Mon Sep 17 00:00:00 2001
From: Huaqi Fang <578567190@qq.com>
Date: Mon, 7 Apr 2025 16:04:13 +0800
Subject: [PATCH] driver: interrupt_controller: intc_clic: support 32 and 64
 bit riscv cpu

This patch is used to provide clic(eclic) in 64 bit riscv cpu support,
since in 64 bit riscv cpu, the clic irq table entry is also 64 bit,
so we need to use ld/sd to do irq entry load and store

Signed-off-by: Huaqi Fang <578567190@qq.com>
---
 drivers/interrupt_controller/intc_clic.S | 31 +++++++++++++++++++++---
 1 file changed, 27 insertions(+), 4 deletions(-)

diff --git a/drivers/interrupt_controller/intc_clic.S b/drivers/interrupt_controller/intc_clic.S
index 720b829e214..3a03b8d417c 100644
--- a/drivers/interrupt_controller/intc_clic.S
+++ b/drivers/interrupt_controller/intc_clic.S
@@ -11,6 +11,29 @@
 #include <zephyr/arch/cpu.h>
 #include "intc_clic.h"
 
+#ifdef CONFIG_64BIT
+	/* register-wide load/store based on ld/sd (XLEN = 64) */
+
+	.macro lr, rd, mem
+	ld \rd, \mem
+	.endm
+
+	.macro sr, rs, mem
+	sd \rs, \mem
+	.endm
+
+#else
+	/* register-wide load/store based on lw/sw (XLEN = 32) */
+
+	.macro lr, rd, mem
+	lw \rd, \mem
+	.endm
+
+	.macro sr, rs, mem
+	sw \rs, \mem
+	.endm
+
+#endif
 
 GTEXT(__soc_handle_irq)
 /*
@@ -36,7 +59,7 @@ GTEXT(sys_trace_isr_exit)
  */
 SECTION_FUNC(exception.other, __soc_handle_all_irqs)
 	addi sp, sp, -16
-	sw ra, 0(sp)
+	sr ra, 0(sp)
 
 	/* Read and clear mnxti to get highest current interrupt and enable interrupts. Will return
 	 * original interrupt if no others appear. */
@@ -58,10 +81,10 @@ irq_loop:
 	add t0, t0, a0
 
 	/* Load argument in a0 register */
-	lw a0, 0(t0)
+	lr a0, 0(t0)
 
 	/* Load ISR function address in register t1 */
-	lw t1, RV_REGSIZE(t0)
+	lr t1, RV_REGSIZE(t0)
 
 	/* Call ISR function */
 	jalr ra, t1, 0
@@ -75,6 +98,6 @@ irq_loop:
 	bnez a0, irq_loop
 
 irq_done:
-	lw ra, 0(sp)
+	lr ra, 0(sp)
 	addi sp, sp, 16
 	ret