diff --git a/soc/nxp/common/Kconfig.xspi_xip b/soc/nxp/common/Kconfig.xspi_xip new file mode 100644 index 00000000000..d087e8b2d2e --- /dev/null +++ b/soc/nxp/common/Kconfig.xspi_xip @@ -0,0 +1,42 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +DT_CHOSEN_Z_FLASH := zephyr,flash +DT_COMPAT_XSPI := nxp,xspi + +DT_CHOSEN_FLASH_NODE := $(dt_chosen_path,$(DT_CHOSEN_Z_FLASH)) +DT_CHOSEN_FLASH_PARENT := $(dt_node_parent,$(DT_CHOSEN_FLASH_NODE)) + +DT_FLASH_PARENT_IS_XSPI := $(dt_node_has_compat,$(DT_CHOSEN_FLASH_PARENT),$(DT_COMPAT_XSPI)) +DT_FLASH_HAS_SIZE_PROP := $(dt_node_has_prop,$(DT_CHOSEN_FLASH_NODE),size) + +config FLASH_BASE_ADDRESS + default $(dt_node_reg_addr_hex,$(DT_CHOSEN_FLASH_PARENT),1) \ + if $(DT_FLASH_PARENT_IS_XSPI) + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) + +config FLASH_SIZE + default $(dt_node_int_prop_int,$(DT_CHOSEN_FLASH_NODE),size,Kb) + +config FLASH_MCUX_XSPI_XIP + bool + default $(DT_FLASH_PARENT_IS_XSPI) + select XIP + help + Allows the soc to safely initialize the clocks for the + XSpi when planning to execute code in XSpi Memory. + +if FLASH_MCUX_XSPI_XIP + +config CODE_DATA_RELOCATION_SRAM + default y + +config FLASH_MCUX_XSPI_XIP_MEM + string + prompt "Xspi drivers memory location" + default "RAM" + help + Select the location to run the XSPI drivers when using + the flash API. + +endif diff --git a/soc/nxp/imxrt/CMakeLists.txt b/soc/nxp/imxrt/CMakeLists.txt index 5984d081ba9..814da8d7fa2 100644 --- a/soc/nxp/imxrt/CMakeLists.txt +++ b/soc/nxp/imxrt/CMakeLists.txt @@ -69,7 +69,7 @@ if(CONFIG_SOC_SERIES_IMXRT118X) zephyr_compile_definitions(XIP_EXTERNAL_FLASH) endif() -if(CONFIG_SOC_SERIES_IMXRT6XX OR CONFIG_SOC_SERIES_IMXRT5XX) +if(CONFIG_SOC_SERIES_IMXRT6XX OR CONFIG_SOC_SERIES_IMXRT5XX OR CONFIG_SOC_SERIES_IMXRT7XX) zephyr_linker_sources_ifdef(CONFIG_USB_DEVICE_DRIVER SECTIONS usb.ld) zephyr_linker_sources_ifdef(CONFIG_UDC_DRIVER SECTIONS usb.ld) endif() diff --git a/soc/nxp/imxrt/Kconfig b/soc/nxp/imxrt/Kconfig index 0b8c8f0ab87..648b30d750d 100644 --- a/soc/nxp/imxrt/Kconfig +++ b/soc/nxp/imxrt/Kconfig @@ -10,7 +10,13 @@ if SOC_FAMILY_NXP_IMXRT # can override the defaults given here rsource "*/Kconfig" +if DT_HAS_NXP_IMX_FLEXSPI_ENABLED rsource "../common/Kconfig.flexspi_xip" +endif + +if DT_HAS_NXP_XSPI_ENABLED +rsource "../common/Kconfig.xspi_xip" +endif # Note- When SECOND_CORE_MCUX is set, the dependencies for this Kconfig # should be set elsewhere, since the determination of which SOC core @@ -29,8 +35,13 @@ rsource "../common/Kconfig.rom_loader" choice BOOT_DEVICE prompt "Boot device" + default BOOT_XSPI_NOR if DT_HAS_NXP_XSPI_ENABLED default BOOT_FLEXSPI_NOR +config BOOT_XSPI_NOR + bool "XPI serial NOR" + depends on DT_HAS_NXP_XSPI_ENABLED + config BOOT_FLEXSPI_NOR bool "FlexSPI serial NOR" depends on HAS_MCUX_FLEXSPI @@ -49,6 +60,8 @@ config BOOT_SEMC_NAND endchoice # BOOT_DEVICE +if BOOT_FLEXSPI_NOR + config FLEXSPI_CONFIG_BLOCK_OFFSET hex "FlexSPI config block offset" default 0x0 if BOOT_FLEXSPI_NOR @@ -59,6 +72,21 @@ config FLEXSPI_CONFIG_BLOCK_OFFSET sequence (optional), etc. The boot ROM expects FlexSPI configuration parameter to be presented in serial nor flash. +endif # BOOT_FLEXSPI_NOR + +if BOOT_XSPI_NOR + +config XSPI_CONFIG_BLOCK_OFFSET + hex "XSPI config block offset" + default 0x0 + help + XSPI configuration block consists of parameters regarding specific + flash devices including read command sequence, quad mode enablement + sequence (optional), etc. The boot ROM expects XSPI configuration + parameter to be presented in serial nor flash. + +endif # BOOT_XSPI_NOR + config IMAGE_VECTOR_TABLE_OFFSET hex "Image vector table offset" default 0x1000 if BOOT_FLEXSPI_NOR || BOOT_SEMC_NOR diff --git a/soc/nxp/imxrt/boot_header.ld b/soc/nxp/imxrt/boot_header.ld index 618c760f017..b61487c4819 100644 --- a/soc/nxp/imxrt/boot_header.ld +++ b/soc/nxp/imxrt/boot_header.ld @@ -9,11 +9,15 @@ __VECTOR_TABLE = CONFIG_ROM_START_OFFSET; __Vectors = __VECTOR_TABLE; #endif +#if defined(CONFIG_BOOT_XSPI_NOR) +. = CONFIG_XSPI_CONFIG_BLOCK_OFFSET; +#else . = CONFIG_FLEXSPI_CONFIG_BLOCK_OFFSET; +#endif #if defined(CONFIG_SOC_SERIES_IMXRT11XX) || defined(CONFIG_SOC_SERIES_IMXRT10XX) || defined(CONFIG_SOC_SERIES_IMXRT118X) KEEP(*(.boot_hdr.conf)) #endif -#if defined(CONFIG_SOC_SERIES_IMXRT6XX) || defined(CONFIG_SOC_SERIES_IMXRT5XX) +#if defined(CONFIG_SOC_SERIES_IMXRT6XX) || defined(CONFIG_SOC_SERIES_IMXRT5XX) || defined(CONFIG_SOC_SERIES_IMXRT7XX) KEEP(*(.flash_conf)) #endif #if defined(CONFIG_SOC_SERIES_IMXRT118X) diff --git a/soc/nxp/imxrt/imxrt7xx/CMakeLists.txt b/soc/nxp/imxrt/imxrt7xx/CMakeLists.txt new file mode 100644 index 00000000000..dc36672a9ba --- /dev/null +++ b/soc/nxp/imxrt/imxrt7xx/CMakeLists.txt @@ -0,0 +1,9 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +if(CONFIG_SOC_MIMXRT798S_CM33_CPU0 OR CONFIG_SOC_MIMXRT798S_CM33_CPU1) + add_subdirectory(cm33) +endif() diff --git a/soc/nxp/imxrt/imxrt7xx/Kconfig b/soc/nxp/imxrt/imxrt7xx/Kconfig new file mode 100644 index 00000000000..5333f074118 --- /dev/null +++ b/soc/nxp/imxrt/imxrt7xx/Kconfig @@ -0,0 +1,58 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_MIMXRT798S_CM33_CPU0 + select CPU_CORTEX_M33 + select CLOCK_CONTROL + select CPU_CORTEX_M_HAS_DWT + select ARM + select CPU_HAS_ARM_SAU + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select ARMV8_M_DSP + select ARM_TRUSTZONE_M + select CPU_CORTEX_M_HAS_SYSTICK + select HAS_MCUX + select HAS_MCUX_SYSCON + select HAS_MCUX_CACHE + select SOC_RESET_HOOK + +config SOC_MIMXRT798S_CM33_CPU1 + select CPU_CORTEX_M33 + select CLOCK_CONTROL + select CPU_CORTEX_M_HAS_DWT + select ARM + select CPU_HAS_ARM_SAU + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select ARMV8_M_DSP + select ARM_TRUSTZONE_M + select CPU_CORTEX_M_HAS_SYSTICK + select HAS_MCUX + select HAS_MCUX_SYSCON + +if SOC_SERIES_IMXRT7XX + +if NXP_IMXRT_BOOT_HEADER + +config IMAGE_VECTOR_TABLE_OFFSET + default 0x4000 + +endif # NXP_IMXRT_BOOT_HEADER + +config GLIKEY_MCUX_GLIKEY + default y + bool "Use glikey MCUX Driver" + +config IMXRT7XX_CODE_CACHE + bool "Code cache" + default y if HAS_MCUX_CACHE + help + Enable code cache for XSPI region at boot. If this Kconfig is + cleared, the CACHE64 controller will be disabled during SOC init + +config MCUX_CORE_SUFFIX + default "_cm33_core0" if SOC_MIMXRT798S_CM33_CPU0 + default "_cm33_core1" if SOC_MIMXRT798S_CM33_CPU1 + +endif # SOC_SERIES_IMXRT7XX diff --git a/soc/nxp/imxrt/imxrt7xx/Kconfig.defconfig b/soc/nxp/imxrt/imxrt7xx/Kconfig.defconfig new file mode 100644 index 00000000000..5d5466b182c --- /dev/null +++ b/soc/nxp/imxrt/imxrt7xx/Kconfig.defconfig @@ -0,0 +1,29 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_MIMXRT798S_CM33_CPU0 + +config ROM_START_OFFSET + default 0x4000 if NXP_IMXRT_BOOT_HEADER + +config NUM_IRQS + default 158 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 237500000 if CORTEX_M_SYSTICK + +endif # SOC_MIMXRT798S_CM33_CPU0 + +if SOC_MIMXRT798S_CM33_CPU1 + +config NUM_IRQS + default 93 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 100000000 if CORTEX_M_SYSTICK + +endif # SOC_MIMXRT798S_CM33_CPU1 + +config MFD + default y + depends on DT_HAS_NXP_LP_FLEXCOMM_ENABLED diff --git a/soc/nxp/imxrt/imxrt7xx/Kconfig.soc b/soc/nxp/imxrt/imxrt7xx/Kconfig.soc new file mode 100644 index 00000000000..5e321bdc9bb --- /dev/null +++ b/soc/nxp/imxrt/imxrt7xx/Kconfig.soc @@ -0,0 +1,50 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_IMXRT7XX + bool + select SOC_FAMILY_NXP_IMXRT + +config SOC_MIMXRT798S + bool + select SOC_SERIES_IMXRT7XX + +config SOC_MIMXRT798S_CM33_CPU0 + bool + select SOC_MIMXRT798S + +config SOC_MIMXRT798S_CM33_CPU1 + bool + select SOC_MIMXRT798S + +config SOC_SERIES + default "imxrt7xx" if SOC_SERIES_IMXRT7XX + +config SOC + default "mimxrt798s" if SOC_MIMXRT798S + +config SOC_PART_NUMBER_MIMXRT798SGAWAR + bool + +config SOC_PART_NUMBER_MIMXRT798SGFOA + bool + +config SOC_PART_NUMBER_MIMXRT758SGAWAR + bool + +config SOC_PART_NUMBER_MIMXRT758SGFOA + bool + +config SOC_PART_NUMBER_MIMXRT735SGAWAR + bool + +config SOC_PART_NUMBER_MIMXRT735SGFOA + bool + +config SOC_PART_NUMBER + default "MIMXRT798SGFOA" if SOC_PART_NUMBER_MIMXRT798SGFOA + default "MIMXRT798SGAWAR" if SOC_PART_NUMBER_MIMXRT798SGAWAR + default "MIMXRT758SGFOA" if SOC_PART_NUMBER_MIMXRT758SGFOA + default "MIMXRT758SGAWAR" if SOC_PART_NUMBER_MIMXRT758SGAWAR + default "MIMXRT735SGFOA" if SOC_PART_NUMBER_MIMXRT735SGFOA + default "MIMXRT735SGAWAR" if SOC_PART_NUMBER_MIMXRT735SGAWAR diff --git a/soc/nxp/imxrt/imxrt7xx/cm33/CMakeLists.txt b/soc/nxp/imxrt/imxrt7xx/cm33/CMakeLists.txt new file mode 100644 index 00000000000..cd9319bffaa --- /dev/null +++ b/soc/nxp/imxrt/imxrt7xx/cm33/CMakeLists.txt @@ -0,0 +1,25 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_compile_definitions_ifdef(CONFIG_NXP_LP_FLEXCOMM LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER=1) + +zephyr_compile_definitions(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) + +zephyr_include_directories(.) + +zephyr_sources(soc.c) + +if(CONFIG_FLASH_MCUX_XSPI_XIP) + zephyr_sources(flash_clock_setup.c) + zephyr_code_relocate(FILES flash_clock_setup.c LOCATION ${CONFIG_FLASH_MCUX_XSPI_XIP_MEM}_TEXT) +endif() + +zephyr_library_include_directories( + ${ZEPHYR_BASE}/kernel/include + ${ZEPHYR_BASE}/arch/${ARCH}/include + ) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/nxp/imxrt/imxrt7xx/cm33/flash_clock_setup.c b/soc/nxp/imxrt/imxrt7xx/cm33/flash_clock_setup.c new file mode 100644 index 00000000000..9994fc3885f --- /dev/null +++ b/soc/nxp/imxrt/imxrt7xx/cm33/flash_clock_setup.c @@ -0,0 +1,168 @@ +/* + * Copyright 2024 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#ifdef CONFIG_HAS_MCUX_CACHE +#include +#endif + +static void enable_xspi_cache(CACHE64_CTRL_Type *cache) +{ + /* First, invalidate the entire cache. */ + cache->CCR |= CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK | + CACHE64_CTRL_CCR_GO_MASK; + while ((cache->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0x00U) { + } + /* As a precaution clear the bits to avoid inadvertently re-running this command. */ + cache->CCR &= ~(CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK); + /* Now enable the cache. */ + cache->CCR |= CACHE64_CTRL_CCR_ENCACHE_MASK; +} + +static void disable_xspi_cache(CACHE64_CTRL_Type *cache) +{ + cache->CCR |= CACHE64_CTRL_CCR_PUSHW0_MASK | CACHE64_CTRL_CCR_PUSHW1_MASK | + CACHE64_CTRL_CCR_GO_MASK; /* First, clean XSPI cache. */ + while ((cache->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0x00U) { + } + /* As a precaution clear the bits to avoid inadvertently re-running this command. */ + cache->CCR &= ~(CACHE64_CTRL_CCR_PUSHW0_MASK | CACHE64_CTRL_CCR_PUSHW1_MASK); + + /* Now disable XSPI cache. */ + cache->CCR &= ~CACHE64_CTRL_CCR_ENCACHE_MASK; +} + +static void flash_deinit(XSPI_Type *base, CACHE64_CTRL_Type *cache) +{ + if (base == XSPI0) { + /* Enable clock again. */ + CLKCTL0->PSCCTL1_SET = CLKCTL0_PSCCTL1_CLR_XSPI0_MASK; + } else if (base == XSPI1) { + /* Enable clock again. */ + CLKCTL0->PSCCTL1_SET = CLKCTL0_PSCCTL1_CLR_XSPI1_MASK; + } + + base->MCR &= ~XSPI_MCR_MDIS_MASK; + if ((cache->CCR & CACHE64_CTRL_CCR_ENCACHE_MASK) != 0x00U) { + disable_xspi_cache(cache); + } + /* Wait until XSPI is not busy */ + while ((base->SR & XSPI_SR_BUSY_MASK) != 0U) { + } + /* Disable module. */ + base->MCR |= XSPI_MCR_MDIS_MASK; +} + +static void flash_init(XSPI_Type *base, CACHE64_CTRL_Type *cache) +{ + /* Enable XSPI module */ + base->MCR |= XSPI_MCR_MDIS_MASK; + + base->MCR |= XSPI_MCR_SWRSTSD_MASK | XSPI_MCR_SWRSTHD_MASK; + for (uint32_t i = 0; i < 6; i++) { + __NOP(); + } + base->MCR &= ~(XSPI_MCR_SWRSTSD_MASK | XSPI_MCR_SWRSTHD_MASK); + base->MCR |= XSPI_MCR_IPS_TG_RST_MASK | XSPI_MCR_MDIS_MASK; + base->MCR &= ~XSPI_MCR_ISD3FA_MASK; + base->MCR &= ~XSPI_MCR_MDIS_MASK; + base->MCR |= XSPI_MCR_MDIS_MASK; + base->MCR |= XSPI_MCR_ISD3FA_MASK; + base->MCR &= ~XSPI_MCR_MDIS_MASK; + + base->MCR |= XSPI_MCR_MDIS_MASK; + base->SMPR = (((base->SMPR) & (~XSPI_SMPR_DLLFSMPFA_MASK)) | + XSPI_SMPR_DLLFSMPFA(FSL_FEATURE_XSPI_DLL_REF_VALUE_DDR_DELAY_TAP_NUM)); + base->MCR &= ~XSPI_MCR_MDIS_MASK; + + base->DLLCR[0] &= + ~(XSPI_DLLCR_SLV_DLL_BYPASS_MASK | XSPI_DLLCR_DLL_CDL8_MASK | + XSPI_DLLCR_SLV_DLY_OFFSET_MASK | XSPI_DLLCR_SLV_FINE_OFFSET_MASK | + XSPI_DLLCR_DLLRES_MASK | XSPI_DLLCR_DLL_REFCNTR_MASK | XSPI_DLLCR_FREQEN_MASK); + base->DLLCR[0] &= + ~(XSPI_DLLCR_SLV_EN_MASK | XSPI_DLLCR_SLAVE_AUTO_UPDT_MASK | XSPI_DLLCR_DLLEN_MASK); + /* Enable subordinate as auto update mode. */ + base->DLLCR[0] |= XSPI_DLLCR_SLV_EN_MASK | XSPI_DLLCR_SLAVE_AUTO_UPDT_MASK; + /* program DLL to desired delay. */ + base->DLLCR[0] |= + XSPI_DLLCR_DLLRES(FSL_FEATURE_XSPI_DLL_REF_VALUE_AUTOUPDATE_X16_DISABLE_RES) | + XSPI_DLLCR_DLL_REFCNTR( + FSL_FEATURE_XSPI_DLL_REF_VALUE_AUTOUPDATE_X16_DISABLED_REF_COUNTER) | + XSPI_DLLCR_SLV_FINE_OFFSET(0) | XSPI_DLLCR_SLV_DLY_OFFSET(0) | + XSPI_DLLCR_FREQEN(1U); + /* Load above settings into delay chain. */ + base->DLLCR[0] |= XSPI_DLLCR_SLV_UPD_MASK; + base->DLLCR[0] |= XSPI_DLLCR_DLLEN_MASK; + base->DLLCR[0] &= ~XSPI_DLLCR_SLV_UPD_MASK; + + while ((base->DLLSR & XSPI_DLLSR_SLVA_LOCK_MASK) == 0UL) { + } + + if ((cache->CCR & CACHE64_CTRL_CCR_ENCACHE_MASK) == 0x00U) { + enable_xspi_cache(cache); + /* flush pipeline */ + __DSB(); + __ISB(); + } +} + +/* xspi_setup_clock run in RAM when XIP. */ +void xspi_setup_clock(XSPI_Type *base, uint32_t src, uint32_t divider) +{ + if (base == XSPI0) { + if ((CLKCTL0->XSPI0FCLKSEL != CLKCTL0_XSPI0FCLKSEL_SEL(src)) || + ((CLKCTL0->XSPI0FCLKDIV & CLKCTL0_XSPI0FCLKDIV_DIV_MASK) != (divider - 1))) { + /* Always deinit XSPI and init XSPI for the flash to make + * sure the flash works correctly after the XSPI root clock + * changed as the default XSPI configuration may does not + * work for the new root clock frequency. + */ + flash_deinit(base, CACHE64_CTRL0); + + /* Disable clock before changing clock source */ + CLKCTL0->PSCCTL1_CLR = CLKCTL0_PSCCTL1_CLR_XSPI0_MASK; + /* Update XSPI clock. */ + CLKCTL0->XSPI0FCLKSEL = + CLKCTL0_XSPI0FCLKSEL_SEL(src) | CLKCTL0_XSPI0FCLKSEL_SEL_EN_MASK; + CLKCTL0->XSPI0FCLKDIV = CLKCTL0_XSPI0FCLKDIV_DIV(divider - 1); + while ((CLKCTL0->XSPI0FCLKDIV) & CLKCTL0_XSPI0FCLKDIV_REQFLAG_MASK) { + } + /* Enable XSPI clock again */ + CLKCTL0->PSCCTL1_SET = CLKCTL0_PSCCTL1_SET_XSPI0_MASK; + + flash_init(base, CACHE64_CTRL0); + } + } else if (base == XSPI1) { + if ((CLKCTL0->XSPI1FCLKSEL != CLKCTL0_XSPI1FCLKSEL_SEL(src)) || + ((CLKCTL0->XSPI1FCLKDIV & CLKCTL0_XSPI1FCLKDIV_DIV_MASK) != (divider - 1))) { + /* Always deinit XSPI and init XSPI for the flash to make sure the flash + * works correctly after the XSPI root clock changed as the default XSPI + * configuration may does not work for the new root clock frequency. + */ + flash_deinit(base, CACHE64_CTRL1); + + /* Disable clock before changing clock source */ + CLKCTL0->PSCCTL1_CLR = CLKCTL0_PSCCTL1_CLR_XSPI1_MASK; + /* Update XSPI clock. */ + CLKCTL0->XSPI1FCLKSEL = + CLKCTL0_XSPI1FCLKSEL_SEL(src) | CLKCTL0_XSPI1FCLKSEL_SEL_EN_MASK; + CLKCTL0->XSPI1FCLKDIV = CLKCTL0_XSPI1FCLKDIV_DIV(divider - 1); + while ((CLKCTL0->XSPI1FCLKDIV) & CLKCTL0_XSPI1FCLKDIV_REQFLAG_MASK) { + } + /* Enable XSPI clock again */ + CLKCTL0->PSCCTL1_SET = CLKCTL0_PSCCTL1_SET_XSPI1_MASK; + + flash_init(base, CACHE64_CTRL1); + } + } +} + +void xspi_clock_safe_config(void) +{ + xspi_setup_clock(XSPI0, 0U, 1U); + xspi_setup_clock(XSPI1, 0U, 1U); +} diff --git a/soc/nxp/imxrt/imxrt7xx/cm33/pinctrl_soc.h b/soc/nxp/imxrt/imxrt7xx/cm33/pinctrl_soc.h new file mode 100644 index 00000000000..6d5f2a640bc --- /dev/null +++ b/soc/nxp/imxrt/imxrt7xx/cm33/pinctrl_soc.h @@ -0,0 +1,87 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_SOC_ARM_NXP_IMX_RT7XX_PINCTRL_SOC_H_ +#define ZEPHYR_SOC_ARM_NXP_IMX_RT7XX_PINCTRL_SOC_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** @cond INTERNAL_HIDDEN */ + +typedef uint32_t pinctrl_soc_pin_t; + +#define IOPCTL_PIO_PUPDENA_MASK (0x10U) +#define IOPCTL_PIO_PUPDSEL_MASK (0x20U) + +#define IOPCTL_PIO_ODENA_MASK (0x400U) +#define IOPCTL_PIO_ODENA_SHIFT (10U) +#define IOPCTL_PIO_ODENA(x) \ + (((uint32_t)(((uint32_t)(x)) << IOPCTL_PIO_ODENA_SHIFT)) & IOPCTL_PIO_ODENA_MASK) + +#define IOPCTL_PIO_IBENA_MASK (0x40U) +#define IOPCTL_PIO_IBENA_SHIFT (6U) +#define IOPCTL_PIO_IBENA(x) \ + (((uint32_t)(((uint32_t)(x)) << IOPCTL_PIO_IBENA_SHIFT)) & IOPCTL_PIO_IBENA_MASK) + +/* Please note there is no SLEWRATE attribution on IOPCTL2 */ +#define IOPCTL_PIO_SLEWRATE_MASK (0x80U) +#define IOPCTL_PIO_SLEWRATE_SHIFT (7U) +#define IOPCTL_PIO_SLEWRATE(x) \ + (((uint32_t)(((uint32_t)(x)) << IOPCTL_PIO_SLEWRATE_SHIFT)) & IOPCTL_PIO_SLEWRATE_MASK) + +/* Please note there is no FULLDRIVE attribution on IOPCTL2 */ +#define IOPCTL_PIO_FULLDRIVE_MASK (0x100U) +#define IOPCTL_PIO_FULLDRIVE_SHIFT (8U) +#define IOPCTL_PIO_FULLDRIVE(x) \ + (((uint32_t)(((uint32_t)(x)) << IOPCTL_PIO_FULLDRIVE_SHIFT)) & IOPCTL_PIO_FULLDRIVE_MASK) + +#define IOPCTL_PIO_IIENA_MASK (0x800U) +#define IOPCTL_PIO_IIENA_SHIFT (11U) +#define IOPCTL_PIO_IIENA(x) \ + (((uint32_t)(((uint32_t)(x)) << IOPCTL_PIO_IIENA_SHIFT)) & IOPCTL1_PIO_IIENA_MASK) + +/* Please note there is no AMENA attribution on IOPCTL2 */ +#define IOPCTL_PIO_AMENA_MASK (0x200U) +#define IOPCTL_PIO_AMENA_SHIFT (9U) +#define IOPCTL_PIO_AMENA(x) \ + (((uint32_t)(((uint32_t)(x)) << IOPCTL_PIO_AMENA_SHIFT)) & IOPCTL_PIO_AMENA_MASK) + +#define Z_PINCTRL_IOPCTL_PINCFG(node_id) \ + (IF_ENABLED(DT_PROP(node_id, bias_pull_down), \ + (IOPCTL_PIO_PUPDENA_MASK |)) /* pull down */ \ + IF_ENABLED(DT_PROP(node_id, bias_pull_up), \ + (IOPCTL_PIO_PUPDENA_MASK | IOPCTL_PIO_PUPDSEL_MASK |)) /* pull up */ \ + IOPCTL_PIO_ODENA(DT_PROP(node_id, drive_open_drain)) | /* open drain */ \ + IOPCTL_PIO_IBENA(DT_PROP(node_id, input_enable)) | /* input buffer */ \ + IOPCTL_PIO_SLEWRATE(DT_ENUM_IDX(node_id, slew_rate)) | /* slew rate */ \ + IOPCTL_PIO_FULLDRIVE( \ + DT_ENUM_IDX(node_id, drive_strength)) | /* drive strength */ \ + IOPCTL_PIO_IIENA(DT_PROP(node_id, nxp_invert)) | /* invert input */ \ + IOPCTL_PIO_AMENA( \ + DT_PROP(node_id, nxp_analog_mode))) /* analog multiplexor */ + +/* MCUX RT parts only have one pin type */ +#define Z_PINCTRL_IOCON_D_PIN_MASK (0xFFF) +#define Z_PINCTRL_IOCON_A_PIN_MASK (0) +#define Z_PINCTRL_IOCON_I_PIN_MASK (0) + +#define Z_PINCTRL_STATE_PIN_INIT(group, pin_prop, idx) \ + DT_PROP_BY_IDX(group, pin_prop, idx), + +#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \ + {DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), DT_FOREACH_PROP_ELEM, pinmux, \ + Z_PINCTRL_STATE_PIN_INIT)} + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_SOC_ARM_NXP_IMX_RT7XX_PINCTRL_SOC_H_ */ diff --git a/soc/nxp/imxrt/imxrt7xx/cm33/soc.c b/soc/nxp/imxrt/imxrt7xx/cm33/soc.c new file mode 100644 index 00000000000..d8675dd02db --- /dev/null +++ b/soc/nxp/imxrt/imxrt7xx/cm33/soc.c @@ -0,0 +1,27 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief System/hardware module for NXP RT7XX platform + * + * This module provides routines to initialize and support board-level + * hardware for the RT7XX platforms. + */ + +#include +#include +#include +#include + +#ifdef CONFIG_SOC_RESET_HOOK + +void soc_reset_hook(void) +{ + SystemInit(); +} + +#endif /* CONFIG_SOC_RESET_HOOK */ diff --git a/soc/nxp/imxrt/imxrt7xx/cm33/soc.h b/soc/nxp/imxrt/imxrt7xx/cm33/soc.h new file mode 100644 index 00000000000..777c19f435c --- /dev/null +++ b/soc/nxp/imxrt/imxrt7xx/cm33/soc.h @@ -0,0 +1,36 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Board configuration macros for the MIMXRT7XX platform + * + * This header file is used to specify and describe board-level aspects for the + * 'MIMXRT7XX' platform. + */ + +#ifndef _SOC__H_ +#define _SOC__H_ + +#ifndef _ASMLANGUAGE + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +void xspi_clock_safe_config(void); +void xspi_setup_clock(XSPI_Type *base, uint32_t src, uint32_t divider); + +#ifdef __cplusplus +} +#endif + +#endif /* !_ASMLANGUAGE */ + +#endif /* _SOC__H_ */ diff --git a/soc/nxp/imxrt/soc.yml b/soc/nxp/imxrt/soc.yml index 2fd2a0df226..da607add93b 100644 --- a/soc/nxp/imxrt/soc.yml +++ b/soc/nxp/imxrt/soc.yml @@ -38,6 +38,12 @@ family: - name: mimxrt685s cpuclusters: - name: cm33 + - name: imxrt7xx + socs: + - name: mimxrt798s + cpuclusters: + - name: cm33_cpu0 + - name: cm33_cpu1 runners: run_once: '--erase':