boards: arm and arm64: rcar_h3ulcb: Convert to v2

Converts the board to hwmv2

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>

boards/boards_legacy/arm/rcar_h3ulcb/Kconfig.board

@@ -1,6 +0,0 @@
-# Copyright (c) 2021 IoT.bzh
-# SPDX-License-Identifier: Apache-2.0
-
-config BOARD_RCAR_H3ULCB_CR7
-	bool "Cortex-R7 for Renesas H3ULCB"
-	depends on SOC_R8A77951

boards/boards_legacy/arm/rcar_h3ulcb/Kconfig.defconfig

@@ -1,7 +0,0 @@
-# Copyright (c) 2021 IoT.bzh
-# SPDX-License-Identifier: Apache-2.0
-
-if BOARD_RCAR_H3ULCB_CR7
-config BOARD
-	default "rcar_h3ulcb_cr7"
-endif # BOARD_RCAR_H3ULCB_CR7

boards/boards_legacy/arm/rcar_h3ulcb/board.cmake

@@ -1,3 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-board_runner_args(openocd "--use-elf")
-include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)

boards/boards_legacy/arm/rcar_h3ulcb/support/openocd.cfg

@@ -1,88 +0,0 @@
-# Renesas R-Car Gen3 H3ULCB Cortex-R7 Board Config
-
-source [find interface/ftdi/olimex-arm-usb-ocd-h.cfg]
-source [find target/renesas_rcar_reset_common.cfg]
-set _CHIPNAME r8a77951
-set DAP_TAPID 0x5ba00477
-set CA57_0_DBGBASE 0x80410000
-set CA57_0_CTIBASE 0x80420000
-set CR7_DBGBASE 0x80910000
-set CR7_CTIBASE 0x80918000
-
-adapter srst delay 1000
-adapter speed 20000
-global $_CHIPNAME
-transport select jtag
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f -expected-id $DAP_TAPID
-dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
-
-cti create $_CHIPNAME.r7.cti -dap $_CHIPNAME.dap -ap-num 1 -baseaddr $CR7_CTIBASE
-target create $_CHIPNAME.r7 cortex_r4 -dap $_CHIPNAME.dap -ap-num 1 -dbgbase $CR7_DBGBASE -defer-examine
-
-$_CHIPNAME.r7 configure -rtos auto
-
-cti create $_CHIPNAME.a57.0.cti -dap $_CHIPNAME.dap -ap-num 1 -baseaddr $CA57_0_CTIBASE
-target create $_CHIPNAME.a57.0 aarch64 -dap $_CHIPNAME.dap -ap-num 1 -dbgbase $CA57_0_DBGBASE -cti $_CHIPNAME.a57.0.cti
-
-proc reset_cr7 { assert } {
-    global _CHIPNAME
-    if { $assert == 1 } {
-	# Software Reset Register 2 Bit(22) Arm Realtime core
-	$_CHIPNAME.a57.0 mww 0xe61500b0 0x00400000
-    } else {
-	# Software Reset Clearing Register 2 Bit(22) Arm Realtime core
-	$_CHIPNAME.a57.0 mww 0xe6150948 0x00400000
-    }
-}
-
-# This function make use of A5x processor to:
-# - Power on the CR7 (PWRONCR7)
-# - Set the boot address (CR7BAR)
-# - Halt the processor
-# - Deassert the CR7 reset
-proc start_cr7 { args } {
-    global _CHIPNAME
-
-    targets $_CHIPNAME.a57.0
-    $_CHIPNAME.a57.0 arp_halt
-
-    # CR7BAR RBAR [31:18] BAREN bit(4)
-    $_CHIPNAME.a57.0 mww 0xe6160070 0x40040010
-
-    # PWRONCR7
-    $_CHIPNAME.a57.0 mww 0xe618024c 1
-    # Wait until power is on. Also possible to
-    # poll PWRSR7 and CR7PSTR register.
-    sleep 100
-
-    $_CHIPNAME.r7 arp_examine
-    catch { $_CHIPNAME.r7 arp_halt }
-    reset_cr7 0
-
-    # resume a5x processor or cmt timer will not run
-    resume
-    # set CR7 processor as default target for future commands
-    targets $_CHIPNAME.r7
-}
-
-$_CHIPNAME.r7 configure -event reset-end {
-     global _CHIPNAME
-     targets $_CHIPNAME.a57.0
-     # Resume the A57 processor and gives
-     # enough time to A57 bootloaders to set-up dram
-     # clocks, power management, security groups
-     resume
-     sleep 500
-     $_CHIPNAME.a57.0 arp_halt
-     $_CHIPNAME.a57.0 arp_poll
-     start_cr7
-}
-
-$_CHIPNAME.a57.0 configure -event examine-end {
-     start_cr7
-}
-
-$_CHIPNAME.r7 configure -event gdb-attach {
-     reset halt
-}

boards/boards_legacy/arm64/rcar_h3ulcb_ca57/Kconfig.board

@@ -1,6 +0,0 @@
-# Copyright (c) 2023 EPAM Systems
-# SPDX-License-Identifier: Apache-2.0
-
-config BOARD_RCAR_H3ULCB_CA57
-	bool "Renesas H3ULCB"
-	depends on SOC_ARM64_R8A77951

boards/renesas/rcar_h3ulcb/Kconfig.defconfig

@@ -1,12 +1,9 @@
 # Copyright (c) 2023 EPAM Systems
 # SPDX-License-Identifier: Apache-2.0
 
-if BOARD_RCAR_H3ULCB_CA57
+if BOARD_RCAR_H3ULCB
-
-config BOARD
-	default "rcar_h3ulcb_ca57"
 
 config BUILD_OUTPUT_BIN
 	default y
 
-endif # BOARD_RCAR_H3ULCB_CA57
+endif # BOARD_RCAR_H3ULCB

boards/renesas/rcar_h3ulcb/Kconfig.rcar_h3ulcb

@@ -0,0 +1,6 @@
+# Copyright (c) 2023 EPAM Systems
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_RCAR_H3ULCB
+	select SOC_R8A77951_R7 if BOARD_RCAR_H3ULCB_R8A77951_R7
+	select SOC_R8A77951_A57 if BOARD_RCAR_H3ULCB_R8A77951_A57

boards/renesas/rcar_h3ulcb/board.cmake

@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_BOARD_RCAR_H3ULCB_R8A77951_R7)
+  board_runner_args(openocd "--use-elf")
+  include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
+endif()

boards/renesas/rcar_h3ulcb/board.yml

@@ -0,0 +1,5 @@
+board:
+  name: rcar_h3ulcb
+  vendor: Renesas
+  socs:
+  - name: r8a77951

boards/renesas/rcar_h3ulcb/doc/rcar_h3ulcb_a57.rst

@@ -61,9 +61,8 @@ hardware features:
 
 Other hardware features have not been enabled yet for this board.
 
-The default configuration can be found in the defconfig file:
+The default configuration can be found in
-
+:zephyr_file:`boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_a57_defconfig``
-        ``boards/arm64/rcar_h3ulcb_ca57/rcar_h3ulcb_ca57_defconfig``
 
 Programming and Debugging
 *************************

boards/renesas/rcar_h3ulcb/doc/rcar_h3ulcb_r7.rst

@@ -205,11 +205,11 @@ Flashing
 
 First of all, open your serial terminal.
 
-Applications for the ``rcar_h3ulcb_cr7`` board configuration can be built in the usual way (see :ref:`build_an_application` for more details).
+Applications for the ``rcar_h3ulcb/r8a77951/r7`` board configuration can be built in the usual way (see :ref:`build_an_application` for more details).
 
 .. zephyr-app-commands::
    :zephyr-app: samples/hello_world
-   :board: rcar_h3ulcb_cr7
+   :board: rcar_h3ulcb/r8a77951/r7
    :goals: flash
 
 You should see the following message in the terminal:
@@ -217,7 +217,7 @@ You should see the following message in the terminal:
 .. code-block:: console
 
 	*** Booting Zephyr OS build v2.6.0-rc1 ***
-	Hello World! rcar_h3ulcb_cr7
+	Hello World! rcar_h3ulcb
 
 Debugging
 =========
@@ -228,7 +228,7 @@ Here is an example for the :ref:`hello_world` application.
 
 .. zephyr-app-commands::
    :zephyr-app: samples/hello_world
-   :board: rcar_h3ulcb_cr7
+   :board: rcar_h3ulcb/r8a77951/r7
    :goals: debug
 
 You will then get access to a GDB session for debug.
@@ -238,7 +238,7 @@ By continuing the app, you should see the following message in the terminal:
 .. code-block:: console
 
 	*** Booting Zephyr OS build v2.6.0-rc1 ***
-	Hello World! rcar_h3ulcb_cr7
+	Hello World! rcar_h3ulcb
 
 References
 **********

boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_a57.dts

@@ -8,7 +8,7 @@
 /dts-v1/;
 #include <mem.h>
 #include <arm64/renesas/r8a77951.dtsi>
-#include "rcar_h3ulcb_ca57-pinctrl.dtsi"
+#include "rcar_h3ulcb_r8a77951_a57-pinctrl.dtsi"
 
 / {
 	model = "H3ULCB CA57";

boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_a57.yaml

@@ -1,4 +1,4 @@
-identifier: rcar_h3ulcb_ca57
+identifier: rcar_h3ulcb/r8a77951/a57
 name: Renesas H3ULCB based on r8a77951
 type: mcu
 arch: arm64

boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_a57_defconfig

@@ -1,6 +1,5 @@
-CONFIG_SOC_ARM64_R8A77951=y
+# Copyright (c) 2023 EPAM Systems
-CONFIG_SOC_SERIES_RCAR_GEN3=y
+# SPDX-License-Identifier: Apache-2.0
-CONFIG_BOARD_RCAR_H3ULCB_CA57=y
 
 # Cache management
 CONFIG_CACHE_MANAGEMENT=y

boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_r7.dts

@@ -7,7 +7,7 @@
 
 /dts-v1/;
 #include <arm/renesas/rcar/gen3/r8a77951.dtsi>
-#include "rcar_h3ulcb_cr7-pinctrl.dtsi"
+#include "rcar_h3ulcb_r8a77951_r7-pinctrl.dtsi"
 #include <zephyr/dt-bindings/input/input-event-codes.h>
 
 / {

boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_r7.yaml

@@ -1,4 +1,4 @@
-identifier: rcar_h3ulcb_cr7
+identifier: rcar_h3ulcb/r8a77951/r7
 name: Cortex r7 for Renesas H3ULCB
 type: mcu
 arch: arm

boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_r7_defconfig

@@ -1,6 +1,3 @@
-CONFIG_SOC_R8A77951=y
-CONFIG_SOC_SERIES_RCAR_GEN3=y
-CONFIG_BOARD_RCAR_H3ULCB_CR7=y
 CONFIG_CLOCK_CONTROL=y
 CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=32000
 CONFIG_CONSOLE=y