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@ -0,0 +1,593 @@
@@ -0,0 +1,593 @@
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/*
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* Copyright (c) 2024 Renesas Electronics Corporation |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#define DT_DRV_COMPAT renesas_ra_agt_counter |
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#include <zephyr/devicetree.h> |
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#include <zephyr/drivers/counter.h> |
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#include <zephyr/irq.h> |
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#include <r_agt.h> |
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#include <zephyr/logging/log.h> |
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#define FSUB_FREQUENCY_HZ (32768U) |
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typedef volatile R_AGTX0_AGT16_CTRL_Type agt_reg_ctrl_t; |
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#define AGT_AGTCR_STOP_TIMER 0xF0U /* 1111 0000 */ |
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#define AGT_AGTCR_START_TIMER 0xF1U /* 1111 0001 */ |
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#define AGT_AGTCR_FLAGS_MASK 0xF0U /* 1111 0000 */ |
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#define AGT_PRV_MIN_CLOCK_FREQ (0U) |
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#define AGT_SOURCE_CLOCK_PCLKB_BITS (0x3U) |
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LOG_MODULE_REGISTER(ra_agt_counter, CONFIG_COUNTER_LOG_LEVEL); |
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struct counter_ra_agt_config { |
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/* info must be first element */ |
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struct counter_config_info info; /* Counter Config info struct */ |
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uint32_t channel; /* Channel no */ |
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uint32_t cycle_end_irq; /* Underflow interrupt*/ |
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uint32_t cycle_end_ipl; /* Underflow interrupt priority */ |
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uint32_t channel_ipl; /* IPL channel no. */ |
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uint32_t channel_irq; /* IRQ channel no. */ |
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/* Device tree data */ |
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timer_source_div_t source_div; /* Clock source divider */ |
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agt_agtio_filter_t agtio_filter; /* Input filter for AGTIO */ |
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agt_measure_t measurement_mode; /* Measurement mode */ |
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agt_clock_t count_source; /* AGT channel clock source */ |
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uint32_t resolution; /* AGT node resolution */ |
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uint32_t dt_reg; /* Reg address from device tree */ |
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}; |
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struct counter_ra_agt_alarm { |
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counter_alarm_callback_t callback; |
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void *data; |
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}; |
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struct counter_ra_agt_data { |
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/* Common data */ |
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R_AGTX0_Type *agt_reg; /* AGT register base address */ |
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uint32_t period; /* Current timer period (counts) */ |
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uint32_t period_counts; /* Period in raw timer counts */ |
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uint32_t cycle_end_ipl; /* Cycle end interrupt priority */ |
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IRQn_Type cycle_end_irq; /* Cycle end interrupt */ |
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/* Alarm-related data */ |
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struct counter_ra_agt_alarm alarm; /* Counter alarm config struct */ |
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counter_top_callback_t top_cb; /* Top level callback */ |
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void *top_cb_data; /* Top level callback data */ |
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uint32_t guard_period; /* Absolute counter alarm's guard period */ |
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}; |
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static void r_agt_hardware_cfg(const struct device *dev); |
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static void r_agt_period_register_set(const struct device *dev, uint32_t period_counts); |
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static uint32_t r_agt_clock_frequency_get(agt_reg_ctrl_t *p_reg); |
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static fsp_err_t r_agt_common_preamble(agt_reg_ctrl_t *p_reg); |
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static agt_reg_ctrl_t *r_agt_reg_ctrl_get(const struct device *dev); |
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static uint32_t r_agt_ticks_sub(uint32_t val, uint32_t old, uint32_t top); |
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static int counter_ra_agt_start(const struct device *dev) |
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{ |
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agt_reg_ctrl_t *const reg = r_agt_reg_ctrl_get(dev); |
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uint32_t timeout = UINT32_MAX; |
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reg->AGTCR = AGT_AGTCR_START_TIMER; |
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while (!(reg->AGTCR & BIT(R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Pos)) && likely(--timeout)) |
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; |
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return timeout > 0 ? 0 : -EIO; |
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} |
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static int counter_ra_agt_stop(const struct device *dev) |
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{ |
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agt_reg_ctrl_t *const reg = r_agt_reg_ctrl_get(dev); |
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uint32_t timeout = UINT32_MAX; |
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reg->AGTCR = AGT_AGTCR_STOP_TIMER; |
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while ((reg->AGTCR & BIT(R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Pos)) && likely(--timeout)) |
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; |
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return timeout > 0 ? 0 : -EIO; |
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} |
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static inline int counter_ra_agt_read(const struct device *dev) |
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{ |
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struct counter_ra_agt_data *data = dev->data; |
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return data->agt_reg->AGT16.AGT; |
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} |
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static int counter_ra_agt_get_value(const struct device *dev, uint32_t *ticks) |
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{ |
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*ticks = counter_ra_agt_read(dev); |
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return 0; |
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} |
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static uint32_t counter_ra_agt_get_top_value(const struct device *dev) |
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{ |
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const struct counter_ra_agt_config *config = dev->config; |
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return config->info.max_top_value; |
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} |
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static int counter_ra_agt_set_top_value(const struct device *dev, const struct counter_top_cfg *cfg) |
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{ |
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const struct counter_ra_agt_config *config = dev->config; |
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struct counter_ra_agt_data *data = dev->data; |
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agt_reg_ctrl_t *p_reg_ctrl = r_agt_reg_ctrl_get(dev); |
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if (cfg->ticks != config->info.max_top_value) { |
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return -ENOTSUP; |
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} |
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if (cfg->callback == NULL) { |
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/* Disable Match Register A if callback is NULL */ |
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p_reg_ctrl->AGTCR_b.TCMAF = 0; |
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} else { |
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/* Enable Match Register A */ |
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p_reg_ctrl->AGTCR_b.TCMAF = 1; |
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} |
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data->top_cb = cfg->callback; |
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data->top_cb_data = cfg->user_data; |
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return 0; |
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} |
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static inline void counter_ra_agt_set_compare_value(const struct device *dev, uint8_t chan, |
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uint32_t value) |
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{ |
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struct counter_ra_agt_data *data = dev->data; |
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data->agt_reg->AGT16.AGTCMA = value; |
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} |
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static inline void counter_ra_agt_enable_channel_irq(const struct device *dev) |
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{ |
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const struct counter_ra_agt_config *config = dev->config; |
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agt_reg_ctrl_t *p_reg_ctrl = r_agt_reg_ctrl_get(dev); |
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/* Enable AGT compare match A */ |
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p_reg_ctrl->AGTCMSR |= BIT(R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Pos); |
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irq_enable(config->channel_irq); |
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} |
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static inline void counter_ra_agt_clear_channel_irq(const struct device *dev) |
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{ |
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const struct counter_ra_agt_config *config = dev->config; |
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agt_reg_ctrl_t *const reg_ctrl = r_agt_reg_ctrl_get(dev); |
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reg_ctrl->AGTCR_b.TCMAF = 0; |
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R_BSP_IrqStatusClear(config->channel_irq); |
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NVIC_ClearPendingIRQ(config->channel_irq); |
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} |
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static int counter_ra_agt_set_alarm(const struct device *dev, uint8_t chan, |
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const struct counter_alarm_cfg *alarm_cfg) |
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{ |
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struct counter_ra_agt_data *data = dev->data; |
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const struct counter_ra_agt_config *config = dev->config; |
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const bool absolute = alarm_cfg->flags & COUNTER_ALARM_CFG_ABSOLUTE; |
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const uint32_t top = counter_ra_agt_get_top_value(dev); |
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struct counter_ra_agt_alarm *const alarm = &data->alarm; |
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uint16_t val = alarm_cfg->ticks; |
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uint32_t now; |
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uint32_t max_rel_val; |
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bool irq_on_late; |
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int32_t diff = 0; |
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int err = 0; |
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if (alarm_cfg->ticks > counter_ra_agt_get_top_value(dev)) { |
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LOG_ERR("%s: alarm ticks is larger than top value", __func__); |
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return -EINVAL; |
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} |
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if (alarm->callback) { |
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LOG_ERR("%s: Device busy. Callback is still available.", __func__); |
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return -EBUSY; |
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} |
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alarm->callback = alarm_cfg->callback; |
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alarm->data = alarm_cfg->user_data; |
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/*
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* stop AGT for writing the match register directly instead of sync when underflow event |
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* occur reference: RA6M5 User manual - 22.3.2 Reload Register and AGT Compare Match A/B |
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* Register Rewrite Operation |
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*/ |
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counter_ra_agt_stop(dev); |
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now = counter_ra_agt_read(dev); |
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if (absolute) { |
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/* Acceptable alarm value range, counting from current tick (now) */ |
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max_rel_val = top - data->guard_period; |
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irq_on_late = alarm_cfg->flags & COUNTER_ALARM_CFG_EXPIRE_WHEN_LATE; |
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} else { |
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/* If relative value is smaller than half of the counter range
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* it is assumed that there is a risk of setting value too late |
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* and late detection algorithm must be applied. When late |
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* setting is detected, interrupt shall be triggered for |
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* immediate expiration of the timer. Detection is performed |
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* by limiting relative distance between CC and counter. |
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* |
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* Note that half of counter range is an arbitrary value. |
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*/ |
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irq_on_late = (val < (top / 2U)); |
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/* Limit max to detect short relative being set too late */ |
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max_rel_val = irq_on_late ? top / 2U : top; |
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/* Recalculate alarm tick timestamp based on current tick (now) */ |
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val = r_agt_ticks_sub(now, val, top); |
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} |
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counter_ra_agt_set_compare_value(dev, chan, val); |
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/* Decrement value to detect also case when val == counter_ra_agt_read(dev).
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* Otherwise, condition would need to include comparing diff against 0. |
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*/ |
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diff = r_agt_ticks_sub(now, val - 1, top); |
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if (diff > max_rel_val) { |
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if (absolute) { |
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err = -ETIME; |
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} |
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/* Interrupt is triggered always for relative alarm and
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* for absolute depending on the flag. |
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*/ |
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if (irq_on_late) { |
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/* Set pending IRQ */ |
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counter_ra_agt_enable_channel_irq(dev); |
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NVIC_SetPendingIRQ(config->channel_irq); |
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} else { |
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alarm->callback = NULL; |
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alarm->data = NULL; |
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} |
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} |
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counter_ra_agt_clear_channel_irq(dev); |
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counter_ra_agt_enable_channel_irq(dev); |
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counter_ra_agt_start(dev); |
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return err; |
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} |
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static int counter_ra_agt_cancel_alarm(const struct device *dev, uint8_t chan) |
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{ |
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struct counter_ra_agt_data *data = dev->data; |
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agt_reg_ctrl_t *p_reg_ctrl = r_agt_reg_ctrl_get(dev); |
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/* Disable AGT compare match A */ |
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p_reg_ctrl->AGTCMSR &= ~BIT(R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Pos); |
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data->alarm.callback = NULL; |
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data->alarm.data = NULL; |
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return 0; |
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} |
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static uint32_t counter_ra_agt_get_pending_int(const struct device *dev) |
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{ |
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agt_reg_ctrl_t *const reg = r_agt_reg_ctrl_get(dev); |
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return (reg->AGTCR & AGT_AGTCR_FLAGS_MASK) != 0; |
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} |
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static uint32_t counter_ra_agt_get_freq(const struct device *dev) |
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{ |
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struct counter_ra_agt_data *data = dev->data; |
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timer_info_t info; |
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agt_reg_ctrl_t *p_reg = r_agt_reg_ctrl_get(dev); |
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r_agt_common_preamble(p_reg); |
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/* Get and store period */ |
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info.period_counts = data->period; |
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info.clock_frequency = r_agt_clock_frequency_get(p_reg); |
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/* AGT supports only counting down direction */ |
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info.count_direction = TIMER_DIRECTION_DOWN; |
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return info.clock_frequency; |
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} |
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static void counter_ra_agt_agti_isr(const struct device *dev) |
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{ |
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const struct counter_ra_agt_config *config = dev->config; |
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struct counter_ra_agt_data *data = dev->data; |
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agt_reg_ctrl_t *const reg_ctrl = r_agt_reg_ctrl_get(dev); |
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R_BSP_IrqStatusClear(config->cycle_end_irq); |
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const uint32_t agtcr = reg_ctrl->AGTCR; |
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if (agtcr & BIT(R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Pos)) { |
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if (data->top_cb) { |
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data->top_cb(dev, data->top_cb_data); |
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} |
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} |
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reg_ctrl->AGTCR = (uint8_t)(agtcr & ~(BIT(R_AGTX0_AGT16_CTRL_AGTCR_TUNDF_Pos) | |
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BIT(R_AGTX0_AGT16_CTRL_AGTCR_TEDGF_Pos))); |
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} |
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static void counter_ra_agt_agtcmai_isr(const struct device *dev) |
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{ |
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const struct counter_ra_agt_config *config = dev->config; |
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struct counter_ra_agt_data *data = dev->data; |
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agt_reg_ctrl_t *const reg_ctrl = r_agt_reg_ctrl_get(dev); |
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struct counter_ra_agt_alarm *const alarm = &data->alarm; |
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const uint32_t val = data->agt_reg->AGT16.AGTCMA; |
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const counter_alarm_callback_t cb = alarm->callback; |
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void *cb_data = alarm->data; |
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alarm->callback = NULL; |
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alarm->data = NULL; |
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/* Disable AGT compare match A */ |
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reg_ctrl->AGTCMSR &= ~BIT(R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Pos); |
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R_BSP_IrqStatusClear(config->channel_irq); |
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if (cb) { |
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cb(dev, config->channel, val, cb_data); |
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} |
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reg_ctrl->AGTCR_b.TCMAF = 0; |
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} |
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static uint32_t counter_ra_agt_get_guard_period(const struct device *dev, uint32_t flags) |
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{ |
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struct counter_ra_agt_data *data = dev->data; |
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return data->guard_period; |
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} |
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static int counter_ra_agt_set_guard_period(const struct device *dev, uint32_t guard, uint32_t flags) |
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{ |
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struct counter_ra_agt_data *data = dev->data; |
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if (counter_ra_agt_get_top_value(dev) < guard) { |
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LOG_ERR("%s: Invalid guard rate", __func__); |
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return -EINVAL; |
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} |
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data->guard_period = guard; |
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return 0; |
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} |
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static int counter_ra_agt_init(const struct device *dev) |
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{ |
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const struct counter_ra_agt_config *config = dev->config; |
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struct counter_ra_agt_data *data = dev->data; |
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data->agt_reg = (R_AGTX0_Type *)config->dt_reg; |
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agt_reg_ctrl_t *p_reg_ctrl = r_agt_reg_ctrl_get(dev); |
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/* Power on the AGT channel */ |
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R_BSP_MODULE_START(FSP_IP_AGT, config->channel); |
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/* Clear AGTCR. This stops the timer if it is running and clears the flags */ |
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p_reg_ctrl->AGTCR = 0U; |
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/* The timer is stopped in sync with the count clock, or in sync with PCLK in event and
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* external count modes. |
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*/ |
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FSP_HARDWARE_REGISTER_WAIT(0U, p_reg_ctrl->AGTCR_b.TCSTF); |
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/* Clear AGTMR2 before AGTMR1 is set. Reference Note 3 in section 25.2.6 "AGT Mode Register
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* 2 (AGTMR2)" of the RA6M3 manual R01UH0886EJ0100. |
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*/ |
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p_reg_ctrl->AGTMR2 = 0U; |
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/* Set count source and divider and configure pins */ |
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r_agt_hardware_cfg(dev); |
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/* Set period register and update duty cycle if output mode is used for one-shot or periodic
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* mode. |
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*/ |
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r_agt_period_register_set(dev, data->period_counts); |
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/* 22.3.1 Reload Register and Counter Rewrite Operation */ |
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p_reg_ctrl->AGTCMSR |= BIT(R_AGTX0_AGT16_CTRL_AGTCMSR_TCMEA_Pos); |
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return 0; |
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} |
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static agt_reg_ctrl_t *r_agt_reg_ctrl_get(const struct device *dev) |
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{ |
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struct counter_ra_agt_data *data = dev->data; |
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agt_reg_ctrl_t *p_reg_ctrl = &data->agt_reg->AGT16.CTRL; |
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return p_reg_ctrl; |
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} |
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static void r_agt_hardware_cfg(const struct device *dev) |
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{ |
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const struct counter_ra_agt_config *config = dev->config; |
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/* Update the divider for PCLKB */ |
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agt_reg_ctrl_t *p_reg_ctrl = r_agt_reg_ctrl_get(dev); |
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uint32_t count_source_int = (uint32_t)config->count_source; |
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uint32_t agtmr2 = 0U; |
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uint32_t agtcmsr = 0U; |
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uint32_t tedgsel = 0U; |
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uint32_t agtioc = config->agtio_filter; |
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uint32_t mode = config->measurement_mode & R_AGTX0_AGT16_CTRL_AGTMR1_TMOD_Msk; |
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uint32_t edge = 0U; |
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if (AGT_CLOCK_PCLKB == config->count_source) { |
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if (TIMER_SOURCE_DIV_1 != config->source_div) { |
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/* Toggle the second bit if the count_source_int is not 0 to map PCLKB / 8
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* to 1 and PCLKB / 2 to 3. |
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*/ |
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count_source_int = config->source_div ^ 2U; |
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count_source_int <<= R_AGTX0_AGT16_CTRL_AGTMR1_TCK_Pos; |
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} |
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} |
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else if (AGT_CLOCK_AGT_UNDERFLOW != config->count_source) { |
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/* Update the divider for LOCO/subclock */ |
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agtmr2 = config->source_div; |
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} else { |
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/* No divider can be used when count source is AGT_CLOCK_AGT_UNDERFLOW */ |
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} |
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uint32_t agtmr1 = (count_source_int | edge) | mode; |
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/* Configure output settings */ |
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agtioc |= tedgsel; |
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p_reg_ctrl->AGTIOC = (uint8_t)agtioc; |
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p_reg_ctrl->AGTCMSR = (uint8_t)agtcmsr; |
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p_reg_ctrl->AGTMR1 = (uint8_t)agtmr1; |
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p_reg_ctrl->AGTMR2 = (uint8_t)agtmr2; |
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|
} |
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static void r_agt_period_register_set(const struct device *dev, uint32_t period_counts) |
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{ |
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struct counter_ra_agt_data *data = dev->data; |
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/* Store the period value so it can be retrieved later */ |
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data->period = period_counts; |
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|
/* Set counter to period minus one */ |
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uint32_t period_reg = (period_counts - 1U); |
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data->agt_reg->AGT16.AGT = (uint16_t)period_reg; |
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} |
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static uint32_t r_agt_clock_frequency_get(agt_reg_ctrl_t *p_reg) |
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|
|
{ |
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|
uint32_t clock_freq_hz = 0U; |
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|
uint8_t count_source_int = p_reg->AGTMR1_b.TCK; |
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timer_source_div_t divider = TIMER_SOURCE_DIV_1; |
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if (0U == (count_source_int & (~AGT_SOURCE_CLOCK_PCLKB_BITS))) { |
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|
|
/* Call CGC function to obtain current PCLKB clock frequency */ |
|
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|
|
clock_freq_hz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKB); |
|
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|
|
/* If Clock source is PCLKB or derived from PCLKB */ |
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|
|
divider = (timer_source_div_t)count_source_int; |
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|
|
if (divider != 0U) { |
|
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|
|
/* Set divider to 3 to divide by 8 when AGTMR1.TCK is 1 (PCLKB / 8). Set
|
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|
|
* divider to 1 to divide by 2 when AGTMR1.TCK is 3 (PCLKB / 2). XOR with 2 |
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|
* to convert 1 to 3 and 3 to 1. |
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|
*/ |
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|
divider ^= 2U; |
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|
|
} |
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|
|
} else { |
|
|
|
|
/* Else either fSUB clock or LOCO clock is used. The frequency is set to 32Khz
|
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|
|
* (32768). This function does not support AGT0 underflow as count source. |
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|
|
|
*/ |
|
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|
|
clock_freq_hz = FSUB_FREQUENCY_HZ; |
|
|
|
|
divider = (timer_source_div_t)p_reg->AGTMR2_b.CKS; |
|
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|
|
} |
|
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|
|
clock_freq_hz >>= divider; |
|
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|
|
return clock_freq_hz; |
|
|
|
|
} |
|
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|
|
static fsp_err_t r_agt_common_preamble(agt_reg_ctrl_t *p_reg) |
|
|
|
|
{ |
|
|
|
|
/* Ensure timer state reflects expected status. Reference section 25.4.1 "Count Operation
|
|
|
|
|
* Start and Stop Control" in the RA6M3 manual R01UH0886EJ0100. |
|
|
|
|
*/ |
|
|
|
|
uint32_t agtcr_tstart = p_reg->AGTCR_b.TSTART; |
|
|
|
|
|
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|
|
FSP_HARDWARE_REGISTER_WAIT(agtcr_tstart, p_reg->AGTCR_b.TCSTF); |
|
|
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|
|
return FSP_SUCCESS; |
|
|
|
|
} |
|
|
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|
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|
|
static uint32_t r_agt_ticks_sub(uint32_t val, uint32_t old, uint32_t top) |
|
|
|
|
{ |
|
|
|
|
if (likely(IS_BIT_MASK(top))) { |
|
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|
|
return (val - old) & top; |
|
|
|
|
} |
|
|
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|
|
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|
|
/* if top is not 2^n-1 */ |
|
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|
|
return (val >= old) ? (val - old) : val + top + 1 - old; |
|
|
|
|
} |
|
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|
|
static const struct counter_driver_api ra_agt_driver_api = { |
|
|
|
|
.start = counter_ra_agt_start, |
|
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|
|
.stop = counter_ra_agt_stop, |
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|
|
.get_value = counter_ra_agt_get_value, |
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|
|
.set_alarm = counter_ra_agt_set_alarm, |
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|
|
.cancel_alarm = counter_ra_agt_cancel_alarm, |
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|
|
.set_top_value = counter_ra_agt_set_top_value, |
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|
|
.get_pending_int = counter_ra_agt_get_pending_int, |
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|
|
.get_top_value = counter_ra_agt_get_top_value, |
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|
|
.get_freq = counter_ra_agt_get_freq, |
|
|
|
|
.get_guard_period = counter_ra_agt_get_guard_period, |
|
|
|
|
.set_guard_period = counter_ra_agt_set_guard_period, |
|
|
|
|
}; |
|
|
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|
|
|
|
#define TIMER(idx) DT_INST_PARENT(idx) |
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|
|
#define _ELC_EVENT_AGT_INT(channel) ELC_EVENT_AGT##channel##_INT |
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|
|
#define _ELC_EVENT_AGT_COMPARE_A(channel) ELC_EVENT_AGT##channel##_COMPARE_A |
|
|
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|
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|
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|
|
#define ELC_EVENT_AGT_INT(channel) _ELC_EVENT_AGT_INT(channel) |
|
|
|
|
#define ELC_EVENT_AGT_COMPARE_A(channel) _ELC_EVENT_AGT_COMPARE_A(channel) |
|
|
|
|
|
|
|
|
|
#define AGT_DEVICE_INIT_RA(n) \ |
|
|
|
|
static const struct counter_ra_agt_config ra_agt_config_##n = { \ |
|
|
|
|
.info = \ |
|
|
|
|
{ \ |
|
|
|
|
.max_top_value = UINT16_MAX, \ |
|
|
|
|
.freq = 0, \ |
|
|
|
|
.channels = 1, \ |
|
|
|
|
.flags = 0, \ |
|
|
|
|
}, \ |
|
|
|
|
.agtio_filter = AGT_AGTIO_FILTER_NONE, \ |
|
|
|
|
.measurement_mode = 0U, \ |
|
|
|
|
.source_div = DT_PROP(TIMER(n), prescaler), \ |
|
|
|
|
.count_source = DT_STRING_TOKEN(TIMER(n), count_source), \ |
|
|
|
|
.channel = DT_PROP(TIMER(n), channel), \ |
|
|
|
|
.channel_irq = DT_IRQ_BY_NAME(TIMER(n), agtcmai, irq), \ |
|
|
|
|
.channel_ipl = DT_IRQ_BY_NAME(TIMER(n), agtcmai, priority), \ |
|
|
|
|
.cycle_end_irq = DT_IRQ_BY_NAME(TIMER(n), agti, irq), \ |
|
|
|
|
.cycle_end_ipl = DT_IRQ_BY_NAME(TIMER(n), agti, priority), \ |
|
|
|
|
.resolution = DT_PROP(TIMER(n), resolution), \ |
|
|
|
|
.dt_reg = DT_REG_ADDR(TIMER(n)), \ |
|
|
|
|
}; \ |
|
|
|
|
\ |
|
|
|
|
static struct counter_ra_agt_data counter_ra_agt_data_##n = { \ |
|
|
|
|
.period_counts = 0, \ |
|
|
|
|
}; \ |
|
|
|
|
\ |
|
|
|
|
static int counter_ra_agt_##n##_init(const struct device *dev) \ |
|
|
|
|
{ \ |
|
|
|
|
R_ICU->IELSR[DT_IRQ_BY_NAME(TIMER(n), agti, irq)] = \ |
|
|
|
|
ELC_EVENT_AGT_INT(DT_PROP(TIMER(n), channel)); \ |
|
|
|
|
IRQ_CONNECT(DT_IRQ_BY_NAME(TIMER(n), agti, irq), \ |
|
|
|
|
DT_IRQ_BY_NAME(TIMER(n), agti, priority), counter_ra_agt_agti_isr, \ |
|
|
|
|
DEVICE_DT_INST_GET(n), 0); \ |
|
|
|
|
irq_enable(DT_IRQ_BY_NAME(TIMER(n), agti, irq)); \ |
|
|
|
|
\ |
|
|
|
|
R_ICU->IELSR[DT_IRQ_BY_NAME(TIMER(n), agtcmai, irq)] = \ |
|
|
|
|
ELC_EVENT_AGT_COMPARE_A(DT_PROP(TIMER(n), channel)); \ |
|
|
|
|
IRQ_CONNECT(DT_IRQ_BY_NAME(TIMER(n), agtcmai, irq), \ |
|
|
|
|
DT_IRQ_BY_NAME(TIMER(n), agtcmai, priority), \ |
|
|
|
|
counter_ra_agt_agtcmai_isr, DEVICE_DT_INST_GET(n), 0); \ |
|
|
|
|
irq_disable(DT_IRQ_BY_NAME(TIMER(n), agtcmai, irq)); \ |
|
|
|
|
\ |
|
|
|
|
return counter_ra_agt_init(dev); \ |
|
|
|
|
} \ |
|
|
|
|
\ |
|
|
|
|
DEVICE_DT_INST_DEFINE(n, counter_ra_agt_##n##_init, NULL, &counter_ra_agt_data_##n, \ |
|
|
|
|
&ra_agt_config_##n, POST_KERNEL, CONFIG_COUNTER_INIT_PRIORITY, \ |
|
|
|
|
&ra_agt_driver_api); |
|
|
|
|
|
|
|
|
|
DT_INST_FOREACH_STATUS_OKAY(AGT_DEVICE_INIT_RA) |
Thao Luong
1 year ago
committed by
Henrik Brix Andersen