drivers: spi_xmc4xxx: Add delay when changing clock polarity

The passive level of the clock does not change instanteneously when
it's set using function XMC_SPI_CH_ConfigureShiftClockOutput().
This means that the passive level of the clock can be in the wrong
state when the chip select goes low.

Fix this by adding a small delay when the polarity changes to allow
the clock to return to the proper level.

Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>

drivers/spi/spi_xmc4xxx.c

@@ -23,6 +23,7 @@ LOG_MODULE_REGISTER(spi_xmc4xxx);
 #define USIC_IRQ_MIN  84
 #define USIC_IRQ_MAX  101
 #define IRQS_PER_USIC 6
+#define CLOCK_POLARITY_CHANGE_DELAY 10
 
 #define SPI_XMC4XXX_DMA_ERROR_FLAG   BIT(0)
 #define SPI_XMC4XXX_DMA_RX_DONE_FLAG BIT(1)
@@ -189,6 +190,7 @@ static void spi_xmc4xxx_isr(const struct device *dev)
 static int spi_xmc4xxx_configure(const struct device *dev, const struct spi_config *spi_cfg)
 {
 	int ret;
+	bool clock_polarity_delay = false;
 	struct spi_xmc4xxx_data *data = dev->data;
 	const struct spi_xmc4xxx_config *config = dev->config;
 	struct spi_context *ctx = &data->ctx;
@@ -203,6 +205,11 @@ static int spi_xmc4xxx_configure(const struct device *dev, const struct spi_conf
 		return 0;
 	}
 
+	if (ctx->config == NULL ||
+	    ((SPI_MODE_GET(ctx->config->operation) & SPI_MODE_CPOL) != CPOL)) {
+		clock_polarity_delay = true;
+	}
+
 	ctx->config = spi_cfg;
 
 	if (spi_cfg->operation & SPI_HALF_DUPLEX) {
@@ -253,6 +260,10 @@ static int spi_xmc4xxx_configure(const struct device *dev, const struct spi_conf
 
 	XMC_SPI_CH_SetWordLength(config->spi, 8);
 
+	if (clock_polarity_delay) {
+		k_busy_wait(CLOCK_POLARITY_CHANGE_DELAY);
+	}
+
 	return 0;
 }