drivers: i3c: add it51xxx i3cm driver

Add it51xxx i3c controller driver.

Tested with: it51xxx evb board with st_lps22df sensor

Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>

drivers/i3c/CMakeLists.txt

@@ -56,6 +56,11 @@ zephyr_library_sources_ifdef(
   i3c_dw.c
 )
 
+zephyr_library_sources_ifdef(
+  CONFIG_I3CM_IT51XXX
+  i3cm_it51xxx.c
+)
+
 zephyr_library_sources_ifdef(
   CONFIG_I3CS_IT51XXX
   i3cs_it51xxx.c

drivers/i3c/Kconfig.it51xxx

@@ -5,6 +5,31 @@ module = I3C_IT51XXX
 module-str = i3c-it51xxx
 source "subsys/logging/Kconfig.template.log_config"
 
+config I3CM_IT51XXX
+	bool "it51xxx i3cm driver"
+	depends on DT_HAS_ITE_IT51XXX_I3CM_ENABLED
+	select PINCTRL
+	select I3C_IBI_WORKQUEUE if I3C_USE_IBI
+	select SOC_IT51XXX_CPU_IDLE_GATING
+	default y
+	help
+	  Enable it51xxx i3c controller driver.
+
+if I3CM_IT51XXX
+
+config I3CM_IT51XXX_TRANSFER_TIMEOUT_MS
+	int "Set the transfer timeout in milliseconds"
+	default 1000
+
+config I3CM_IT51XXX_DLM_SIZE
+	int "it51xxx i3cm dlm data size"
+	depends on I3CM_IT51XXX
+	default 256
+	help
+	  Set i3cm data-local-memory(DLM) size.
+
+endif # I3CM_IT51XXX
+
 config I3CS_IT51XXX
 	bool "it51xxx i3cs driver"
 	depends on DT_HAS_ITE_IT51XXX_I3CS_ENABLED

dts/bindings/i3c/ite,it51xxx-i3cm.yaml

@@ -0,0 +1,78 @@
+# Copyright (c) 2025 ITE Corporation. All Rights Reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+description: IT51XXX I3CM controller
+
+compatible: "ite,it51xxx-i3cm"
+
+include: [i3c-controller.yaml, pinctrl-device.yaml]
+
+properties:
+  reg:
+    required: true
+
+  interrupts:
+    required: true
+
+  io-channel:
+    required: true
+    type: int
+    enum: [0, 1, 2, 3]
+    description: |
+      The it51xxx chip features four i3c io channels and two i3c cotroller
+      (i3cm) engines. This property allows the i3cm engine to select the
+      desired i3c io channel. To ensure proper i3c functionality, make sure
+      that multiple controllers (including the i3cm controller and i3cs
+      target engines) are not assigned the same io channel.
+
+  i3c-pp-duty-cycle:
+    default: 50
+    type: int
+    description: |
+      The duty cycle of push-pull frequency(unit in percentage).
+
+  i3c-od-scl-hz:
+    required: true
+    type: int
+    description: |
+      The open-drain frequency for the i3c controller.
+
+  i3c-scl-hddat:
+    type: int
+    description: |
+      i3c data hold time(0 by default). The time is calculated as:
+      t_hddat = (i3c-scl-hddat + 1) * 20.8ns. The range of i3c-scl-hddat is
+      [63:0].
+
+  i3c-scl-tcas:
+    type: int
+    description: |
+      i3c clock after start condition(1 by default). The time is calculated as:
+      t_cas = (i3c-scl-tcas + 1) * 20.8ns. The maximum value is 255.
+
+  i3c-scl-tcbs:
+    type: int
+    description: |
+      i3c clock before stop condition(0 by default). The time is calculated as:
+      t_cbs = (i3c-scl-tcbs + 1) * 20.8ns. The maximum value is 255.
+
+  i3c-scl-tcasr:
+    type: int
+    description: |
+      i3c clock after repeated start condition(1 by default). The time is
+      calculated as: t_casr = (i3c-scl-tcasr + 1) * 20.8ns. The maximum value
+      is 255.
+
+  i3c-scl-tcbsr:
+    type: int
+    description: |
+      i3c clock before repeated start condition(0 by default). The time is
+      calculated as: t_cbsr = (i3c-scl-tcbsr + 1) * 20.8ns. The maximum value
+      is 255.
+
+  i2c-scl-hddat:
+    type: int
+    description: |
+      i2c data hold time(0 by default). The time is calculated as:
+      t_hddat = (i2c-scl-hddat + 1) * 20.8ns. The range of i3c-scl-hddat is
+      [65535:0].

dts/riscv/ite/it51xxx.dtsi

@@ -1204,6 +1204,28 @@
 			status = "disabled";
 		};
 
+		i3c0: i3c@f03c00 {
+			compatible = "ite,it51xxx-i3cm";
+			reg = <0x00f03c00 0x0053>;
+			status = "disabled";
+			interrupts = <IT51XXX_IRQ_I3C_M0 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-parent = <&intc>;
+			#address-cells = <3>;
+			#size-cells = <0>;
+			io-channel = <0>;
+		};
+
+		i3c1: i3c@f03c80 {
+			compatible = "ite,it51xxx-i3cm";
+			reg = <0x00f03c80 0x0053>;
+			status = "disabled";
+			interrupts = <IT51XXX_IRQ_I3C_M1 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-parent = <&intc>;
+			#address-cells = <3>;
+			#size-cells = <0>;
+			io-channel = <1>;
+		};
+
 		i3c2: i3c@f03d00 {
 			compatible = "ite,it51xxx-i3cs";
 			reg = <0x00f03d00 0x007a>;