@ -7,6 +7,7 @@
@@ -7,6 +7,7 @@
# define DT_DRV_COMPAT raspberrypi_pico_watchdog
# include <hardware/watchdog.h>
# include <hardware/ticks.h>
# include <hardware/structs/psm.h>
# include <zephyr/drivers/clock_control.h>
# include <zephyr/drivers/watchdog.h>
@ -15,9 +16,13 @@
@@ -15,9 +16,13 @@
# include <zephyr/logging/log.h>
LOG_MODULE_REGISTER ( wdt_rpi_pico , CONFIG_WDT_LOG_LEVEL ) ;
# ifdef CONFIG_SOC_RP2040
/* Maximum watchdog time is halved due to errata RP2040-E1 */
# define RPI_PICO_MAX_WDT_TIME (0xffffff / 2)
# define RPI_PICO_WDT_TIME_MULTIPLICATION_FACTOR 2
# else
# define RPI_PICO_WDT_TIME_MULTIPLICATION_FACTOR 1
# endif
# define RPI_PICO_MAX_WDT_TIME (0xffffff / RPI_PICO_WDT_TIME_MULTIPLICATION_FACTOR)
/* Watchdog requires a 1MHz clock source, divided from the crystal oscillator */
# define RPI_PICO_CLK_REF_FREQ_WDT_TICK_DIVISOR 1000000
@ -89,8 +94,13 @@ static int wdt_rpi_pico_setup(const struct device *dev, uint8_t options)
@@ -89,8 +94,13 @@ static int wdt_rpi_pico_setup(const struct device *dev, uint8_t options)
return err ;
}
# ifdef CONFIG_SOC_RP2040
watchdog_hw - > tick = ( ref_clk / RPI_PICO_CLK_REF_FREQ_WDT_TICK_DIVISOR ) |
WATCHDOG_TICK_ENABLE_BITS ;
# else
ticks_hw - > ticks [ TICK_WATCHDOG ] . cycles = ref_clk / RPI_PICO_CLK_REF_FREQ_WDT_TICK_DIVISOR ;
ticks_hw - > ticks [ TICK_WATCHDOG ] . ctrl = TICKS_WATCHDOG_CTRL_ENABLE_BITS ;
# endif
return 0 ;
}