boards: ruiside: RA8D1 Vision Board: add support

this is another board from ruiside, tested uart,
button, led, sdram, sd card

Signed-off-by: Shan Pen <bricle031@gmail.com>

boards/ruiside/ra8d1_vision_board/Kconfig.defconfig

@@ -0,0 +1,13 @@
+# Copyright (c) 2025 Shan Pen <bricle031@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_RA8D1_VISION_BOARD
+
+if DISK_DRIVER_SDMMC
+
+config SD_CMD_TIMEOUT
+	default 1000
+
+endif # DISK_DRIVER_SDMMC
+
+endif # BOARD_RA8D1_VISION_BOARD

boards/ruiside/ra8d1_vision_board/Kconfig.ra8d1_vision_board

@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Shan Pen <bricle031@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_RA8D1_VISION_BOARD
+	select SOC_R7FA8D1BHECBD

boards/ruiside/ra8d1_vision_board/board.cmake

@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: Apache-2.0
+
+# keep first
+board_runner_args(pyocd "--target=R7FA8D1BH")
+
+# keep first
+include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)

boards/ruiside/ra8d1_vision_board/board.yml

@@ -0,0 +1,6 @@
+board:
+  name: ra8d1_vision_board
+  full_name: RA8D1 Vision Board
+  vendor: ruiside
+  socs:
+    - name: r7fa8d1bhecbd

boards/ruiside/ra8d1_vision_board/doc/index.rst

@@ -0,0 +1,96 @@
+.. zephyr:board:: ra8d1_vision_board
+
+Overview
+********
+
+The RA8D1-VISION-BOARD, based on the Renesas Cortex-M85 architecture RA8D1 chip, offers
+engineers a flexible and comprehensive development platform, empowering them to explore the realm of
+machine vision more deeply.
+
+Key Features
+
+- Arm Cortex-M85
+- 480MHz frequency, on-chip 2Mb Flash, 1Mb SRAM
+- 32Mb-SDRAM; 8Mb-QSPI Flash
+- MIPI-DSI; RGB666; 8bit Camera
+- On-board DAP-LINK debugger with CMSIS-DAP
+- Raspberry Pi Interface
+
+More information about the board can be found at the `RA8D1-VISION-BOARD website`_.
+
+Hardware
+********
+Detailed Hardware features for the RA8D1 MCU group can be found at `RA8D1 Group User's Manual Hardware`_
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Default Zephyr Peripheral Mapping:
+----------------------------------
+
+The RA8D1-VISION-BOARD board features a On-board CMSIS-DAP debugger/programmer. Board is configured as follows:
+
+- UART9 TX/RX : P209/P208 (CMSIS-DAP Virtual Port Com)
+- LED0 : P102
+- LED1 : P106
+- LED2 : PA07
+- USER BUTTON : P907
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Applications for the ``ra8d1_vision_board`` board can be
+built, flashed, and debugged in the usual way. See
+:ref:`build_an_application` and :ref:`application_run` for more details on
+building and running.
+
+**Note:** Only support from SDK v0.16.6 in which GCC for Cortex Arm-M85 was available.
+To build for RA8D1-VISION-BOARD user need to get and install GNU Arm Embedded toolchain from https://github.com/zephyrproject-rtos/sdk-ng/releases/tag/v0.16.6
+
+Flashing
+========
+
+Program can be flashed to RA8D1-VISION-BOARD via the on-board DAP-LINK debugger.
+
+Linux users: to fix the permission issue, simply add the following udev rule for the
+CMSIS-DAP interface:
+
+.. code-block:: console
+
+   $ echo 'SUBSYSTEM=="usb", ATTR{idVendor}=="0416", ATTR{idProduct}=="7687", MODE:="666"' > /etc/udev/rules.d/50-cmsis-dap.rules
+
+To flash the program to board
+
+1. Connect to DAP-LINK via USB port to host PC
+
+2. Execute west command
+
+	.. code-block:: console
+
+		west flash
+
+Debugging
+=========
+
+You can debug an application in the usual way.  Here is an example for the
+:zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: ra8d1_vision_board
+   :maybe-skip-config:
+   :goals: debug
+
+References
+**********
+.. target-notes::
+
+.. _RA8D1-VISION-BOARD Website:
+   https://github.com/RT-Thread-Studio/sdk-bsp-ra8d1-vision-board
+
+.. _RA8D1 Group User's Manual Hardware:
+   https://www.renesas.com/us/en/document/mah/ra8d1-group-users-manual-hardware

boards/ruiside/ra8d1_vision_board/ra8d1_vision_board-pinctrl.dtsi

@@ -0,0 +1,130 @@
+/*
+ * Copyright (c) 2025 Shan Pen <bricle031@gmail.com>
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	sci9_default: sci9_default {
+		group1 {
+			/* tx */
+			psels = <RA_PSEL(RA_PSEL_SCI_9, 2, 9)>;
+			drive-strength = "medium";
+		};
+
+		group2 {
+			/* rx */
+			psels = <RA_PSEL(RA_PSEL_SCI_9, 2, 8)>;
+		};
+	};
+
+	sdram_default: sdram_default {
+		group1 {
+			/* SDRAM_DQM1 */
+			psels = <RA_PSEL(RA_PSEL_BUS, 1, 12)>,
+			/* SDRAM_CKE */
+			<RA_PSEL(RA_PSEL_BUS, 1, 13)>,
+			/* SDRAM_WE */
+			<RA_PSEL(RA_PSEL_BUS, 1, 14)>,
+			/* SDRAM_CS */
+			<RA_PSEL(RA_PSEL_BUS, 1, 15)>,
+			/* SDRAM_A0 */
+			<RA_PSEL(RA_PSEL_BUS, 3, 0)>,
+			/* SDRAM_A1 */
+			<RA_PSEL(RA_PSEL_BUS, 3, 1)>,
+			/* SDRAM_A2 */
+			<RA_PSEL(RA_PSEL_BUS, 3, 2)>,
+			/* SDRAM_A3 */
+			<RA_PSEL(RA_PSEL_BUS, 3, 3)>,
+			/* SDRAM_A4 */
+			<RA_PSEL(RA_PSEL_BUS, 3, 4)>,
+			/* SDRAM_A5 */
+			<RA_PSEL(RA_PSEL_BUS, 3, 5)>,
+			/* SDRAM_A6 */
+			<RA_PSEL(RA_PSEL_BUS, 3, 6)>,
+			/* SDRAM_A7 */
+			<RA_PSEL(RA_PSEL_BUS, 3, 7)>,
+			/* SDRAM_A8 */
+			<RA_PSEL(RA_PSEL_BUS, 3, 8)>,
+			/* SDRAM_A9 */
+			<RA_PSEL(RA_PSEL_BUS, 3, 9)>,
+			/* SDRAM_A10 */
+			<RA_PSEL(RA_PSEL_BUS, 3, 10)>,
+			/* SDRAM_A11 */
+			<RA_PSEL(RA_PSEL_BUS, 3, 11)>,
+			/* SDRAM_A12 */
+			<RA_PSEL(RA_PSEL_BUS, 3, 12)>,
+			/* SDRAM_A13 */
+			<RA_PSEL(RA_PSEL_BUS, 3, 12)>,
+			/* SDRAM_A14 */
+			<RA_PSEL(RA_PSEL_BUS, 9, 5)>,
+			/* SDRAM_A15 */
+			<RA_PSEL(RA_PSEL_BUS, 9, 6)>,
+			/* SDRAM_D0 */
+			<RA_PSEL(RA_PSEL_BUS, 6, 1)>,
+			/* SDRAM_D1 */
+			<RA_PSEL(RA_PSEL_BUS, 6, 2)>,
+			/* SDRAM_D2 */
+			<RA_PSEL(RA_PSEL_BUS, 6, 3)>,
+			/* SDRAM_D3 */
+			<RA_PSEL(RA_PSEL_BUS, 6, 4)>,
+			/* SDRAM_D4 */
+			<RA_PSEL(RA_PSEL_BUS, 6, 5)>,
+			/* SDRAM_D5 */
+			<RA_PSEL(RA_PSEL_BUS, 6, 6)>,
+			/* SDRAM_D6 */
+			<RA_PSEL(RA_PSEL_BUS, 6, 7)>,
+			/* SDRAM_D8 */
+			<RA_PSEL(RA_PSEL_BUS, 6, 9)>,
+			/* SDRAM_D9 */
+			<RA_PSEL(RA_PSEL_BUS, 6, 10)>,
+			/* SDRAM_D10 */
+			<RA_PSEL(RA_PSEL_BUS, 6, 11)>,
+			/* SDRAM_D11 */
+			<RA_PSEL(RA_PSEL_BUS, 6, 12)>,
+			/* SDRAM_D12 */
+			<RA_PSEL(RA_PSEL_BUS, 6, 13)>,
+			/* SDRAM_D13 */
+			<RA_PSEL(RA_PSEL_BUS, 6, 14)>,
+			/* SDRAM_D14 */
+			<RA_PSEL(RA_PSEL_BUS, 6, 15)>,
+			/* SDRAM_RAS */
+			<RA_PSEL(RA_PSEL_BUS, 9, 8)>,
+			/* SDRAM_CAS */
+			<RA_PSEL(RA_PSEL_BUS, 9, 9)>;
+			drive-strength = "high";
+		};
+
+		group2 {
+			/* SDRAM_SDCLK */
+			psels = <RA_PSEL(RA_PSEL_BUS, 10, 9)>;
+			drive-strength = "highspeed-high";
+		};
+
+		group3 {
+			/* SDRAM_D7 */
+			psels = <RA_PSEL(RA_PSEL_BUS, 10, 0)>,
+			/* SDRAM_D15 */
+			<RA_PSEL(RA_PSEL_BUS, 10, 8)>,
+			/* SDRAM_DQM0 */
+			<RA_PSEL(RA_PSEL_BUS, 10, 10)>;
+			drive-strength = "high";
+		};
+	};
+
+	sdhc1_default: sdhc1_default {
+		group1 {
+			psels = <RA_PSEL(RA_PSEL_SDHI, 5, 3)>, /* SDCD */
+			<RA_PSEL(RA_PSEL_SDHI, 8, 11)>, /* SDCMD */
+			<RA_PSEL(RA_PSEL_SDHI, 8, 12)>, /* SDDATA0 */
+			<RA_PSEL(RA_PSEL_SDHI, 5, 0)>, /* SDDATA1 */
+			<RA_PSEL(RA_PSEL_SDHI, 5, 1)>, /* SDDATA2 */
+			<RA_PSEL(RA_PSEL_SDHI, 5, 2)>; /* SDDATA3 */
+			drive-strength = "high";
+		};
+
+		group2 {
+			psels = <RA_PSEL(RA_PSEL_SDHI, 8, 10)>; /* SDCLK */
+			drive-strength = "highspeed-high";
+		};
+	};
+};

boards/ruiside/ra8d1_vision_board/ra8d1_vision_board.dts

@@ -0,0 +1,219 @@
+/*
+ * Copyright (c) 2025 Shan Pen <bricle031@gmail.com>
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <renesas/ra/ra8/r7fa8d1bhecbd.dtsi>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input-event-codes.h>
+#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
+#include <zephyr/dt-bindings/memory-controller/renesas,ra-sdram.h>
+#include "ra8d1_vision_board-pinctrl.dtsi"
+
+/ {
+	model = "Ruiside Electronic RA8D1-VISION-BOARD";
+	compatible = "ruiside,ra8d1-vision-board";
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+		zephyr,console = &uart9;
+		zephyr,shell-uart = &uart9;
+		zephyr,entropy = &trng;
+		zephyr,flash-controller = &flash;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led0: led0 {
+			gpios = <&ioport1 2 GPIO_ACTIVE_LOW>;
+			label = "LED0";
+		};
+
+		led1: led1 {
+			gpios = <&ioport1 6 GPIO_ACTIVE_LOW>;
+			label = "LED1";
+		};
+
+		led2: led2 {
+			gpios = <&ioporta 7 GPIO_ACTIVE_LOW>;
+			label = "LED2";
+		};
+	};
+
+	buttons {
+		compatible = "gpio-keys";
+
+		user_button: button_0 {
+			gpios = <&ioport9 7 GPIO_ACTIVE_LOW>;
+			label = "User Button";
+			zephyr,code = <INPUT_KEY_0>;
+		};
+	};
+
+	sdram1: sdram@68000000 {
+		    compatible = "zephyr,memory-region", "mmio-sram";
+		    reg = <0x68000000 DT_SIZE_M(32)>;
+		    zephyr,memory-region = "SDRAM";
+		    status = "okay";
+	};
+
+	aliases {
+		led0 = &led0;
+		sw0 = &user_button;
+		watchdog0 = &wdt;
+		sdhc0 = &sdhc1;
+	};
+};
+
+&xtal {
+	clock-frequency = <DT_FREQ_M(20)>;
+	mosel = <0>;
+	#clock-cells = <0>;
+	status = "okay";
+};
+
+&subclk {
+	status = "okay";
+};
+
+&pll {
+	status = "okay";
+
+	pllp {
+		status = "okay";
+	};
+
+	pllq {
+		div = <4>;
+		freq = <DT_FREQ_M(240)>;
+		status = "okay";
+	};
+
+	pllr {
+		status = "okay";
+	};
+};
+
+&sciclk {
+	clocks = <&pllp>;
+	div = <4>;
+	status = "okay";
+};
+
+&uclk {
+	clocks = <&pllq>;
+	div = <5>;
+	status = "okay";
+};
+
+&ioport0 {
+	status = "okay";
+};
+
+&ioport1 {
+	status = "okay";
+};
+
+&ioport4 {
+	status = "okay";
+};
+
+&ioport5 {
+	status = "okay";
+};
+
+&ioport6 {
+	status = "okay";
+};
+
+&ioport8 {
+	status = "okay";
+};
+
+&ioport9 {
+	status = "okay";
+};
+
+&ioporta {
+	status = "okay";
+};
+
+&sci9 {
+	pinctrl-0 = <&sci9_default>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	uart9: uart {
+		current-speed = <115200>;
+		status = "okay";
+	};
+};
+
+&trng {
+	status = "okay";
+};
+
+&flash1 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		storage_partition: partition@0 {
+			label = "storage";
+			reg = <0X0 DT_SIZE_K(12)>;
+		};
+	};
+};
+
+&port_irq10 {
+	interrupts = <86 12>;
+	status = "okay";
+};
+
+&sdram {
+	    pinctrl-0 = <&sdram_default>;
+	    pinctrl-names = "default";
+	    status = "okay";
+	    auto-refresh-interval = <SDRAM_AUTO_REFREDSH_INTERVEL_10CYCLES>;
+	    auto-refresh-count = <SDRAM_AUTO_REFREDSH_COUNT_8TIMES>;
+	    precharge-cycle-count = <SDRAM_AUTO_PRECHARGE_CYCLE_3CYCLES>;
+	    multiplex-addr-shift = "9-bit";
+	    edian-mode = "little-endian";
+	    continuous-access;
+	    bus-width = "16-bit";
+
+	    bank@0 {
+			reg = <0>;
+			renesas,ra-sdram-timing = <SDRAM_TRAS_4CYCLES
+			SDRAM_TRCD_2CYCLES
+			SDRAM_TRP_2CYCLES
+			SDRAM_TWR_2CYCLES
+			SDRAM_TCL_3CYCLES
+			937
+			SDRAM_TREFW_8CYCLES>;
+	    };
+};
+
+&sdhc1 {
+	pinctrl-names = "default";
+	interrupt-names = "accs", "card", "dma-req";
+	interrupts = <60 12>, <61 12>, <62 12>;
+	pinctrl-0 = <&sdhc1_default>;
+	status = "okay";
+	/delete-property/ card-detect;
+
+	sdmmc {
+		compatible = "zephyr,sdmmc-disk";
+		disk-name = "SD";
+		status = "okay";
+	};
+};
+
+&wdt {
+	status = "okay";
+};

boards/ruiside/ra8d1_vision_board/ra8d1_vision_board.yaml

@@ -0,0 +1,15 @@
+identifier: ra8d1_vision_board
+name: ra8d1 vision board
+type: mcu
+arch: arm
+ram: 1024
+flash: 2048
+toolchain:
+  - zephyr
+  - gnuarmemb
+supported:
+  - gpio
+  - uart
+  - watchdog
+  - memc
+vendor: ruiside

boards/ruiside/ra8d1_vision_board/ra8d1_vision_board_defconfig

@@ -0,0 +1,11 @@
+# Copyright (c) 2025 Shan Pen <bricle031@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+# Enable Console
+CONFIG_SERIAL=y
+CONFIG_UART_CONSOLE=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+CONFIG_CONSOLE=y

tests/drivers/memc/ram/testcase.yaml

@@ -33,7 +33,9 @@ tests:
       - memc
     depends_on: memc
     filter: dt_compat_enabled("renesas,ra-sdram")
-    platform_allow: ek_ra8d1
+    platform_allow:
+      - ek_ra8d1
+      - ra8d1_vision_board
   drivers.memc.max32_hpb:
     tags:
       - drivers