drivers/flash: Enable flash controller for it51xxx series

Enable flash controller for ITE it51xxx series.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>

drivers/flash/Kconfig.it8xxx2

@@ -7,7 +7,8 @@ config SOC_FLASH_ITE_IT8XXX2
 	bool "ITE IT8XXX2 flash driver"
 	default y
 	depends on DT_HAS_ITE_IT8XXX2_FLASH_CONTROLLER_ENABLED
-	select SOC_IT8XXX2_USE_ILM
+	select SOC_IT51XXX_USE_ILM if SOC_SERIES_IT51XXX
+	select SOC_IT8XXX2_USE_ILM if SOC_SERIES_IT8XXX2
 	select FLASH_HAS_PAGE_LAYOUT
 	select FLASH_HAS_DRIVER_ENABLED
 	select FLASH_HAS_EXPLICIT_ERASE

drivers/flash/flash_ite_it8xxx2.c

@@ -92,6 +92,7 @@ static const struct flash_parameters flash_it8xxx2_parameters = {
 
 void __soc_ram_code ramcode_reset_i_cache(void)
 {
+#ifdef CONFIG_SOC_SERIES_IT8XXX2
 	struct gctrl_ite_ec_regs *const gctrl_regs = GCTRL_ITE_EC_REGS_BASE;
 
 	/* I-Cache tag sram reset */
@@ -101,6 +102,9 @@ void __soc_ram_code ramcode_reset_i_cache(void)
 
 	gctrl_regs->GCTRL_MCCR &= ~IT8XXX2_GCTRL_ICACHE_RESET;
 	__asm__ volatile ("fence.i" ::: "memory");
+#else
+	custom_reset_instr_cache();
+#endif
 }
 
 void __soc_ram_code ramcode_flash_follow_mode(void)

dts/riscv/ite/it51xxx.dtsi

@@ -43,7 +43,7 @@
 		ranges;
 
 		flashctrl: flash-controller@f01000 {
-			compatible = "ite,it51xxx-flash-controller";
+			compatible = "ite,it8xxx2-flash-controller";
 			reg = <0x00f01000 0x100>;
 			#address-cells = <1>;
 			#size-cells = <1>;

soc/ite/ec/it51xxx/chip_chipregs.h

@@ -57,10 +57,9 @@ struct smfi_it51xxx_regs {
 	volatile uint8_t SMFI_HRAMW0AAS;
 	/* 0x5E: Host RAM Window 1 Access Allow Size */
 	volatile uint8_t SMFI_HRAMW1AAS;
-	volatile uint8_t reserved2[67];
+	volatile uint8_t reserved_5f_80[34];
-	/* 0xA2: Flash control 6 */
+	/* 0x81: Flash control 6 */
 	volatile uint8_t SMFI_FLHCTRL6R;
-	volatile uint8_t reserved3[46];
 };
 #endif /* !__ASSEMBLER__ */
 
@@ -69,6 +68,7 @@ struct smfi_it51xxx_regs {
 #define EC_INDIRECT_READ_INTERNAL_FLASH BIT(6)
 /* Enable EC-indirect page program command */
 #define IT51XXX_SMFI_MASK_ECINDPP       BIT(3)
+#define ITE_EC_SMFI_MASK_ECINDPP        IT51XXX_SMFI_MASK_ECINDPP
 /* 0x42: Scratch SRAM 0 address high byte */
 #define SCARH_ENABLE                    BIT(7)
 #define SCARH_ADDR_BIT19                BIT(3)
@@ -311,7 +311,12 @@ struct gctrl_it51xxx_regs {
 #define IT51XXX_GCTRL_SCRSIZE_4K  0x03
 
 /* Alias gpio_ite_ec_regs to gpio_it51xxx_regs for compatibility */
-#define gpio_ite_ec_regs      gpio_it51xxx_regs
+#define gpio_ite_ec_regs       gpio_it51xxx_regs
-#define GPIO_ITE_EC_REGS_BASE GPIO_IT51XXX_REGS_BASE
+#define GPIO_ITE_EC_REGS_BASE  GPIO_IT51XXX_REGS_BASE
+/* Alias smfi_ite_ec_regs to smfi_it51xxx_regs for compatibility */
+#define smfi_ite_ec_regs       smfi_it51xxx_regs
+/* Alias gctrl_ite_ec_regs to gctrl_it51xxx_regs for compatibility */
+#define gctrl_ite_ec_regs      gctrl_it51xxx_regs
+#define GCTRL_ITE_EC_REGS_BASE GCTRL_IT51XXX_REGS_BASE
 
 #endif /* CHIP_CHIPREGS_H */