drivers: clock: Enable PORT & LP Flexcomm in NXP syscon driver

1. Add support to enable PORT control clocks
2. Add support for LP Flexcomm
3. MCX family has a different Clock API for USDHC.

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>

drivers/clock_control/clock_control_mcux_syscon.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020-23, NXP
+ * Copyright 2020-2024 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -33,6 +33,28 @@ static int mcux_lpc_syscon_clock_control_on(const struct device *dev,
 	}
 #endif /* defined(CONFIG_COUNTER_NXP_MRT) */
 
+#if defined(CONFIG_PINCTRL_NXP_KINETIS)
+	switch ((uint32_t)sub_system) {
+	case MCUX_PORT0_CLK:
+		CLOCK_EnableClock(kCLOCK_Port0);
+		break;
+	case MCUX_PORT1_CLK:
+		CLOCK_EnableClock(kCLOCK_Port1);
+		break;
+	case MCUX_PORT2_CLK:
+		CLOCK_EnableClock(kCLOCK_Port2);
+		break;
+	case MCUX_PORT3_CLK:
+		CLOCK_EnableClock(kCLOCK_Port3);
+		break;
+	case MCUX_PORT4_CLK:
+		CLOCK_EnableClock(kCLOCK_Port4);
+		break;
+	default:
+		break;
+	}
+#endif /* defined(CONFIG_PINCTRL_NXP_KINETIS) */
+
 	return 0;
 }
 
@@ -109,9 +131,47 @@ static int mcux_lpc_syscon_clock_control_get_subsys_rate(
 	case MCUX_HS_SPI1_CLK:
 		*rate = CLOCK_GetFlexCommClkFreq(16);
 		break;
+#elif defined(CONFIG_NXP_LP_FLEXCOMM)
+	case MCUX_FLEXCOMM0_CLK:
+		*rate = CLOCK_GetLPFlexCommClkFreq(0);
+		break;
+	case MCUX_FLEXCOMM1_CLK:
+		*rate = CLOCK_GetLPFlexCommClkFreq(1);
+		break;
+	case MCUX_FLEXCOMM2_CLK:
+		*rate = CLOCK_GetLPFlexCommClkFreq(2);
+		break;
+	case MCUX_FLEXCOMM3_CLK:
+		*rate = CLOCK_GetLPFlexCommClkFreq(3);
+		break;
+	case MCUX_FLEXCOMM4_CLK:
+		*rate = CLOCK_GetLPFlexCommClkFreq(4);
+		break;
+	case MCUX_FLEXCOMM5_CLK:
+		*rate = CLOCK_GetLPFlexCommClkFreq(5);
+		break;
+	case MCUX_FLEXCOMM6_CLK:
+		*rate = CLOCK_GetLPFlexCommClkFreq(6);
+		break;
+	case MCUX_FLEXCOMM7_CLK:
+		*rate = CLOCK_GetLPFlexCommClkFreq(7);
+		break;
+	case MCUX_FLEXCOMM8_CLK:
+		*rate = CLOCK_GetLPFlexCommClkFreq(8);
+		break;
+	case MCUX_FLEXCOMM9_CLK:
+		*rate = CLOCK_GetLPFlexCommClkFreq(9);
+		break;
+
 #endif
 
 #if (defined(FSL_FEATURE_SOC_USDHC_COUNT) && FSL_FEATURE_SOC_USDHC_COUNT)
+
+#if CONFIG_SOC_FAMILY_NXP_MCX
+	case MCUX_USDHC1_CLK:
+		*rate = CLOCK_GetUsdhcClkFreq();
+		break;
+#else
 	case MCUX_USDHC1_CLK:
 		*rate = CLOCK_GetSdioClkFreq(0);
 		break;
@@ -120,6 +180,8 @@ static int mcux_lpc_syscon_clock_control_get_subsys_rate(
 		break;
 #endif
 
+#endif
+
 #if (defined(FSL_FEATURE_SOC_SDIF_COUNT) && \
 	(FSL_FEATURE_SOC_SDIF_COUNT)) && \
 	CONFIG_MCUX_SDIF

include/zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h

@@ -1,5 +1,5 @@
 /*
- * Copyright 2020-2023, NXP
+ * Copyright 2020-2024 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -59,4 +59,11 @@
 
 #define MCUX_MRT_CLK			40
 
+#define MCUX_PORT0_CLK			41
+#define MCUX_PORT1_CLK			42
+#define MCUX_PORT2_CLK			43
+#define MCUX_PORT3_CLK			44
+#define MCUX_PORT4_CLK			45
+#define MCUX_PORT5_CLK			46
+
 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_MCUX_LPC_SYSCON_H_ */