soc: renesas: rz: Update Renesas RZ/V2N, RZ/V2L according to RZ/V2H

Porting gp_renesas_isr_context variable used in FSP interrupt source
to unify with RZ/V2H and prevent build error since they share the same
hal_renesas source code.

Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>

soc/renesas/rz/rzv2l/soc.c

@@ -14,6 +14,7 @@
 
 /* System core clock is set to 200 MHz after reset */
 uint32_t SystemCoreClock = 200000000;
+void *gp_renesas_isr_context[BSP_ICU_VECTOR_MAX_ENTRIES];
 
 void soc_early_init_hook(void)
 {

soc/renesas/rz/rzv2n/soc.c

@@ -14,6 +14,7 @@
 
 /* System core clock is set to 200 MHz after reset */
 uint32_t SystemCoreClock = 200000000;
+void *gp_renesas_isr_context[BSP_ICU_VECTOR_MAX_ENTRIES];
 
 void soc_early_init_hook(void)
 {