drivers: intc: update to use multi-level API

Update these multi-level interrupt drivers to use the new API.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>

arch/common/Kconfig

@@ -23,6 +23,10 @@ config LEGACY_MULTI_LEVEL_TABLE_GENERATION
 	depends on MULTI_LEVEL_INTERRUPTS
 	depends on !PLIC
 	depends on !NXP_IRQSTEER
+	depends on !RV32M1_INTMUX
+	depends on !CAVS_ICTL
+	depends on !DW_ICTL_ACE
+	depends on !DW_ICTL
 	help
 	  A make-shift Kconfig to continue generating the multi-level interrupt LUT
 	  with the legacy way using DT macros.

drivers/interrupt_controller/intc_cavs.c

@@ -8,9 +8,11 @@
 
 #include <zephyr/arch/cpu.h>
 #include <zephyr/device.h>
+#include <zephyr/devicetree/interrupt_controller.h>
 #include <zephyr/irq.h>
 #include <zephyr/irq_nextlevel.h>
 #include <zephyr/arch/arch_interface.h>
+#include <zephyr/sw_isr_table.h>
 #include "intc_cavs.h"
 
 #if defined(CONFIG_SMP) && (CONFIG_MP_MAX_NUM_CPUS > 1)
@@ -150,6 +152,10 @@ static const struct irq_next_level_api cavs_apis = {
 		IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority),	\
 			    cavs_ictl_isr, DEVICE_DT_INST_GET(n),	\
 			    DT_INST_IRQ(n, sense));			\
-	}
+	}								\
+	IRQ_PARENT_ENTRY_DEFINE(					\
+		intc_cavs_##n, DEVICE_DT_INST_GET(n), DT_INST_IRQN(n),	\
+		INTC_INST_ISR_TBL_OFFSET(n),				\
+		DT_INST_INTC_GET_AGGREGATOR_LEVEL(n));
 
 DT_INST_FOREACH_STATUS_OKAY(CAVS_ICTL_INIT)

drivers/interrupt_controller/intc_dw.c

@@ -14,7 +14,9 @@
  */
 
 #include <zephyr/device.h>
+#include <zephyr/devicetree/interrupt_controller.h>
 #include <zephyr/irq_nextlevel.h>
+#include <zephyr/sw_isr_table.h>
 #include "intc_dw.h"
 #include <soc.h>
 #include <zephyr/irq.h>
@@ -156,3 +158,6 @@ static void dw_ictl_config_irq(const struct device *port)
 		    DEVICE_DT_INST_GET(0),
 		    DT_INST_IRQ(0, sense));
 }
+
+IRQ_PARENT_ENTRY_DEFINE(intc_dw, DEVICE_DT_INST_GET(0), DT_INST_IRQN(0),
+			INTC_INST_ISR_TBL_OFFSET(0), DT_INST_INTC_GET_AGGREGATOR_LEVEL(0));

drivers/interrupt_controller/intc_dw_ace.c

@@ -8,11 +8,10 @@
 
 #include <zephyr/device.h>
 #include <zephyr/devicetree.h>
+#include <zephyr/devicetree/interrupt_controller.h>
 #include <zephyr/irq_nextlevel.h>
 #include <zephyr/arch/xtensa/irq.h>
-#ifdef CONFIG_DYNAMIC_INTERRUPTS
 #include <zephyr/sw_isr_table.h>
-#endif
 #include <zephyr/drivers/interrupt_controller/dw_ace.h>
 #include <soc.h>
 #include <adsp_interrupt.h>
@@ -180,3 +179,7 @@ static const struct dw_ace_v1_ictl_driver_api dw_ictl_ace_v1x_apis = {
 DEVICE_DT_INST_DEFINE(0, dw_ace_init, NULL, NULL, NULL,
 		 PRE_KERNEL_1, CONFIG_INTC_INIT_PRIORITY,
 		 &dw_ictl_ace_v1x_apis);
+
+IRQ_PARENT_ENTRY_DEFINE(ace_intc, DEVICE_DT_INST_GET(0), DT_INST_IRQN(0),
+			INTC_BASE_ISR_TBL_OFFSET(DT_DRV_INST(0)),
+			DT_INST_INTC_GET_AGGREGATOR_LEVEL(0));

drivers/interrupt_controller/intc_rv32m1_intmux.c

@@ -23,6 +23,7 @@
  */
 
 #include <zephyr/kernel.h>
+#include <zephyr/devicetree/interrupt_controller.h>
 #include <zephyr/drivers/clock_control.h>
 #include <zephyr/init.h>
 #include <zephyr/irq.h>
@@ -218,3 +219,10 @@ static int rv32m1_intmux_init(const struct device *dev)
 DEVICE_DT_INST_DEFINE(0, &rv32m1_intmux_init, NULL, NULL,
 		    &rv32m1_intmux_cfg, PRE_KERNEL_1,
 		    CONFIG_RV32M1_INTMUX_INIT_PRIORITY, &rv32m1_intmux_apis);
+
+#define INTC_CHILD_IRQ_ENTRY_DEF(node_id)                                                          \
+	IRQ_PARENT_ENTRY_DEFINE(CONCAT(DT_DRV_COMPAT, _child_, DT_NODE_CHILD_IDX(node_id)), NULL,  \
+				DT_IRQN(node_id), INTC_CHILD_ISR_TBL_OFFSET(node_id),              \
+				DT_INTC_GET_AGGREGATOR_LEVEL(node_id));
+
+DT_INST_FOREACH_CHILD_STATUS_OKAY(0, INTC_CHILD_IRQ_ENTRY_DEF);