diff --git a/boards/seeed/xiao_esp32c6/Kconfig b/boards/seeed/xiao_esp32c6/Kconfig new file mode 100644 index 00000000000..bc76c90de06 --- /dev/null +++ b/boards/seeed/xiao_esp32c6/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Mario Paja +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 diff --git a/boards/seeed/xiao_esp32c6/Kconfig.sysbuild b/boards/seeed/xiao_esp32c6/Kconfig.sysbuild new file mode 100644 index 00000000000..543becaa4f6 --- /dev/null +++ b/boards/seeed/xiao_esp32c6/Kconfig.sysbuild @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Mario Paja +# SPDX-License-Identifier: Apache-2.0 + +choice BOOTLOADER + default BOOTLOADER_MCUBOOT +endchoice + +choice BOOT_SIGNATURE_TYPE + default BOOT_SIGNATURE_TYPE_NONE +endchoice diff --git a/boards/seeed/xiao_esp32c6/Kconfig.xiao_esp32c6 b/boards/seeed/xiao_esp32c6/Kconfig.xiao_esp32c6 new file mode 100644 index 00000000000..34fc9fe1b5e --- /dev/null +++ b/boards/seeed/xiao_esp32c6/Kconfig.xiao_esp32c6 @@ -0,0 +1,7 @@ +# XIAO ESP32C6 board configuration + +# Copyright (c) 2024 Mario Paja +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_XIAO_ESP32C6 + select SOC_ESP32_C6_WROOM_1U_N4 diff --git a/boards/seeed/xiao_esp32c6/board.cmake b/boards/seeed/xiao_esp32c6/board.cmake new file mode 100644 index 00000000000..2f04d1fe886 --- /dev/null +++ b/boards/seeed/xiao_esp32c6/board.cmake @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*") + set(OPENOCD OPENOCD-NOTFOUND) +endif() +find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH) + +include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/seeed/xiao_esp32c6/board.yml b/boards/seeed/xiao_esp32c6/board.yml new file mode 100644 index 00000000000..f7d65e65a43 --- /dev/null +++ b/boards/seeed/xiao_esp32c6/board.yml @@ -0,0 +1,6 @@ +board: + name: xiao_esp32c6 + full_name: XIAO ESP32C6 + vendor: seeed + socs: + - name: esp32c6 diff --git a/boards/seeed/xiao_esp32c6/doc/img/xiao_esp32c6.webp b/boards/seeed/xiao_esp32c6/doc/img/xiao_esp32c6.webp new file mode 100644 index 00000000000..739123ba9f5 Binary files /dev/null and b/boards/seeed/xiao_esp32c6/doc/img/xiao_esp32c6.webp differ diff --git a/boards/seeed/xiao_esp32c6/doc/img/xiao_esp32c6_pinout.webp b/boards/seeed/xiao_esp32c6/doc/img/xiao_esp32c6_pinout.webp new file mode 100644 index 00000000000..3cc7232f27c Binary files /dev/null and b/boards/seeed/xiao_esp32c6/doc/img/xiao_esp32c6_pinout.webp differ diff --git a/boards/seeed/xiao_esp32c6/doc/index.rst b/boards/seeed/xiao_esp32c6/doc/index.rst new file mode 100644 index 00000000000..123869ae84b --- /dev/null +++ b/boards/seeed/xiao_esp32c6/doc/index.rst @@ -0,0 +1,233 @@ +.. zephyr:board:: xiao_esp32c6 + +Overview +******** + +Seeed Studio XIAO ESP32C6 is powered by the highly-integrated ESP32-C6 SoC. +It consists of a high-performance (HP) 32-bit RISC-V processor, which can be clocked up to 160 MHz, +and a low-power (LP) 32-bit RISC-V processor, which can be clocked up to 20 MHz. +It has a 320KB ROM, a 512KB SRAM, and works with external flash. +This board integrates complete Wi-Fi, Bluetooth LE, Zigbee, and Thread functions. +For more information, check `Seeed Studio XIAO ESP32C6`_ . + +Hardware +******** + +This board is based on the ESP32-C6 with 4MB of flash, integrating 2.4 GHz Wi-Fi 6, +Bluetooth 5.3 (LE) and the 802.15.4 protocol. It has an USB-C port for programming +and debugging, integrated battery charging and an U.FL external antenna connector. +It is based on a standard XIAO 14 pin pinout. + +Supported Features +================== + +The Zephyr ``xiao_esp32c6`` board target supports the following hardware features: + ++------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++============+============+=====================================+ +| UART | on-chip | serial port | ++------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++------------+------------+-------------------------------------+ +| USB-JTAG | on-chip | hardware interface | ++------------+------------+-------------------------------------+ +| SPI Master | on-chip | spi | ++------------+------------+-------------------------------------+ +| Watchdog | on-chip | watchdog | ++------------+------------+-------------------------------------+ +| LEDC | on-chip | pwm | ++------------+------------+-------------------------------------+ +| SPI DMA | on-chip | spi | ++------------+------------+-------------------------------------+ +| GDMA | on-chip | dma | ++------------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++------------+------------+-------------------------------------+ +| USB-CDC | on-chip | serial | ++------------+------------+-------------------------------------+ +| Wi-Fi | on-chip | | ++------------+------------+-------------------------------------+ + +The board uses a standard XIAO pinout, the default pin mapping is the following: + +.. figure:: img/xiao_esp32c6_pinout.webp + :align: center + :alt: XIAO ESP32C6 Pinout + + XIAO ESP32C6 Pinout + +System requirements +******************* + +Prerequisites +============= + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +******************* + +Simple boot +=========== + +The board could be loaded using the single binary image, without 2nd stage bootloader. +It is the default option when building the application without additional configuration. + +.. note:: + + Simple boot does not provide any security features nor OTA updates. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be built (and flashed) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + + .. code:: cfg + + CONFIG_BOOTLOADER_MCUBOOT=y + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the EPS32 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :zephyr-app: samples/hello_world + :board: xiao_esp32c6 + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │   └── zephyr + │   ├── zephyr.elf + │   └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be built one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: xiao_esp32c6 + :goals: build + +The usual ``flash`` target will work with the ``xiao_esp32c6`` board +configuration. Here is an example for the :zephyr:code-sample:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: xiao_esp32c6 + :goals: flash + +Since the Zephyr console is by default on the ``usb_serial`` device, we use +the espressif monitor to view. + +.. code-block:: console + + $ west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! xiao_esp32c6/esp32c6 + +Debugging +********* + +As with much custom hardware, the ESP32-C6 modules require patches to +OpenOCD that are not upstreamed yet. Espressif maintains their own fork of +the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_. + +The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the +``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` +parameter when building. + +Here is an example for building the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: xiao_esp32c6 + :goals: build flash + :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= + +You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: xiao_esp32c6 + :goals: debug + +References +********** + +.. target-notes:: + +.. _`Seeed Studio XIAO ESP32C6`: https://wiki.seeedstudio.com/xiao_esp32c6_getting_started/ +.. _`ESP32-C6 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf +.. _`ESP32-C6 Technical Reference Manual`: https://espressif.com/sites/default/files/documentation/esp32-c6_technical_reference_manual_en.pdf +.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases diff --git a/boards/seeed/xiao_esp32c6/seeed_xiao_connector.dtsi b/boards/seeed/xiao_esp32c6/seeed_xiao_connector.dtsi new file mode 100644 index 00000000000..9fcac7e7b67 --- /dev/null +++ b/boards/seeed/xiao_esp32c6/seeed_xiao_connector.dtsi @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2024 Mario Paja + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + xiao_d: connector { + compatible = "seeed,xiao-gpio"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio0 0 0>, /* D0 */ + <1 0 &gpio0 1 0>, /* D1 */ + <2 0 &gpio0 2 0>, /* D2 */ + <3 0 &gpio0 21 0>, /* D3 */ + <4 0 &gpio0 22 0>, /* D4 */ + <5 0 &gpio0 23 0>, /* D5 */ + <6 0 &gpio0 16 0>, /* D6 */ + <7 0 &gpio0 17 0>, /* D7 */ + <8 0 &gpio0 19 0>, /* D8 */ + <9 0 &gpio0 20 0>, /* D9 */ + <10 0 &gpio0 18 0>; /* D10 */ + }; +}; + +xiao_spi: &spi2 {}; +xiao_serial: &uart0 {}; diff --git a/boards/seeed/xiao_esp32c6/support/openocd.cfg b/boards/seeed/xiao_esp32c6/support/openocd.cfg new file mode 100644 index 00000000000..d86a5517a4c --- /dev/null +++ b/boards/seeed/xiao_esp32c6/support/openocd.cfg @@ -0,0 +1,4 @@ +# ESP32C6 has built-in JTAG interface over USB port in pins GPIO13/GPIO12 (D-/D+). +set ESP_RTOS none + +source [find board/esp32c6-builtin.cfg] diff --git a/boards/seeed/xiao_esp32c6/xiao_esp32c6-pinctrl.dtsi b/boards/seeed/xiao_esp32c6/xiao_esp32c6-pinctrl.dtsi new file mode 100644 index 00000000000..061a21eb2c0 --- /dev/null +++ b/boards/seeed/xiao_esp32c6/xiao_esp32c6-pinctrl.dtsi @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2024 Mario Paja + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +&pinctrl { + + uart0_default: uart0_default { + group1 { + pinmux = ; + output-high; + }; + group2 { + pinmux = ; + bias-pull-up; + }; + }; + + spim2_default: spim2_default { + group1 { + pinmux = , + ; + }; + group2 { + pinmux = ; + output-low; + }; + }; +}; diff --git a/boards/seeed/xiao_esp32c6/xiao_esp32c6.dts b/boards/seeed/xiao_esp32c6/xiao_esp32c6.dts new file mode 100644 index 00000000000..0e46e01c655 --- /dev/null +++ b/boards/seeed/xiao_esp32c6/xiao_esp32c6.dts @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2024 Mario Paja + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "xiao_esp32c6-pinctrl.dtsi" +#include +#include +#include "seeed_xiao_connector.dtsi" + +/ { + model = "Seeed XIAO ESP32C6"; + compatible = "seeed,xiao-esp32c6"; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &usb_serial; + zephyr,shell-uart = &usb_serial; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; + + leds: leds { + compatible = "gpio-leds"; + yellow_led: led_0 { + gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; + label = "User LED1"; + }; + }; + + aliases { + led0 = &yellow_led; + watchdog0 = &wdt0; + }; + +}; + +&trng0 { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&usb_serial { + status = "okay"; +}; + +&spi2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim2_default>; + pinctrl-names = "default"; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; diff --git a/boards/seeed/xiao_esp32c6/xiao_esp32c6.yaml b/boards/seeed/xiao_esp32c6/xiao_esp32c6.yaml new file mode 100644 index 00000000000..c626ac54870 --- /dev/null +++ b/boards/seeed/xiao_esp32c6/xiao_esp32c6.yaml @@ -0,0 +1,19 @@ +identifier: xiao_esp32c6 +name: XIAO ESP32C6 +type: mcu +arch: riscv +toolchain: + - zephyr +supported: + - gpio + - watchdog + - uart + - dma + - spi + - entropy +testing: + ignore_tags: + - net + - bluetooth + - tracing +vendor: seeed diff --git a/boards/seeed/xiao_esp32c6/xiao_esp32c6_defconfig b/boards/seeed/xiao_esp32c6/xiao_esp32c6_defconfig new file mode 100644 index 00000000000..6539bd42e59 --- /dev/null +++ b/boards/seeed/xiao_esp32c6/xiao_esp32c6_defconfig @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_GPIO=y