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This commit adds pinctrl support for Apollo510 SoCs, and unified pinctrl bindings across apollo families. Signed-off-by: Hao Luo <hluo@ambiq.com>pull/85634/merge
Hao Luo
5 months ago
committed by
Benjamin Cabé
4 changed files with 195 additions and 1 deletions
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# Copyright (c) 2025 Ambiq Micro Inc. |
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# SPDX-License-Identifier: Apache-2.0 |
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description: | |
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The Ambiq Apollo5 pin controller is a node responsible for controlling |
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pin function selection and pin properties, such as routing a UART0 TX |
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to pin 60 and enabling the pullup resistor on that pin. |
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The node has the 'pinctrl' node label set in your SoC's devicetree, |
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so you can modify it like this: |
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&pinctrl { |
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/* your modifications go here */ |
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}; |
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All device pin configurations should be placed in child nodes of the |
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'pinctrl' node, as shown in this example: |
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/* You can put this in places like a board-pinctrl.dtsi file in |
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* your board directory, or a devicetree overlay in your application. |
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*/ |
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/* include pre-defined combinations for the SoC variant used by the board */ |
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#include <dt-bindings/pinctrl/ambiq-apollo5-pinctrl.h> |
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&pinctrl { |
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uart0_default: uart0_default { |
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group1 { |
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pinmux = <UART0TX_P60>; |
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}; |
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group2 { |
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pinmux = <UART0RX_P47>; |
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input-enable; |
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}; |
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}; |
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}; |
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The 'uart0_default' child node encodes the pin configurations for a |
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particular state of a device; in this case, the default (that is, active) |
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state. |
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As shown, pin configurations are organized in groups within each child node. |
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Each group can specify a list of pin function selections in the 'pinmux' |
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property. |
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A group can also specify shared pin properties common to all the specified |
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pins, such as the 'input-enable' property in group 2. |
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compatible: "ambiq,apollo5-pinctrl" |
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include: base.yaml |
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child-binding: |
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description: | |
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Definitions for a pinctrl state. |
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child-binding: |
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include: |
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- name: pincfg-node.yaml |
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property-allowlist: |
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- input-enable |
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- drive-push-pull |
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- drive-open-drain |
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- bias-high-impedance |
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- bias-pull-up |
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- bias-pull-down |
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properties: |
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pinmux: |
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required: true |
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type: array |
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description: | |
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An array of pins sharing the same group properties. Each |
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element of the array is an integer constructed from the |
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pin number and the alternative function of the pin. |
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drive-strength: |
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type: string |
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enum: |
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- "0.1" |
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- "0.5" |
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- "0.75" |
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- "1.0" |
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default: "0.1" |
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description: | |
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The drive strength of a pin, relative to full-driver strength. |
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The default value is 0.1, which is the reset value. |
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ambiq,pull-up-ohms: |
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type: int |
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enum: |
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- 1500 |
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- 6000 |
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- 12000 |
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- 24000 |
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- 50000 |
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- 100000 |
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default: 1500 |
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description: | |
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The pullup resistor value. The default value is 1500 ohms. |
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ambiq,nce-src: |
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type: int |
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default: 0 |
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description: | |
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IOM0CE0 = 0x0 - IOM 0 NCE 0 module |
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IOM0CE1 = 0x1 - IOM 0 NCE 1 module |
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IOM0CE2 = 0x2 - IOM 0 NCE 2 module |
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IOM0CE3 = 0x3 - IOM 0 NCE 3 module |
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IOM1CE0 = 0x4 - IOM 1 NCE 0 module |
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IOM1CE1 = 0x5 - IOM 1 NCE 1 module |
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IOM1CE2 = 0x6 - IOM 1 NCE 2 module |
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IOM1CE3 = 0x7 - IOM 1 NCE 3 module |
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IOM2CE0 = 0x8 - IOM 2 NCE 0 module |
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IOM2CE1 = 0x9 - IOM 2 NCE 1 module |
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IOM2CE2 = 0xA - IOM 2 NCE 2 module |
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IOM2CE3 = 0xB - IOM 2 NCE 3 module |
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IOM3CE0 = 0xC - IOM 3 NCE 0 module |
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IOM3CE1 = 0xD - IOM 3 NCE 1 module |
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IOM3CE2 = 0xE - IOM 3 NCE 2 module |
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IOM3CE3 = 0xF - IOM 3 NCE 3 module |
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IOM4CE0 = 0x10 - IOM 4 NCE 0 module |
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IOM4CE1 = 0x11 - IOM 4 NCE 1 module |
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IOM4CE2 = 0x12 - IOM 4 NCE 2 module |
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IOM4CE3 = 0x13 - IOM 4 NCE 3 module |
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IOM5CE0 = 0x14 - IOM 5 NCE 0 module |
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IOM5CE1 = 0x15 - IOM 5 NCE 1 module |
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IOM5CE2 = 0x16 - IOM 5 NCE 2 module |
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IOM5CE3 = 0x17 - IOM 5 NCE 3 module |
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IOM6CE0 = 0x18 - IOM 6 NCE 0 module |
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IOM6CE1 = 0x19 - IOM 6 NCE 1 module |
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IOM6CE2 = 0x1A - IOM 6 NCE 2 module |
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IOM6CE3 = 0x1B - IOM 6 NCE 3 module |
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IOM7CE0 = 0x1C - IOM 7 NCE 0 module |
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IOM7CE1 = 0x1D - IOM 7 NCE 1 module |
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IOM7CE2 = 0x1E - IOM 7 NCE 2 module |
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IOM7CE3 = 0x1F - IOM 7 NCE 3 module |
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DC_DPI_DE = 0x30 - DC DPI DE module |
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DISP_CONT_CSX = 0x31 - DISP CONT CSX module |
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DC_SPI_CS_N = 0x32 - DC SPI CS_N module |
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DC_QSPI_CS_N = 0x33 - DC QSPI CS_N module |
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DC_RESX = 0x34 - DC module RESX |
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ambiq,nce-pol: |
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type: int |
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default: 0 |
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description: | |
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Polarity select for NCE |
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LOW = 0x0 - Polarity is active low |
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HIGH = 0x1 - Polarity is active high |
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ambiq,sdif-cdwp: |
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type: int |
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default: 0 |
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description: | |
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Configure SD Card Detection and Write Protection pin |
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0x0 - Not SDIF pin |
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0x1 - SDIF0CD |
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0x2 - SDIF0WP |
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0x3 - SDIF1CD |
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0x4 - SDIF1WP |
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@ -0,0 +1,20 @@
@@ -0,0 +1,20 @@
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/*
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* Copyright (c) 2025 Ambiq Micro Inc. |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#ifndef __APOLLO5_PINCTRL_H__ |
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#define __APOLLO5_PINCTRL_H__ |
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#define APOLLO5_ALT_FUNC_POS 0 |
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#define APOLLO5_ALT_FUNC_MASK 0xf |
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#define APOLLO5_PIN_NUM_POS 4 |
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#define APOLLO5_PIN_NUM_MASK 0xff |
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#define APOLLO5_PINMUX(pin_num, alt_func) \ |
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(pin_num << APOLLO5_PIN_NUM_POS | \ |
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alt_func << APOLLO5_ALT_FUNC_POS) |
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#endif /* __APOLLO5_PINCTRL_H__ */ |
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