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xtensa: rename z_xtensa_irq to simple xtensa_irq 

This gets rid of the z_ prefix.

Note that z_xt_*() are being used by the HAL so they cannot be
renamed.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
pull/67429/head
Daniel Leung 2 years ago committed by Carles Cufí
parent
8bf20ee975
commit
6d5e0c25a6
8 changed files with 51 additions and 26 deletions
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  1. 3
      arch/xtensa/core/gdbstub.c
  2. 2
      arch/xtensa/core/irq_manage.c
  3. 8
      drivers/interrupt_controller/intc_dw_ace.c
  4. 8
      drivers/interrupt_controller/intc_nxp_irqsteer.c
  5. 38
      include/zephyr/arch/xtensa/irq.h
  6. 2
      soc/xtensa/intel_adsp/ace/multiprocessing.c
  7. 10
      soc/xtensa/intel_adsp/cavs/irq.c
  8. 6
      soc/xtensa/nxp_adsp/common/soc.c

3
arch/xtensa/core/gdbstub.c
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@ -972,8 +972,7 @@ void arch_gdb_init(void)
* after level-1 interrupts is for level-2 interrupt. * after level-1 interrupts is for level-2 interrupt.
* So need to do an offset by subtraction. * So need to do an offset by subtraction.
*/ */
z_xtensa_irq_enable(XCHAL_NUM_EXTINTERRUPTS + xtensa_irq_enable(XCHAL_NUM_EXTINTERRUPTS + XCHAL_DEBUGLEVEL - 2);
XCHAL_DEBUGLEVEL - 2);
/* /*
* Break and go into the GDB stub. * Break and go into the GDB stub.

2
arch/xtensa/core/irq_manage.c
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@ -75,7 +75,7 @@ void z_irq_spurious(const void *arg)
z_xtensa_fatal_error(K_ERR_SPURIOUS_IRQ, NULL); z_xtensa_fatal_error(K_ERR_SPURIOUS_IRQ, NULL);
} }
int z_xtensa_irq_is_enabled(unsigned int irq) int xtensa_irq_is_enabled(unsigned int irq)
{ {
uint32_t ie; uint32_t ie;

8
drivers/interrupt_controller/intc_dw_ace.c
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@ -92,7 +92,7 @@ void dw_ace_irq_enable(const struct device *dev, uint32_t irq)
ACE_INTC[i].irq_intmask_l &= ~BIT(ACE_IRQ_FROM_ZEPHYR(irq)); ACE_INTC[i].irq_intmask_l &= ~BIT(ACE_IRQ_FROM_ZEPHYR(irq));
} }
} else if ((irq & ~XTENSA_IRQ_NUM_MASK) == 0U) { } else if ((irq & ~XTENSA_IRQ_NUM_MASK) == 0U) {
z_xtensa_irq_enable(XTENSA_IRQ_NUMBER(irq)); xtensa_irq_enable(XTENSA_IRQ_NUMBER(irq));
} }
} }
@ -108,7 +108,7 @@ void dw_ace_irq_disable(const struct device *dev, uint32_t irq)
ACE_INTC[i].irq_intmask_l |= BIT(ACE_IRQ_FROM_ZEPHYR(irq)); ACE_INTC[i].irq_intmask_l |= BIT(ACE_IRQ_FROM_ZEPHYR(irq));
} }
} else if ((irq & ~XTENSA_IRQ_NUM_MASK) == 0U) { } else if ((irq & ~XTENSA_IRQ_NUM_MASK) == 0U) {
z_xtensa_irq_disable(XTENSA_IRQ_NUMBER(irq)); xtensa_irq_disable(XTENSA_IRQ_NUMBER(irq));
} }
} }
@ -119,7 +119,7 @@ int dw_ace_irq_is_enabled(const struct device *dev, unsigned int irq)
if (is_dw_irq(irq)) { if (is_dw_irq(irq)) {
return ACE_INTC[0].irq_inten_l & BIT(ACE_IRQ_FROM_ZEPHYR(irq)); return ACE_INTC[0].irq_inten_l & BIT(ACE_IRQ_FROM_ZEPHYR(irq));
} else if ((irq & ~XTENSA_IRQ_NUM_MASK) == 0U) { } else if ((irq & ~XTENSA_IRQ_NUM_MASK) == 0U) {
return z_xtensa_irq_is_enabled(XTENSA_IRQ_NUMBER(irq)); return xtensa_irq_is_enabled(XTENSA_IRQ_NUMBER(irq));
} }
return false; return false;
@ -161,7 +161,7 @@ static int dw_ace_init(const struct device *dev)
ARG_UNUSED(dev); ARG_UNUSED(dev);
IRQ_CONNECT(ACE_INTC_IRQ, 0, dwint_isr, 0, 0); IRQ_CONNECT(ACE_INTC_IRQ, 0, dwint_isr, 0, 0);
z_xtensa_irq_enable(ACE_INTC_IRQ); xtensa_irq_enable(ACE_INTC_IRQ);
return 0; return 0;
} }

8
drivers/interrupt_controller/intc_nxp_irqsteer.c
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@ -324,9 +324,9 @@ void z_soc_irq_enable_disable(uint32_t irq, bool enable)
if (irq_get_level(irq) == 1) { if (irq_get_level(irq) == 1) {
/* LEVEL 1 interrupts are DSP direct */ /* LEVEL 1 interrupts are DSP direct */
if (enable) { if (enable) {
z_xtensa_irq_enable(XTENSA_IRQ_NUMBER(irq)); xtensa_irq_enable(XTENSA_IRQ_NUMBER(irq));
} else { } else {
z_xtensa_irq_disable(XTENSA_IRQ_NUMBER(irq)); xtensa_irq_disable(XTENSA_IRQ_NUMBER(irq));
} }
return; return;
} }
@ -375,7 +375,7 @@ int z_soc_irq_is_enabled(unsigned int irq)
if (irq_get_level(irq) == 1) { if (irq_get_level(irq) == 1) {
/* LEVEL 1 interrupts are DSP direct */ /* LEVEL 1 interrupts are DSP direct */
return z_xtensa_irq_is_enabled(XTENSA_IRQ_NUMBER(irq)); return xtensa_irq_is_enabled(XTENSA_IRQ_NUMBER(irq));
} }
parent_irq = irq_parent_level_2(irq); parent_irq = irq_parent_level_2(irq);
@ -449,7 +449,7 @@ static void irqsteer_enable_dispatchers(const struct device *dev)
IRQSTEER_EnableMasterInterrupt(UINT_TO_IRQSTEER(cfg->regmap_phys), IRQSTEER_EnableMasterInterrupt(UINT_TO_IRQSTEER(cfg->regmap_phys),
dispatcher->irq); dispatcher->irq);
z_xtensa_irq_enable(XTENSA_IRQ_NUMBER(dispatcher->irq)); xtensa_irq_enable(XTENSA_IRQ_NUMBER(dispatcher->irq));
} }
} }

38
include/zephyr/arch/xtensa/irq.h
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@ -13,6 +13,10 @@
#define CONFIG_GEN_IRQ_START_VECTOR 0 #define CONFIG_GEN_IRQ_START_VECTOR 0
/**
* @cond INTERNAL_HIDDEN
*/
/* /*
* Call this function to enable the specified interrupts. * Call this function to enable the specified interrupts.
* *
@ -42,6 +46,7 @@ static inline void z_xt_ints_off(unsigned int mask)
__asm__ volatile("wsr.intenable %0; rsync" : : "r"(val)); __asm__ volatile("wsr.intenable %0; rsync" : : "r"(val));
} }
/* /*
* Call this function to set the specified (s/w) interrupt. * Call this function to set the specified (s/w) interrupt.
*/ */
@ -54,6 +59,10 @@ static inline void z_xt_set_intset(unsigned int arg)
#endif #endif
} }
/**
* INTERNAL_HIDDEN @endcond
*/
#ifdef CONFIG_MULTI_LEVEL_INTERRUPTS #ifdef CONFIG_MULTI_LEVEL_INTERRUPTS
/* for _soc_irq_*() */ /* for _soc_irq_*() */
@ -94,19 +103,29 @@ extern int z_soc_irq_connect_dynamic(unsigned int irq, unsigned int priority,
#define CONFIG_NUM_IRQS XCHAL_NUM_INTERRUPTS #define CONFIG_NUM_IRQS XCHAL_NUM_INTERRUPTS
#define arch_irq_enable(irq) z_xtensa_irq_enable(irq) #define arch_irq_enable(irq) xtensa_irq_enable(irq)
#define arch_irq_disable(irq) z_xtensa_irq_disable(irq) #define arch_irq_disable(irq) xtensa_irq_disable(irq)
#define arch_irq_is_enabled(irq) z_xtensa_irq_is_enabled(irq) #define arch_irq_is_enabled(irq) xtensa_irq_is_enabled(irq)
#endif #endif
static ALWAYS_INLINE void z_xtensa_irq_enable(uint32_t irq) /**
* @brief Enable interrupt on Xtensa core.
*
* @param irq Interrupt to be enabled.
*/
static ALWAYS_INLINE void xtensa_irq_enable(uint32_t irq)
{ {
z_xt_ints_on(1 << irq); z_xt_ints_on(1 << irq);
} }
static ALWAYS_INLINE void z_xtensa_irq_disable(uint32_t irq) /**
* @brief Disable interrupt on Xtensa core.
*
* @param irq Interrupt to be disabled.
*/
static ALWAYS_INLINE void xtensa_irq_disable(uint32_t irq)
{ {
z_xt_ints_off(1 << irq); z_xt_ints_off(1 << irq);
} }
@ -131,7 +150,14 @@ static ALWAYS_INLINE bool arch_irq_unlocked(unsigned int key)
return (key & 0xf) == 0; /* INTLEVEL field */ return (key & 0xf) == 0; /* INTLEVEL field */
} }
extern int z_xtensa_irq_is_enabled(unsigned int irq); /**
* @brief Query if an interrupt is enabled on Xtensa core.
*
* @param irq Interrupt to be queried.
*
* @return True if interrupt is enabled, false otherwise.
*/
extern int xtensa_irq_is_enabled(unsigned int irq);
#include <zephyr/irq.h> #include <zephyr/irq.h>

2
soc/xtensa/intel_adsp/ace/multiprocessing.c
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@ -159,7 +159,7 @@ void soc_start_core(int cpu_num)
void soc_mp_startup(uint32_t cpu) void soc_mp_startup(uint32_t cpu)
{ {
/* Must have this enabled always */ /* Must have this enabled always */
z_xtensa_irq_enable(ACE_INTC_IRQ); xtensa_irq_enable(ACE_INTC_IRQ);
#if CONFIG_ADSP_IDLE_CLOCK_GATING #if CONFIG_ADSP_IDLE_CLOCK_GATING
/* Disable idle power gating */ /* Disable idle power gating */

10
soc/xtensa/intel_adsp/cavs/irq.c
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@ -42,7 +42,7 @@ void z_soc_irq_enable(uint32_t irq)
break; break;
default: default:
/* regular interrupt */ /* regular interrupt */
z_xtensa_irq_enable(XTENSA_IRQ_NUMBER(irq)); xtensa_irq_enable(XTENSA_IRQ_NUMBER(irq));
return; return;
} }
@ -55,7 +55,7 @@ void z_soc_irq_enable(uint32_t irq)
* The specified interrupt is in CAVS interrupt controller. * The specified interrupt is in CAVS interrupt controller.
* So enable core interrupt first. * So enable core interrupt first.
*/ */
z_xtensa_irq_enable(XTENSA_IRQ_NUMBER(irq)); xtensa_irq_enable(XTENSA_IRQ_NUMBER(irq));
/* Then enable the interrupt in CAVS interrupt controller */ /* Then enable the interrupt in CAVS interrupt controller */
irq_enable_next_level(dev_cavs, CAVS_IRQ_NUMBER(irq)); irq_enable_next_level(dev_cavs, CAVS_IRQ_NUMBER(irq));
@ -80,7 +80,7 @@ void z_soc_irq_disable(uint32_t irq)
break; break;
default: default:
/* regular interrupt */ /* regular interrupt */
z_xtensa_irq_disable(XTENSA_IRQ_NUMBER(irq)); xtensa_irq_disable(XTENSA_IRQ_NUMBER(irq));
return; return;
} }
@ -97,7 +97,7 @@ void z_soc_irq_disable(uint32_t irq)
/* Then disable the parent IRQ if all children are disabled */ /* Then disable the parent IRQ if all children are disabled */
if (!irq_is_enabled_next_level(dev_cavs)) { if (!irq_is_enabled_next_level(dev_cavs)) {
z_xtensa_irq_disable(XTENSA_IRQ_NUMBER(irq)); xtensa_irq_disable(XTENSA_IRQ_NUMBER(irq));
} }
} }
@ -121,7 +121,7 @@ int z_soc_irq_is_enabled(unsigned int irq)
break; break;
default: default:
/* regular interrupt */ /* regular interrupt */
ret = z_xtensa_irq_is_enabled(XTENSA_IRQ_NUMBER(irq)); ret = xtensa_irq_is_enabled(XTENSA_IRQ_NUMBER(irq));
goto out; goto out;
} }

6
soc/xtensa/nxp_adsp/common/soc.c
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@ -25,7 +25,7 @@ void z_soc_irq_enable(uint32_t irq)
/* /*
* enable core interrupt * enable core interrupt
*/ */
z_xtensa_irq_enable(XTENSA_IRQ_NUMBER(irq)); xtensa_irq_enable(XTENSA_IRQ_NUMBER(irq));
} }
void z_soc_irq_disable(uint32_t irq) void z_soc_irq_disable(uint32_t irq)
@ -33,7 +33,7 @@ void z_soc_irq_disable(uint32_t irq)
/* /*
* disable the interrupt in interrupt controller * disable the interrupt in interrupt controller
*/ */
z_xtensa_irq_disable(XTENSA_IRQ_NUMBER(irq)); xtensa_irq_disable(XTENSA_IRQ_NUMBER(irq));
} }
int z_soc_irq_is_enabled(unsigned int irq) int z_soc_irq_is_enabled(unsigned int irq)
@ -41,7 +41,7 @@ int z_soc_irq_is_enabled(unsigned int irq)
int ret = 0; int ret = 0;
/* regular interrupt */ /* regular interrupt */
ret = z_xtensa_irq_is_enabled(XTENSA_IRQ_NUMBER(irq)); ret = xtensa_irq_is_enabled(XTENSA_IRQ_NUMBER(irq));
return ret; return ret;
} }

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