xtensa: rename z_xtensa_irq to simple xtensa_irq

This gets rid of the z_ prefix.

Note that z_xt_*() are being used by the HAL so they cannot be
renamed.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>

arch/xtensa/core/gdbstub.c

@@ -972,8 +972,7 @@ void arch_gdb_init(void)
 	 * after level-1 interrupts is for level-2 interrupt.
 	 * So need to do an offset by subtraction.
 	 */
-	z_xtensa_irq_enable(XCHAL_NUM_EXTINTERRUPTS +
-			    XCHAL_DEBUGLEVEL - 2);
+	xtensa_irq_enable(XCHAL_NUM_EXTINTERRUPTS + XCHAL_DEBUGLEVEL - 2);
 
 	/*
 	 * Break and go into the GDB stub.

arch/xtensa/core/irq_manage.c

@@ -75,7 +75,7 @@ void z_irq_spurious(const void *arg)
 	z_xtensa_fatal_error(K_ERR_SPURIOUS_IRQ, NULL);
 }
 
-int z_xtensa_irq_is_enabled(unsigned int irq)
+int xtensa_irq_is_enabled(unsigned int irq)
 {
 	uint32_t ie;
 

drivers/interrupt_controller/intc_dw_ace.c

@@ -92,7 +92,7 @@ void dw_ace_irq_enable(const struct device *dev, uint32_t irq)
 			ACE_INTC[i].irq_intmask_l &= ~BIT(ACE_IRQ_FROM_ZEPHYR(irq));
 		}
 	} else if ((irq & ~XTENSA_IRQ_NUM_MASK) == 0U) {
-		z_xtensa_irq_enable(XTENSA_IRQ_NUMBER(irq));
+		xtensa_irq_enable(XTENSA_IRQ_NUMBER(irq));
 	}
 }
 
@@ -108,7 +108,7 @@ void dw_ace_irq_disable(const struct device *dev, uint32_t irq)
 			ACE_INTC[i].irq_intmask_l |= BIT(ACE_IRQ_FROM_ZEPHYR(irq));
 		}
 	} else if ((irq & ~XTENSA_IRQ_NUM_MASK) == 0U) {
-		z_xtensa_irq_disable(XTENSA_IRQ_NUMBER(irq));
+		xtensa_irq_disable(XTENSA_IRQ_NUMBER(irq));
 	}
 }
 
@@ -119,7 +119,7 @@ int dw_ace_irq_is_enabled(const struct device *dev, unsigned int irq)
 	if (is_dw_irq(irq)) {
 		return ACE_INTC[0].irq_inten_l & BIT(ACE_IRQ_FROM_ZEPHYR(irq));
 	} else if ((irq & ~XTENSA_IRQ_NUM_MASK) == 0U) {
-		return z_xtensa_irq_is_enabled(XTENSA_IRQ_NUMBER(irq));
+		return xtensa_irq_is_enabled(XTENSA_IRQ_NUMBER(irq));
 	}
 
 	return false;
@@ -161,7 +161,7 @@ static int dw_ace_init(const struct device *dev)
 	ARG_UNUSED(dev);
 
 	IRQ_CONNECT(ACE_INTC_IRQ, 0, dwint_isr, 0, 0);
-	z_xtensa_irq_enable(ACE_INTC_IRQ);
+	xtensa_irq_enable(ACE_INTC_IRQ);
 
 	return 0;
 }

drivers/interrupt_controller/intc_nxp_irqsteer.c

@@ -324,9 +324,9 @@ void z_soc_irq_enable_disable(uint32_t irq, bool enable)
 	if (irq_get_level(irq) == 1) {
 		/* LEVEL 1 interrupts are DSP direct */
 		if (enable) {
-			z_xtensa_irq_enable(XTENSA_IRQ_NUMBER(irq));
+			xtensa_irq_enable(XTENSA_IRQ_NUMBER(irq));
 		} else {
-			z_xtensa_irq_disable(XTENSA_IRQ_NUMBER(irq));
+			xtensa_irq_disable(XTENSA_IRQ_NUMBER(irq));
 		}
 		return;
 	}
@@ -375,7 +375,7 @@ int z_soc_irq_is_enabled(unsigned int irq)
 
 	if (irq_get_level(irq) == 1) {
 		/* LEVEL 1 interrupts are DSP direct */
-		return z_xtensa_irq_is_enabled(XTENSA_IRQ_NUMBER(irq));
+		return xtensa_irq_is_enabled(XTENSA_IRQ_NUMBER(irq));
 	}
 
 	parent_irq = irq_parent_level_2(irq);
@@ -449,7 +449,7 @@ static void irqsteer_enable_dispatchers(const struct device *dev)
 		IRQSTEER_EnableMasterInterrupt(UINT_TO_IRQSTEER(cfg->regmap_phys),
 					       dispatcher->irq);
 
-		z_xtensa_irq_enable(XTENSA_IRQ_NUMBER(dispatcher->irq));
+		xtensa_irq_enable(XTENSA_IRQ_NUMBER(dispatcher->irq));
 	}
 }
 

include/zephyr/arch/xtensa/irq.h

@@ -13,6 +13,10 @@
 
 #define CONFIG_GEN_IRQ_START_VECTOR 0
 
+/**
+ * @cond INTERNAL_HIDDEN
+ */
+
 /*
  * Call this function to enable the specified interrupts.
  *
@@ -42,6 +46,7 @@ static inline void z_xt_ints_off(unsigned int mask)
 	__asm__ volatile("wsr.intenable %0; rsync" : : "r"(val));
 }
 
+
 /*
  * Call this function to set the specified (s/w) interrupt.
  */
@@ -54,6 +59,10 @@ static inline void z_xt_set_intset(unsigned int arg)
 #endif
 }
 
+/**
+ * INTERNAL_HIDDEN @endcond
+ */
+
 #ifdef CONFIG_MULTI_LEVEL_INTERRUPTS
 
 /* for _soc_irq_*() */
@@ -94,19 +103,29 @@ extern int z_soc_irq_connect_dynamic(unsigned int irq, unsigned int priority,
 
 #define CONFIG_NUM_IRQS XCHAL_NUM_INTERRUPTS
 
-#define arch_irq_enable(irq)	z_xtensa_irq_enable(irq)
-#define arch_irq_disable(irq)	z_xtensa_irq_disable(irq)
+#define arch_irq_enable(irq)	xtensa_irq_enable(irq)
+#define arch_irq_disable(irq)	xtensa_irq_disable(irq)
 
-#define arch_irq_is_enabled(irq)	z_xtensa_irq_is_enabled(irq)
+#define arch_irq_is_enabled(irq)	xtensa_irq_is_enabled(irq)
 
 #endif
 
-static ALWAYS_INLINE void z_xtensa_irq_enable(uint32_t irq)
+/**
+ * @brief Enable interrupt on Xtensa core.
+ *
+ * @param irq Interrupt to be enabled.
+ */
+static ALWAYS_INLINE void xtensa_irq_enable(uint32_t irq)
 {
 	z_xt_ints_on(1 << irq);
 }
 
-static ALWAYS_INLINE void z_xtensa_irq_disable(uint32_t irq)
+/**
+ * @brief Disable interrupt on Xtensa core.
+ *
+ * @param irq Interrupt to be disabled.
+ */
+static ALWAYS_INLINE void xtensa_irq_disable(uint32_t irq)
 {
 	z_xt_ints_off(1 << irq);
 }
@@ -131,7 +150,14 @@ static ALWAYS_INLINE bool arch_irq_unlocked(unsigned int key)
 	return (key & 0xf) == 0; /* INTLEVEL field */
 }
 
-extern int z_xtensa_irq_is_enabled(unsigned int irq);
+/**
+ * @brief Query if an interrupt is enabled on Xtensa core.
+ *
+ * @param irq Interrupt to be queried.
+ *
+ * @return True if interrupt is enabled, false otherwise.
+ */
+extern int xtensa_irq_is_enabled(unsigned int irq);
 
 #include <zephyr/irq.h>
 

soc/xtensa/intel_adsp/ace/multiprocessing.c

@@ -159,7 +159,7 @@ void soc_start_core(int cpu_num)
 void soc_mp_startup(uint32_t cpu)
 {
 	/* Must have this enabled always */
-	z_xtensa_irq_enable(ACE_INTC_IRQ);
+	xtensa_irq_enable(ACE_INTC_IRQ);
 
 #if CONFIG_ADSP_IDLE_CLOCK_GATING
 	/* Disable idle power gating */

soc/xtensa/intel_adsp/cavs/irq.c

@@ -42,7 +42,7 @@ void z_soc_irq_enable(uint32_t irq)
 		break;
 	default:
 		/* regular interrupt */
-		z_xtensa_irq_enable(XTENSA_IRQ_NUMBER(irq));
+		xtensa_irq_enable(XTENSA_IRQ_NUMBER(irq));
 		return;
 	}
 
@@ -55,7 +55,7 @@ void z_soc_irq_enable(uint32_t irq)
 	 * The specified interrupt is in CAVS interrupt controller.
 	 * So enable core interrupt first.
 	 */
-	z_xtensa_irq_enable(XTENSA_IRQ_NUMBER(irq));
+	xtensa_irq_enable(XTENSA_IRQ_NUMBER(irq));
 
 	/* Then enable the interrupt in CAVS interrupt controller */
 	irq_enable_next_level(dev_cavs, CAVS_IRQ_NUMBER(irq));
@@ -80,7 +80,7 @@ void z_soc_irq_disable(uint32_t irq)
 		break;
 	default:
 		/* regular interrupt */
-		z_xtensa_irq_disable(XTENSA_IRQ_NUMBER(irq));
+		xtensa_irq_disable(XTENSA_IRQ_NUMBER(irq));
 		return;
 	}
 
@@ -97,7 +97,7 @@ void z_soc_irq_disable(uint32_t irq)
 
 	/* Then disable the parent IRQ if all children are disabled */
 	if (!irq_is_enabled_next_level(dev_cavs)) {
-		z_xtensa_irq_disable(XTENSA_IRQ_NUMBER(irq));
+		xtensa_irq_disable(XTENSA_IRQ_NUMBER(irq));
 	}
 }
 
@@ -121,7 +121,7 @@ int z_soc_irq_is_enabled(unsigned int irq)
 		break;
 	default:
 		/* regular interrupt */
-		ret = z_xtensa_irq_is_enabled(XTENSA_IRQ_NUMBER(irq));
+		ret = xtensa_irq_is_enabled(XTENSA_IRQ_NUMBER(irq));
 		goto out;
 	}
 

soc/xtensa/nxp_adsp/common/soc.c

@@ -25,7 +25,7 @@ void z_soc_irq_enable(uint32_t irq)
 	/*
 	 * enable core interrupt
 	 */
-	z_xtensa_irq_enable(XTENSA_IRQ_NUMBER(irq));
+	xtensa_irq_enable(XTENSA_IRQ_NUMBER(irq));
 }
 
 void z_soc_irq_disable(uint32_t irq)
@@ -33,7 +33,7 @@ void z_soc_irq_disable(uint32_t irq)
 	/*
 	 * disable the interrupt in interrupt controller
 	 */
-	z_xtensa_irq_disable(XTENSA_IRQ_NUMBER(irq));
+	xtensa_irq_disable(XTENSA_IRQ_NUMBER(irq));
 }
 
 int z_soc_irq_is_enabled(unsigned int irq)
@@ -41,7 +41,7 @@ int z_soc_irq_is_enabled(unsigned int irq)
 	int ret = 0;
 
 	/* regular interrupt */
-	ret = z_xtensa_irq_is_enabled(XTENSA_IRQ_NUMBER(irq));
+	ret = xtensa_irq_is_enabled(XTENSA_IRQ_NUMBER(irq));
 
 	return ret;
 }