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Add PDM driver for DMIC. This driver is compatible with samples/audio/dmic application. Signed-off-by: Lewis Lee <llee@ambiq.com>pull/92244/head
Lewis Lee
2 months ago
committed by
Benjamin Cabé
12 changed files with 450 additions and 0 deletions
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# Copyright (c) 2025 Ambiq Micro Inc. |
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# SPDX-License-Identifier: Apache-2.0 |
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config AUDIO_DMIC_AMBIQ_PDM |
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bool "Ambiq PDM driver" |
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default y |
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depends on DT_HAS_AMBIQ_PDM_ENABLED |
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select AMBIQ_HAL |
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select AMBIQ_HAL_USE_PDM |
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select PINCTRL |
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help |
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Enable support for Ambiq PDM driver for Apollo 5 MCU. |
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if AUDIO_DMIC_AMBIQ_PDM |
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config PDM_AMBIQ_HANDLE_CACHE |
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bool "Turn on cache handling in PDM driver" |
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default y |
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depends on CACHE_MANAGEMENT && DCACHE |
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help |
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Disable this if cache has been handled in upper layers. |
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config PDM_AMBIQ_BUFFER_ALIGNMENT |
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int "Set the PDM DMA TCB buffer alignment" |
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default DCACHE_LINE_SIZE if DCACHE |
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help |
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PDM buffer should be 32bytes aligned when placed in cachable region. |
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endif |
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/*
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* Copyright (c) 2025 Ambiq Micro Inc. |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#include <zephyr/drivers/pinctrl.h> |
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#include <zephyr/drivers/gpio.h> |
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#include <zephyr/kernel.h> |
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#include <soc.h> |
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#include <zephyr/logging/log.h> |
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#include <zephyr/irq.h> |
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#include <zephyr/audio/dmic.h> |
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#include <zephyr/cache.h> |
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#include <zephyr/pm/device.h> |
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#include <zephyr/pm/policy.h> |
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#include <zephyr/pm/device_runtime.h> |
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#include <am_mcu_apollo.h> |
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#define DT_DRV_COMPAT ambiq_pdm |
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LOG_MODULE_REGISTER(ambiq_pdm, CONFIG_AUDIO_DMIC_LOG_LEVEL); |
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struct dmic_ambiq_pdm_data { |
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void *pdm_handler; |
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struct k_mem_slab *mem_slab; |
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void *mem_slab_buffer; |
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struct k_sem dma_done_sem; |
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int inst_idx; |
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uint32_t block_size; |
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uint32_t sample_num; |
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uint8_t frame_size_bytes; |
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am_hal_pdm_config_t pdm_cfg; |
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am_hal_pdm_transfer_t pdm_transfer; |
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bool pm_policy_state_on; |
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enum dmic_state dmic_state; |
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}; |
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struct dmic_ambiq_pdm_cfg { |
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void (*irq_config_func)(void); |
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const struct pinctrl_dev_config *pcfg; |
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}; |
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static void dmic_ambiq_pdm_pm_policy_state_lock_get(const struct device *dev) |
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{ |
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if (IS_ENABLED(CONFIG_PM)) { |
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struct dmic_ambiq_pdm_data *data = dev->data; |
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if (!data->pm_policy_state_on) { |
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data->pm_policy_state_on = true; |
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pm_policy_state_lock_get(PM_STATE_SUSPEND_TO_RAM, PM_ALL_SUBSTATES); |
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pm_device_runtime_get(dev); |
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} |
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} |
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} |
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static void dmic_ambiq_pdm_pm_policy_state_lock_put(const struct device *dev) |
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{ |
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if (IS_ENABLED(CONFIG_PM)) { |
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struct dmic_ambiq_pdm_data *data = dev->data; |
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if (data->pm_policy_state_on) { |
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data->pm_policy_state_on = false; |
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pm_device_runtime_put(dev); |
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pm_policy_state_lock_put(PM_STATE_SUSPEND_TO_RAM, PM_ALL_SUBSTATES); |
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} |
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} |
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} |
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static void dmic_ambiq_pdm_isr(const struct device *dev) |
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{ |
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uint32_t ui32Status; |
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struct dmic_ambiq_pdm_data *data = dev->data; |
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am_hal_pdm_interrupt_status_get(data->pdm_handler, &ui32Status, true); |
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am_hal_pdm_interrupt_clear(data->pdm_handler, ui32Status); |
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am_hal_pdm_interrupt_service(data->pdm_handler, ui32Status, &(data->pdm_transfer)); |
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if (ui32Status & AM_HAL_PDM_INT_DCMP) { |
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k_sem_give(&data->dma_done_sem); |
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} |
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} |
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static int dmic_ambiq_pdm_init(const struct device *dev) |
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{ |
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struct dmic_ambiq_pdm_data *data = dev->data; |
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const struct dmic_ambiq_pdm_cfg *config = dev->config; |
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int ret = 0; |
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ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); |
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if (ret < 0) { |
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LOG_ERR("Fail to config PDM pins\n"); |
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return ret; |
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} |
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am_hal_pdm_initialize(data->inst_idx, &data->pdm_handler); |
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am_hal_pdm_power_control(data->pdm_handler, AM_HAL_PDM_POWER_ON, false); |
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data->dmic_state = DMIC_STATE_INITIALIZED; |
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return 0; |
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} |
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static int dmic_ambiq_pdm_configure(const struct device *dev, struct dmic_cfg *dev_config) |
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{ |
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struct dmic_ambiq_pdm_data *data = dev->data; |
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const struct dmic_ambiq_pdm_cfg *config = dev->config; |
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struct pdm_chan_cfg *channel = &dev_config->channel; |
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struct pcm_stream_cfg *stream = &dev_config->streams[0]; |
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if (data->dmic_state == DMIC_STATE_ACTIVE) { |
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LOG_ERR("Cannot configure device while it is active"); |
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return -EBUSY; |
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} |
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if (channel->req_num_streams != 1 || channel->req_num_chan > 2 || |
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channel->req_num_chan < 1 || channel->req_chan_map_hi != channel->act_chan_map_hi) { |
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LOG_ERR("Requested configuration is not supported"); |
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return -EINVAL; |
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} |
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if ((stream->pcm_width != 16) && (stream->pcm_width != 24)) { |
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LOG_ERR("Only 16-bit or 24-bit samples are supported"); |
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return -EINVAL; |
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} |
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channel->act_num_streams = 1; |
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channel->act_chan_map_hi = 0; |
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channel->act_chan_map_lo = channel->req_chan_map_lo; |
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data->pdm_cfg.ePDMClkSpeed = AM_HAL_PDM_CLK_HFRC_24MHZ; |
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/* 1.5MHz PDM CLK OUT:
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* AM_HAL_PDM_CLK_24MHZ, AM_HAL_PDM_MCLKDIV_1, AM_HAL_PDM_PDMA_CLKO_DIV7 |
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* 15.625KHz 24bit Sampling: |
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* DecimationRate = 48 |
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*/ |
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data->pdm_cfg.eClkDivider = AM_HAL_PDM_MCLKDIV_1; |
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data->pdm_cfg.ePDMAClkOutDivder = AM_HAL_PDM_PDMA_CLKO_DIV7; |
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data->pdm_cfg.ui32DecimationRate = 48; |
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data->pdm_cfg.eStepSize = AM_HAL_PDM_GAIN_STEP_0_13DB; |
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data->pdm_cfg.bHighPassEnable = AM_HAL_PDM_HIGH_PASS_ENABLE; |
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data->pdm_cfg.ui32HighPassCutoff = 0x3; |
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data->pdm_cfg.eLeftGain = AM_HAL_PDM_GAIN_0DB; |
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data->pdm_cfg.eRightGain = AM_HAL_PDM_GAIN_0DB; |
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data->pdm_cfg.bDataPacking = 1; |
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if (channel->req_num_chan == 1) { |
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data->pdm_cfg.ePCMChannels = AM_HAL_PDM_CHANNEL_LEFT; |
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} else { |
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data->pdm_cfg.ePCMChannels = AM_HAL_PDM_CHANNEL_STEREO; |
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} |
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data->pdm_cfg.bPDMSampleDelay = AM_HAL_PDM_CLKOUT_PHSDLY_NONE; |
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data->pdm_cfg.ui32GainChangeDelay = AM_HAL_PDM_CLKOUT_DELAY_NONE; |
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data->pdm_cfg.bSoftMute = 0; |
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data->pdm_cfg.bLRSwap = 1; |
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am_hal_pdm_configure(data->pdm_handler, &data->pdm_cfg); |
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am_hal_pdm_interrupt_clear(data->pdm_handler, (AM_HAL_PDM_INT_DERR | AM_HAL_PDM_INT_DCMP | |
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AM_HAL_PDM_INT_UNDFL | AM_HAL_PDM_INT_OVF)); |
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am_hal_pdm_interrupt_enable(data->pdm_handler, (AM_HAL_PDM_INT_DERR | AM_HAL_PDM_INT_DCMP | |
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AM_HAL_PDM_INT_UNDFL | AM_HAL_PDM_INT_OVF)); |
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config->irq_config_func(); |
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data->block_size = stream->block_size; |
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if (stream->pcm_width == 16) { |
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data->frame_size_bytes = 2; |
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} else if (stream->pcm_width == 24) { |
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data->frame_size_bytes = 4; |
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} |
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data->sample_num = stream->block_size / data->frame_size_bytes; |
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data->mem_slab = stream->mem_slab; |
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data->dmic_state = DMIC_STATE_CONFIGURED; |
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/* Configure DMA and target address.*/ |
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data->pdm_transfer.ui32TotalCount = data->sample_num * sizeof(uint32_t); |
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data->pdm_transfer.ui32TargetAddrReverse = |
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data->pdm_transfer.ui32TargetAddr + data->pdm_transfer.ui32TotalCount; |
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return 0; |
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} |
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static void am_pdm_dma_trigger(const struct device *dev) |
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{ |
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struct dmic_ambiq_pdm_data *data = dev->data; |
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/* Start the data transfer. */ |
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am_hal_pdm_dma_start(data->pdm_handler, &(data->pdm_transfer)); |
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} |
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static int dmic_ambiq_pdm_trigger(const struct device *dev, enum dmic_trigger cmd) |
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{ |
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struct dmic_ambiq_pdm_data *data = dev->data; |
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switch (cmd) { |
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case DMIC_TRIGGER_PAUSE: |
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case DMIC_TRIGGER_STOP: |
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if (data->dmic_state == DMIC_STATE_ACTIVE) { |
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am_hal_pdm_disable(data->pdm_handler); |
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data->dmic_state = DMIC_STATE_PAUSED; |
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} |
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break; |
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case DMIC_TRIGGER_RELEASE: |
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case DMIC_TRIGGER_START: |
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if (data->dmic_state == DMIC_STATE_PAUSED || |
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data->dmic_state == DMIC_STATE_CONFIGURED) { |
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am_hal_pdm_enable(data->pdm_handler); |
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am_pdm_dma_trigger(dev); |
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data->dmic_state = DMIC_STATE_ACTIVE; |
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} |
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break; |
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default: |
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LOG_ERR("Invalid command: %d", cmd); |
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return -EINVAL; |
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} |
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return 0; |
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} |
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static int dmic_ambiq_pdm_read(const struct device *dev, uint8_t stream, void **buffer, |
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size_t *size, int32_t timeout) |
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{ |
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struct dmic_ambiq_pdm_data *data = dev->data; |
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int ret; |
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ARG_UNUSED(stream); |
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if (data->dmic_state != DMIC_STATE_ACTIVE) { |
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LOG_ERR("Device is not activated"); |
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return -EIO; |
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} |
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ret = k_sem_take(&data->dma_done_sem, SYS_TIMEOUT_MS(timeout)); |
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dmic_ambiq_pdm_pm_policy_state_lock_get(dev); |
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if (ret != 0) { |
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LOG_DBG("No audio data to be read %d", ret); |
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} else { |
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ret = k_mem_slab_alloc(data->mem_slab, &data->mem_slab_buffer, K_NO_WAIT); |
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uint32_t *pdm_data_buf = (uint32_t *)am_hal_pdm_dma_get_buffer(data->pdm_handler); |
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if (data->frame_size_bytes == 2) { |
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/*
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* PDM DMA is 32-bit datawidth for each sample, so we need to invalidate 2x |
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* block_size on 16 bit PCM data. |
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*/ |
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#if CONFIG_PDM_AMBIQ_HANDLE_CACHE |
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if (!buf_in_nocache((uintptr_t)pdm_data_buf, data->block_size * 2)) { |
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sys_cache_data_invd_range(pdm_data_buf, data->block_size * 2); |
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} |
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#endif /* PDM_AMBIQ_HANDLE_CACHE */ |
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uint8_t *temp1 = (uint8_t *)data->mem_slab_buffer; |
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/* Re-arrange data */ |
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for (uint32_t i = 0; i < data->sample_num; i++) { |
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temp1[2 * i] = (pdm_data_buf[i] & 0xFF00) >> 8U; |
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temp1[2 * i + 1] = (pdm_data_buf[i] & 0xFF0000) >> 16U; |
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} |
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} else if (data->frame_size_bytes == 4) { |
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#if CONFIG_PDM_AMBIQ_HANDLE_CACHE |
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if (!buf_in_nocache((uintptr_t)pdm_data_buf, data->block_size)) { |
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sys_cache_data_invd_range(pdm_data_buf, data->block_size); |
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} |
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#endif /* PDM_AMBIQ_HANDLE_CACHE */ |
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memcpy((void *)data->mem_slab_buffer, (void *)pdm_data_buf, |
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data->block_size); |
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} |
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*size = data->block_size; |
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*buffer = data->mem_slab_buffer; |
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} |
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dmic_ambiq_pdm_pm_policy_state_lock_put(dev); |
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return ret; |
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} |
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#ifdef CONFIG_PM_DEVICE |
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static int dmic_ambiq_pdm_pm_action(const struct device *dev, enum pm_device_action action) |
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{ |
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struct dmic_ambiq_pdm_data *data = dev->data; |
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uint32_t ret; |
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am_hal_sysctrl_power_state_e status; |
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switch (action) { |
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case PM_DEVICE_ACTION_RESUME: |
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status = AM_HAL_SYSCTRL_WAKE; |
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break; |
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case PM_DEVICE_ACTION_SUSPEND: |
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status = AM_HAL_SYSCTRL_DEEPSLEEP; |
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break; |
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default: |
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return -ENOTSUP; |
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} |
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ret = am_hal_pdm_power_control(data->pdm_handler, status, true); |
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if (ret != AM_HAL_STATUS_SUCCESS) { |
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LOG_ERR("am_hal_pdm_power_control failed: %d", ret); |
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return -EPERM; |
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} else { |
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return 0; |
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} |
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} |
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#endif /* CONFIG_PM_DEVICE */ |
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static const struct _dmic_ops dmic_ambiq_ops = { |
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.configure = dmic_ambiq_pdm_configure, |
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.trigger = dmic_ambiq_pdm_trigger, |
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.read = dmic_ambiq_pdm_read, |
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}; |
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#define AMBIQ_PDM_DEFINE(n) \ |
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PINCTRL_DT_INST_DEFINE(n); \ |
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static void pdm_irq_config_func_##n(void) \ |
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{ \ |
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IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), dmic_ambiq_pdm_isr, \ |
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DEVICE_DT_INST_GET(n), 0); \ |
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irq_enable(DT_INST_IRQN(n)); \ |
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} \ |
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static uint32_t pdm_dma_tcb_buf##n[DT_INST_PROP_OR(n, pdm_buffer_size, 1536)] \ |
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__attribute__((section(DT_INST_PROP_OR(n, pdm_buffer_location, ".data")))) \ |
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__aligned(CONFIG_PDM_AMBIQ_BUFFER_ALIGNMENT); \ |
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static struct dmic_ambiq_pdm_data dmic_ambiq_pdm_data##n = { \ |
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.dma_done_sem = Z_SEM_INITIALIZER(dmic_ambiq_pdm_data##n.dma_done_sem, 0, 1), \ |
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.inst_idx = n, \ |
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.block_size = 0, \ |
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.sample_num = 0, \ |
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.dmic_state = DMIC_STATE_UNINIT, \ |
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.pdm_transfer.ui32TargetAddr = (uint32_t)pdm_dma_tcb_buf##n, \ |
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}; \ |
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static const struct dmic_ambiq_pdm_cfg dmic_ambiq_pdm_cfg##n = { \ |
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.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \ |
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.irq_config_func = pdm_irq_config_func_##n, \ |
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}; \ |
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PM_DEVICE_DT_INST_DEFINE(n, dmic_ambiq_pdm_pm_action); \ |
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DEVICE_DT_INST_DEFINE(n, dmic_ambiq_pdm_init, NULL, &dmic_ambiq_pdm_data##n, \ |
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&dmic_ambiq_pdm_cfg##n, POST_KERNEL, \ |
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CONFIG_AUDIO_DMIC_INIT_PRIORITY, &dmic_ambiq_ops); |
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DT_INST_FOREACH_STATUS_OKAY(AMBIQ_PDM_DEFINE) |
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@ -0,0 +1,31 @@
@@ -0,0 +1,31 @@
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# Copyright (c) 2024 Ambiq Micro Inc. |
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# SPDX-License-Identifier: Apache-2.0 |
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description: Ambiq PDM |
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compatible: "ambiq,pdm" |
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include: ["base.yaml", "pinctrl-device.yaml"] |
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properties: |
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reg: |
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required: true |
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interrupts: |
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required: true |
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pinctrl-0: |
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required: true |
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pinctrl-names: |
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required: true |
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pdm-buffer-location: |
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type: string |
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description: | |
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Define PDM DMA buffer location section |
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pdm-buffer-size: |
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type: int |
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description: | |
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Define the PDM DMA buffer size in (4-byte) words |
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@ -0,0 +1,5 @@
@@ -0,0 +1,5 @@
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dmic_dev: &pdm0 { |
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pdm-buffer-location = "SRAM_NO_CACHE"; |
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pdm-buffer-size = <640>; |
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status = "okay"; |
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}; |
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