Browse Source
Refactor the ESP32 target SOCs together with all related boards. Most braking changes includes: - changing the CONFIG_SOC_ESP32* to refer to the actual soc line (esp32,esp32s2,esp32s3,esp32c3) - replacing CONFIG_SOC with the CONFIG_SOC_SERIES - creating CONFIG_SOC_FAMILY_ESP32 to embrace all the ESP32 across all used architectures - introducing CONFIG_SOC_PART_NUMBER_* to provide a SOC model config - introducing the 'common' folder to hide all commonly used configs and files. - updating west.yml to reflect previous changes in hal Signed-off-by: Marek Matej <marek.matej@espressif.com>pull/65396/head
Marek Matej
2 years ago
committed by
Carles Cufí
154 changed files with 1026 additions and 1623 deletions
@ -1,8 +1,10 @@
@@ -1,8 +1,10 @@
|
||||
# ESP32S2 saola board configuration |
||||
|
||||
# Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd. |
||||
# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
|
||||
config BOARD_ESP32S2_SAOLA |
||||
bool "ESP32S2 Saola Board" |
||||
depends on SOC_ESP32S2 |
||||
depends on SOC_SERIES_ESP32S2 |
||||
|
||||
choice SOC_PART_NUMBER |
||||
default SOC_ESP32S2_WROVER_N4R2 |
||||
endchoice |
||||
|
||||
@ -1,8 +1,11 @@
@@ -1,8 +1,11 @@
|
||||
# ESP32S3 DevKitM board configuration |
||||
|
||||
# Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
|
||||
# ESP32S3 DevKitM board configuration |
||||
config BOARD_ESP32S3_DEVKITM |
||||
bool "ESP32S3 DevKitM Board" |
||||
depends on SOC_ESP32S3 |
||||
depends on SOC_SERIES_ESP32S3 |
||||
|
||||
choice SOC_PART_NUMBER |
||||
default SOC_ESP32S3_MINI_N8 |
||||
endchoice |
||||
|
||||
@ -1,14 +1,12 @@
@@ -1,14 +1,12 @@
|
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
|
||||
CONFIG_XTENSA_RESET_VECTOR=n |
||||
CONFIG_BOARD_ESP32S3_DEVKITM=y |
||||
CONFIG_SOC_ESP32S3=y |
||||
CONFIG_SOC_SERIES_ESP32S3=y |
||||
|
||||
CONFIG_MAIN_STACK_SIZE=2048 |
||||
|
||||
CONFIG_CONSOLE=y |
||||
CONFIG_SERIAL=y |
||||
CONFIG_UART_CONSOLE=y |
||||
CONFIG_XTENSA_USE_CORE_CRT1=n |
||||
CONFIG_GPIO=y |
||||
CONFIG_GEN_ISR_TABLES=y |
||||
CONFIG_GEN_IRQ_VECTOR_TABLE=n |
||||
CONFIG_CLOCK_CONTROL=y |
||||
|
||||
@ -1,54 +0,0 @@
@@ -1,54 +0,0 @@
|
||||
# ESP32C3 board configuration |
||||
|
||||
# Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd. |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
|
||||
if SOC_ESP32C3 |
||||
|
||||
if BOOTLOADER_MCUBOOT |
||||
|
||||
config HAS_FLASH_LOAD_OFFSET |
||||
default y |
||||
|
||||
config MCUBOOT_GENERATE_UNSIGNED_IMAGE |
||||
default y |
||||
|
||||
config MCUBOOT_GENERATE_CONFIRMED_IMAGE |
||||
default y |
||||
|
||||
config ROM_START_OFFSET |
||||
default 0x20 |
||||
|
||||
endif |
||||
|
||||
config SOC |
||||
default "esp32c3" |
||||
|
||||
config NUM_IRQS |
||||
default 62 |
||||
|
||||
config GEN_ISR_TABLES |
||||
default y |
||||
|
||||
config GEN_SW_ISR_TABLE |
||||
default y |
||||
|
||||
config GEN_IRQ_VECTOR_TABLE |
||||
default n |
||||
|
||||
config DYNAMIC_INTERRUPTS |
||||
default y |
||||
|
||||
config ISR_STACK_SIZE |
||||
default 2048 |
||||
|
||||
config ATOMIC_OPERATIONS_C |
||||
default y |
||||
|
||||
config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE |
||||
default n |
||||
|
||||
config SYS_CLOCK_HW_CYCLES_PER_SEC |
||||
default 16000000 |
||||
|
||||
endif |
||||
@ -0,0 +1,5 @@
@@ -0,0 +1,5 @@
|
||||
# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
|
||||
add_subdirectory(${SOC_SERIES}) |
||||
add_subdirectory(common) |
||||
@ -0,0 +1,16 @@
@@ -0,0 +1,16 @@
|
||||
# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
|
||||
config SOC_FAMILY_ESP32 |
||||
bool |
||||
|
||||
if SOC_FAMILY_ESP32 |
||||
|
||||
config SOC_FAMILY |
||||
string |
||||
default "espressif_esp32" |
||||
|
||||
source "soc/riscv/espressif_esp32/common/Kconfig.soc" |
||||
source "soc/riscv/espressif_esp32/*/Kconfig.soc" |
||||
|
||||
endif # SOC_FAMILY_ESP32 |
||||
@ -0,0 +1,5 @@
@@ -0,0 +1,5 @@
|
||||
# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
|
||||
source "soc/riscv/espressif_esp32/common/Kconfig.defconfig.series" |
||||
source "soc/riscv/espressif_esp32/*/Kconfig.defconfig.series" |
||||
@ -0,0 +1,4 @@
@@ -0,0 +1,4 @@
|
||||
# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
|
||||
source "soc/riscv/espressif_esp32/*/Kconfig.series" |
||||
@ -0,0 +1,2 @@
@@ -0,0 +1,2 @@
|
||||
# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
@ -0,0 +1,52 @@
@@ -0,0 +1,52 @@
|
||||
# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
|
||||
if SOC_FAMILY_ESP32 |
||||
|
||||
config GEN_ISR_TABLES |
||||
default y |
||||
|
||||
config GEN_SW_ISR_TABLE |
||||
default y |
||||
|
||||
config GEN_IRQ_VECTOR_TABLE |
||||
default n |
||||
|
||||
config DYNAMIC_INTERRUPTS |
||||
default y |
||||
|
||||
config ISR_STACK_SIZE |
||||
default 2048 |
||||
|
||||
config ATOMIC_OPERATIONS_C |
||||
default y |
||||
|
||||
config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE |
||||
default n |
||||
|
||||
config SYS_CLOCK_HW_CYCLES_PER_SEC |
||||
default 16000000 |
||||
|
||||
config SYS_CLOCK_TICKS_PER_SEC |
||||
default 1000 |
||||
|
||||
config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE |
||||
default n |
||||
|
||||
config CLOCK_CONTROL |
||||
default y |
||||
|
||||
if BOOTLOADER_MCUBOOT |
||||
|
||||
config HAS_FLASH_LOAD_OFFSET |
||||
default y |
||||
config MCUBOOT_GENERATE_UNSIGNED_IMAGE |
||||
default y |
||||
config MCUBOOT_GENERATE_CONFIRMED_IMAGE |
||||
default y |
||||
config ROM_START_OFFSET |
||||
default 0x20 |
||||
|
||||
endif # BOOTLOADER_MCUBOOT config |
||||
|
||||
endif # SOC_FAMILY_ESP32 |
||||
@ -0,0 +1,15 @@
@@ -0,0 +1,15 @@
|
||||
# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
|
||||
if SOC_FAMILY_ESP32 |
||||
|
||||
config ESPTOOLPY_FLASHFREQ_80M |
||||
bool |
||||
|
||||
config FLASH_SIZE |
||||
int |
||||
|
||||
config FLASH_BASE_ADDRESS |
||||
hex |
||||
|
||||
endif # SOC_FAMILY_ESP32 |
||||
@ -0,0 +1,21 @@
@@ -0,0 +1,21 @@
|
||||
# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
|
||||
if SOC_SERIES_ESP32C3 |
||||
|
||||
config SOC_SERIES |
||||
default "esp32c3" |
||||
|
||||
config NUM_IRQS |
||||
default 62 |
||||
|
||||
config ESPTOOLPY_FLASHFREQ_80M |
||||
default y |
||||
|
||||
config FLASH_SIZE |
||||
default $(dt_node_reg_size_int,/soc/flash-controller@60002000/flash@0,0) |
||||
|
||||
config FLASH_BASE_ADDRESS |
||||
default $(dt_node_reg_addr_hex,/soc/flash-controller@60002000/flash@0) |
||||
|
||||
endif # SOC_SERIES_ESP32C3 |
||||
@ -0,0 +1,20 @@
@@ -0,0 +1,20 @@
|
||||
# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
|
||||
config SOC_SERIES_ESP32C3 |
||||
bool "ESP32C3" |
||||
select RISCV |
||||
select RISCV_GP |
||||
select DYNAMIC_INTERRUPTS |
||||
select CLOCK_CONTROL |
||||
select PINCTRL |
||||
select RISCV_ISA_RV32I |
||||
select RISCV_ISA_EXT_M |
||||
select RISCV_ISA_EXT_C |
||||
select RISCV_ISA_EXT_ZICSR |
||||
select HAS_ESPRESSIF_HAL |
||||
select SOC_FAMILY_ESP32 |
||||
select XIP if !MCUBOOT |
||||
select HAS_PM |
||||
help |
||||
Enable support for Espressif ESP32-C3 |
||||
@ -1,365 +0,0 @@
@@ -1,365 +0,0 @@
|
||||
/*
|
||||
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. |
||||
* |
||||
* Functions here are designed to produce efficient code to |
||||
* search an Xtensa bitmask of interrupts, inspecting only those bits |
||||
* declared to be associated with a given interrupt level. Each |
||||
* dispatcher will handle exactly one flagged interrupt, in numerical |
||||
* order (low bits first) and will return a mask of that bit that can |
||||
* then be cleared by the calling code. Unrecognized bits for the |
||||
* level will invoke an error handler. |
||||
*/ |
||||
|
||||
#include <xtensa/config/core-isa.h> |
||||
#include <zephyr/sys/util.h> |
||||
#include <zephyr/sw_isr_table.h> |
||||
|
||||
#if !defined(XCHAL_INT0_LEVEL) || XCHAL_INT0_LEVEL != 1 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
#if !defined(XCHAL_INT1_LEVEL) || XCHAL_INT1_LEVEL != 1 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
#if !defined(XCHAL_INT2_LEVEL) || XCHAL_INT2_LEVEL != 1 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
#if !defined(XCHAL_INT3_LEVEL) || XCHAL_INT3_LEVEL != 1 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
#if !defined(XCHAL_INT4_LEVEL) || XCHAL_INT4_LEVEL != 1 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
#if !defined(XCHAL_INT5_LEVEL) || XCHAL_INT5_LEVEL != 1 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
#if !defined(XCHAL_INT6_LEVEL) || XCHAL_INT6_LEVEL != 1 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
#if !defined(XCHAL_INT7_LEVEL) || XCHAL_INT7_LEVEL != 1 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
#if !defined(XCHAL_INT8_LEVEL) || XCHAL_INT8_LEVEL != 1 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
#if !defined(XCHAL_INT9_LEVEL) || XCHAL_INT9_LEVEL != 1 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
#if !defined(XCHAL_INT10_LEVEL) || XCHAL_INT10_LEVEL != 1 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
#if !defined(XCHAL_INT12_LEVEL) || XCHAL_INT12_LEVEL != 1 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
#if !defined(XCHAL_INT13_LEVEL) || XCHAL_INT13_LEVEL != 1 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
#if !defined(XCHAL_INT17_LEVEL) || XCHAL_INT17_LEVEL != 1 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
#if !defined(XCHAL_INT18_LEVEL) || XCHAL_INT18_LEVEL != 1 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
#if !defined(XCHAL_INT11_LEVEL) || XCHAL_INT11_LEVEL != 3 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
#if !defined(XCHAL_INT15_LEVEL) || XCHAL_INT15_LEVEL != 3 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
#if !defined(XCHAL_INT22_LEVEL) || XCHAL_INT22_LEVEL != 3 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
#if !defined(XCHAL_INT23_LEVEL) || XCHAL_INT23_LEVEL != 3 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
#if !defined(XCHAL_INT27_LEVEL) || XCHAL_INT27_LEVEL != 3 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
#if !defined(XCHAL_INT29_LEVEL) || XCHAL_INT29_LEVEL != 3 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
#if !defined(XCHAL_INT14_LEVEL) || XCHAL_INT14_LEVEL != 7 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
#if !defined(XCHAL_INT16_LEVEL) || XCHAL_INT16_LEVEL != 5 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
#if !defined(XCHAL_INT26_LEVEL) || XCHAL_INT26_LEVEL != 5 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
#if !defined(XCHAL_INT31_LEVEL) || XCHAL_INT31_LEVEL != 5 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
#if !defined(XCHAL_INT19_LEVEL) || XCHAL_INT19_LEVEL != 2 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
#if !defined(XCHAL_INT20_LEVEL) || XCHAL_INT20_LEVEL != 2 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
#if !defined(XCHAL_INT21_LEVEL) || XCHAL_INT21_LEVEL != 2 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
#if !defined(XCHAL_INT24_LEVEL) || XCHAL_INT24_LEVEL != 4 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
#if !defined(XCHAL_INT25_LEVEL) || XCHAL_INT25_LEVEL != 4 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
#if !defined(XCHAL_INT28_LEVEL) || XCHAL_INT28_LEVEL != 4 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
#if !defined(XCHAL_INT30_LEVEL) || XCHAL_INT30_LEVEL != 4 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
|
||||
static inline int _xtensa_handle_one_int1(unsigned int mask) |
||||
{ |
||||
int irq; |
||||
|
||||
if (mask & 0x7f) { |
||||
if (mask & 0x7) { |
||||
if (mask & BIT(0)) { |
||||
mask = BIT(0); |
||||
irq = 0; |
||||
goto handle_irq; |
||||
} |
||||
if (mask & BIT(1)) { |
||||
mask = BIT(1); |
||||
irq = 1; |
||||
goto handle_irq; |
||||
} |
||||
if (mask & BIT(2)) { |
||||
mask = BIT(2); |
||||
irq = 2; |
||||
goto handle_irq; |
||||
} |
||||
} else { |
||||
if (mask & 0x18) { |
||||
if (mask & BIT(3)) { |
||||
mask = BIT(3); |
||||
irq = 3; |
||||
goto handle_irq; |
||||
} |
||||
if (mask & BIT(4)) { |
||||
mask = BIT(4); |
||||
irq = 4; |
||||
goto handle_irq; |
||||
} |
||||
} else { |
||||
if (mask & BIT(5)) { |
||||
mask = BIT(5); |
||||
irq = 5; |
||||
goto handle_irq; |
||||
} |
||||
if (mask & BIT(6)) { |
||||
mask = BIT(6); |
||||
irq = 6; |
||||
goto handle_irq; |
||||
} |
||||
} |
||||
} |
||||
} else { |
||||
if (mask & 0x780) { |
||||
if (mask & 0x180) { |
||||
if (mask & BIT(7)) { |
||||
mask = BIT(7); |
||||
irq = 7; |
||||
goto handle_irq; |
||||
} |
||||
if (mask & BIT(8)) { |
||||
mask = BIT(8); |
||||
irq = 8; |
||||
goto handle_irq; |
||||
} |
||||
} else { |
||||
if (mask & BIT(9)) { |
||||
mask = BIT(9); |
||||
irq = 9; |
||||
goto handle_irq; |
||||
} |
||||
if (mask & BIT(10)) { |
||||
mask = BIT(10); |
||||
irq = 10; |
||||
goto handle_irq; |
||||
} |
||||
} |
||||
} else { |
||||
if (mask & 0x3000) { |
||||
if (mask & BIT(12)) { |
||||
mask = BIT(12); |
||||
irq = 12; |
||||
goto handle_irq; |
||||
} |
||||
if (mask & BIT(13)) { |
||||
mask = BIT(13); |
||||
irq = 13; |
||||
goto handle_irq; |
||||
} |
||||
} else { |
||||
if (mask & BIT(17)) { |
||||
mask = BIT(17); |
||||
irq = 17; |
||||
goto handle_irq; |
||||
} |
||||
if (mask & BIT(18)) { |
||||
mask = BIT(18); |
||||
irq = 18; |
||||
goto handle_irq; |
||||
} |
||||
} |
||||
} |
||||
} |
||||
return 0; |
||||
handle_irq: |
||||
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg); |
||||
return mask; |
||||
} |
||||
|
||||
static inline int _xtensa_handle_one_int3(unsigned int mask) |
||||
{ |
||||
int irq; |
||||
|
||||
if (mask & 0x408800) { |
||||
if (mask & BIT(11)) { |
||||
mask = BIT(11); |
||||
irq = 11; |
||||
goto handle_irq; |
||||
} |
||||
if (mask & BIT(15)) { |
||||
mask = BIT(15); |
||||
irq = 15; |
||||
goto handle_irq; |
||||
} |
||||
if (mask & BIT(22)) { |
||||
mask = BIT(22); |
||||
irq = 22; |
||||
goto handle_irq; |
||||
} |
||||
} else { |
||||
if (mask & BIT(23)) { |
||||
mask = BIT(23); |
||||
irq = 23; |
||||
goto handle_irq; |
||||
} |
||||
if (mask & BIT(27)) { |
||||
mask = BIT(27); |
||||
irq = 27; |
||||
goto handle_irq; |
||||
} |
||||
if (mask & BIT(29)) { |
||||
mask = BIT(29); |
||||
irq = 29; |
||||
goto handle_irq; |
||||
} |
||||
} |
||||
return 0; |
||||
handle_irq: |
||||
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg); |
||||
return mask; |
||||
} |
||||
|
||||
static inline int _xtensa_handle_one_int7(unsigned int mask) |
||||
{ |
||||
int irq; |
||||
|
||||
if (mask & BIT(14)) { |
||||
mask = BIT(14); |
||||
irq = 14; |
||||
goto handle_irq; |
||||
} |
||||
return 0; |
||||
handle_irq: |
||||
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg); |
||||
return mask; |
||||
} |
||||
|
||||
static inline int _xtensa_handle_one_int5(unsigned int mask) |
||||
{ |
||||
int irq; |
||||
|
||||
if (mask & BIT(16)) { |
||||
mask = BIT(16); |
||||
irq = 16; |
||||
goto handle_irq; |
||||
} |
||||
if (mask & BIT(26)) { |
||||
mask = BIT(26); |
||||
irq = 26; |
||||
goto handle_irq; |
||||
} |
||||
if (mask & BIT(31)) { |
||||
mask = BIT(31); |
||||
irq = 31; |
||||
goto handle_irq; |
||||
} |
||||
return 0; |
||||
handle_irq: |
||||
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg); |
||||
return mask; |
||||
} |
||||
|
||||
static inline int _xtensa_handle_one_int2(unsigned int mask) |
||||
{ |
||||
int irq; |
||||
|
||||
if (mask & BIT(19)) { |
||||
mask = BIT(19); |
||||
irq = 19; |
||||
goto handle_irq; |
||||
} |
||||
if (mask & BIT(20)) { |
||||
mask = BIT(20); |
||||
irq = 20; |
||||
goto handle_irq; |
||||
} |
||||
if (mask & BIT(21)) { |
||||
mask = BIT(21); |
||||
irq = 21; |
||||
goto handle_irq; |
||||
} |
||||
return 0; |
||||
handle_irq: |
||||
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg); |
||||
return mask; |
||||
} |
||||
|
||||
static inline int _xtensa_handle_one_int4(unsigned int mask) |
||||
{ |
||||
int irq; |
||||
|
||||
if (mask & 0x3000000) { |
||||
if (mask & BIT(24)) { |
||||
mask = BIT(24); |
||||
irq = 24; |
||||
goto handle_irq; |
||||
} |
||||
if (mask & BIT(25)) { |
||||
mask = BIT(25); |
||||
irq = 25; |
||||
goto handle_irq; |
||||
} |
||||
} else { |
||||
if (mask & BIT(28)) { |
||||
mask = BIT(28); |
||||
irq = 28; |
||||
goto handle_irq; |
||||
} |
||||
if (mask & BIT(30)) { |
||||
mask = BIT(30); |
||||
irq = 30; |
||||
goto handle_irq; |
||||
} |
||||
} |
||||
return 0; |
||||
handle_irq: |
||||
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg); |
||||
return mask; |
||||
} |
||||
|
||||
static inline int _xtensa_handle_one_int0(unsigned int mask) |
||||
{ |
||||
return 0; |
||||
} |
||||
static inline int _xtensa_handle_one_int6(unsigned int mask) |
||||
{ |
||||
return 0; |
||||
} |
||||
@ -1,55 +0,0 @@
@@ -1,55 +0,0 @@
|
||||
# ESP32S2 board configuration |
||||
|
||||
# Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd. |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
|
||||
if SOC_ESP32S2 |
||||
|
||||
if BOOTLOADER_MCUBOOT |
||||
|
||||
config HAS_FLASH_LOAD_OFFSET |
||||
default y |
||||
|
||||
config MCUBOOT_GENERATE_UNSIGNED_IMAGE |
||||
default y |
||||
|
||||
config MCUBOOT_GENERATE_CONFIRMED_IMAGE |
||||
default y |
||||
|
||||
config ROM_START_OFFSET |
||||
default 0x20 |
||||
|
||||
endif |
||||
|
||||
config SOC |
||||
default "esp32s2" |
||||
|
||||
config SOC_TOOLCHAIN_NAME |
||||
string |
||||
default "espressif_esp32s2" |
||||
|
||||
config GEN_ISR_TABLES |
||||
default y |
||||
|
||||
config GEN_IRQ_VECTOR_TABLE |
||||
default n |
||||
|
||||
config ISR_STACK_SIZE |
||||
default 2048 |
||||
|
||||
config HEAP_MEM_POOL_SIZE |
||||
default 32768 |
||||
|
||||
config MP_MAX_NUM_CPUS |
||||
default 1 |
||||
|
||||
config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE |
||||
default n |
||||
|
||||
config SYS_CLOCK_HW_CYCLES_PER_SEC |
||||
default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) |
||||
|
||||
config XTENSA_CCOUNT_HZ |
||||
default SYS_CLOCK_HW_CYCLES_PER_SEC |
||||
|
||||
endif |
||||
@ -1,371 +0,0 @@
@@ -1,371 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd. |
||||
* |
||||
* SPDX-License-Identifier: Apache-2.0 |
||||
*/ |
||||
|
||||
/*
|
||||
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. |
||||
* |
||||
* Functions here are designed to produce efficient code to |
||||
* search an Xtensa bitmask of interrupts, inspecting only those bits |
||||
* declared to be associated with a given interrupt level. Each |
||||
* dispatcher will handle exactly one flagged interrupt, in numerical |
||||
* order (low bits first) and will return a mask of that bit that can |
||||
* then be cleared by the calling code. Unrecognized bits for the |
||||
* level will invoke an error handler. |
||||
*/ |
||||
|
||||
#include <xtensa/config/core-isa.h> |
||||
#include <zephyr/sys/util.h> |
||||
#include <zephyr/sw_isr_table.h> |
||||
|
||||
#if !defined(XCHAL_INT0_LEVEL) || XCHAL_INT0_LEVEL != 1 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
#if !defined(XCHAL_INT1_LEVEL) || XCHAL_INT1_LEVEL != 1 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
#if !defined(XCHAL_INT2_LEVEL) || XCHAL_INT2_LEVEL != 1 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
#if !defined(XCHAL_INT3_LEVEL) || XCHAL_INT3_LEVEL != 1 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
#if !defined(XCHAL_INT4_LEVEL) || XCHAL_INT4_LEVEL != 1 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
#if !defined(XCHAL_INT5_LEVEL) || XCHAL_INT5_LEVEL != 1 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
#if !defined(XCHAL_INT6_LEVEL) || XCHAL_INT6_LEVEL != 1 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
#if !defined(XCHAL_INT7_LEVEL) || XCHAL_INT7_LEVEL != 1 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
#if !defined(XCHAL_INT8_LEVEL) || XCHAL_INT8_LEVEL != 1 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
#if !defined(XCHAL_INT9_LEVEL) || XCHAL_INT9_LEVEL != 1 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
#if !defined(XCHAL_INT10_LEVEL) || XCHAL_INT10_LEVEL != 1 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
#if !defined(XCHAL_INT12_LEVEL) || XCHAL_INT12_LEVEL != 1 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
#if !defined(XCHAL_INT13_LEVEL) || XCHAL_INT13_LEVEL != 1 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
#if !defined(XCHAL_INT17_LEVEL) || XCHAL_INT17_LEVEL != 1 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
#if !defined(XCHAL_INT18_LEVEL) || XCHAL_INT18_LEVEL != 1 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
#if !defined(XCHAL_INT11_LEVEL) || XCHAL_INT11_LEVEL != 3 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
#if !defined(XCHAL_INT15_LEVEL) || XCHAL_INT15_LEVEL != 3 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
#if !defined(XCHAL_INT22_LEVEL) || XCHAL_INT22_LEVEL != 3 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
#if !defined(XCHAL_INT23_LEVEL) || XCHAL_INT23_LEVEL != 3 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
#if !defined(XCHAL_INT27_LEVEL) || XCHAL_INT27_LEVEL != 3 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
#if !defined(XCHAL_INT29_LEVEL) || XCHAL_INT29_LEVEL != 3 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
#if !defined(XCHAL_INT14_LEVEL) || XCHAL_INT14_LEVEL != 7 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
#if !defined(XCHAL_INT16_LEVEL) || XCHAL_INT16_LEVEL != 5 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
#if !defined(XCHAL_INT26_LEVEL) || XCHAL_INT26_LEVEL != 5 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
#if !defined(XCHAL_INT31_LEVEL) || XCHAL_INT31_LEVEL != 5 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
#if !defined(XCHAL_INT19_LEVEL) || XCHAL_INT19_LEVEL != 2 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
#if !defined(XCHAL_INT20_LEVEL) || XCHAL_INT20_LEVEL != 2 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
#if !defined(XCHAL_INT21_LEVEL) || XCHAL_INT21_LEVEL != 2 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
#if !defined(XCHAL_INT24_LEVEL) || XCHAL_INT24_LEVEL != 4 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
#if !defined(XCHAL_INT25_LEVEL) || XCHAL_INT25_LEVEL != 4 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
#if !defined(XCHAL_INT28_LEVEL) || XCHAL_INT28_LEVEL != 4 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
#if !defined(XCHAL_INT30_LEVEL) || XCHAL_INT30_LEVEL != 4 |
||||
#error core-isa.h interrupt level does not match dispatcher! |
||||
#endif |
||||
|
||||
static inline int _xtensa_handle_one_int1(unsigned int mask) |
||||
{ |
||||
int irq; |
||||
|
||||
if (mask & 0x7f) { |
||||
if (mask & 0x7) { |
||||
if (mask & BIT(0)) { |
||||
mask = BIT(0); |
||||
irq = 0; |
||||
goto handle_irq; |
||||
} |
||||
if (mask & BIT(1)) { |
||||
mask = BIT(1); |
||||
irq = 1; |
||||
goto handle_irq; |
||||
} |
||||
if (mask & BIT(2)) { |
||||
mask = BIT(2); |
||||
irq = 2; |
||||
goto handle_irq; |
||||
} |
||||
} else { |
||||
if (mask & 0x18) { |
||||
if (mask & BIT(3)) { |
||||
mask = BIT(3); |
||||
irq = 3; |
||||
goto handle_irq; |
||||
} |
||||
if (mask & BIT(4)) { |
||||
mask = BIT(4); |
||||
irq = 4; |
||||
goto handle_irq; |
||||
} |
||||
} else { |
||||
if (mask & BIT(5)) { |
||||
mask = BIT(5); |
||||
irq = 5; |
||||
goto handle_irq; |
||||
} |
||||
if (mask & BIT(6)) { |
||||
mask = BIT(6); |
||||
irq = 6; |
||||
goto handle_irq; |
||||
} |
||||
} |
||||
} |
||||
} else { |
||||
if (mask & 0x780) { |
||||
if (mask & 0x180) { |
||||
if (mask & BIT(7)) { |
||||
mask = BIT(7); |
||||
irq = 7; |
||||
goto handle_irq; |
||||
} |
||||
if (mask & BIT(8)) { |
||||
mask = BIT(8); |
||||
irq = 8; |
||||
goto handle_irq; |
||||
} |
||||
} else { |
||||
if (mask & BIT(9)) { |
||||
mask = BIT(9); |
||||
irq = 9; |
||||
goto handle_irq; |
||||
} |
||||
if (mask & BIT(10)) { |
||||
mask = BIT(10); |
||||
irq = 10; |
||||
goto handle_irq; |
||||
} |
||||
} |
||||
} else { |
||||
if (mask & 0x3000) { |
||||
if (mask & BIT(12)) { |
||||
mask = BIT(12); |
||||
irq = 12; |
||||
goto handle_irq; |
||||
} |
||||
if (mask & BIT(13)) { |
||||
mask = BIT(13); |
||||
irq = 13; |
||||
goto handle_irq; |
||||
} |
||||
} else { |
||||
if (mask & BIT(17)) { |
||||
mask = BIT(17); |
||||
irq = 17; |
||||
goto handle_irq; |
||||
} |
||||
if (mask & BIT(18)) { |
||||
mask = BIT(18); |
||||
irq = 18; |
||||
goto handle_irq; |
||||
} |
||||
} |
||||
} |
||||
} |
||||
return 0; |
||||
handle_irq: |
||||
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg); |
||||
return mask; |
||||
} |
||||
|
||||
static inline int _xtensa_handle_one_int3(unsigned int mask) |
||||
{ |
||||
int irq; |
||||
|
||||
if (mask & 0x408800) { |
||||
if (mask & BIT(11)) { |
||||
mask = BIT(11); |
||||
irq = 11; |
||||
goto handle_irq; |
||||
} |
||||
if (mask & BIT(15)) { |
||||
mask = BIT(15); |
||||
irq = 15; |
||||
goto handle_irq; |
||||
} |
||||
if (mask & BIT(22)) { |
||||
mask = BIT(22); |
||||
irq = 22; |
||||
goto handle_irq; |
||||
} |
||||
} else { |
||||
if (mask & BIT(23)) { |
||||
mask = BIT(23); |
||||
irq = 23; |
||||
goto handle_irq; |
||||
} |
||||
if (mask & BIT(27)) { |
||||
mask = BIT(27); |
||||
irq = 27; |
||||
goto handle_irq; |
||||
} |
||||
if (mask & BIT(29)) { |
||||
mask = BIT(29); |
||||
irq = 29; |
||||
goto handle_irq; |
||||
} |
||||
} |
||||
return 0; |
||||
handle_irq: |
||||
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg); |
||||
return mask; |
||||
} |
||||
|
||||
static inline int _xtensa_handle_one_int7(unsigned int mask) |
||||
{ |
||||
int irq; |
||||
|
||||
if (mask & BIT(14)) { |
||||
mask = BIT(14); |
||||
irq = 14; |
||||
goto handle_irq; |
||||
} |
||||
return 0; |
||||
handle_irq: |
||||
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg); |
||||
return mask; |
||||
} |
||||
|
||||
static inline int _xtensa_handle_one_int5(unsigned int mask) |
||||
{ |
||||
int irq; |
||||
|
||||
if (mask & BIT(16)) { |
||||
mask = BIT(16); |
||||
irq = 16; |
||||
goto handle_irq; |
||||
} |
||||
if (mask & BIT(26)) { |
||||
mask = BIT(26); |
||||
irq = 26; |
||||
goto handle_irq; |
||||
} |
||||
if (mask & BIT(31)) { |
||||
mask = BIT(31); |
||||
irq = 31; |
||||
goto handle_irq; |
||||
} |
||||
return 0; |
||||
handle_irq: |
||||
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg); |
||||
return mask; |
||||
} |
||||
|
||||
static inline int _xtensa_handle_one_int2(unsigned int mask) |
||||
{ |
||||
int irq; |
||||
|
||||
if (mask & BIT(19)) { |
||||
mask = BIT(19); |
||||
irq = 19; |
||||
goto handle_irq; |
||||
} |
||||
if (mask & BIT(20)) { |
||||
mask = BIT(20); |
||||
irq = 20; |
||||
goto handle_irq; |
||||
} |
||||
if (mask & BIT(21)) { |
||||
mask = BIT(21); |
||||
irq = 21; |
||||
goto handle_irq; |
||||
} |
||||
return 0; |
||||
handle_irq: |
||||
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg); |
||||
return mask; |
||||
} |
||||
|
||||
static inline int _xtensa_handle_one_int4(unsigned int mask) |
||||
{ |
||||
int irq; |
||||
|
||||
if (mask & 0x3000000) { |
||||
if (mask & BIT(24)) { |
||||
mask = BIT(24); |
||||
irq = 24; |
||||
goto handle_irq; |
||||
} |
||||
if (mask & BIT(25)) { |
||||
mask = BIT(25); |
||||
irq = 25; |
||||
goto handle_irq; |
||||
} |
||||
} else { |
||||
if (mask & BIT(28)) { |
||||
mask = BIT(28); |
||||
irq = 28; |
||||
goto handle_irq; |
||||
} |
||||
if (mask & BIT(30)) { |
||||
mask = BIT(30); |
||||
irq = 30; |
||||
goto handle_irq; |
||||
} |
||||
} |
||||
return 0; |
||||
handle_irq: |
||||
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg); |
||||
return mask; |
||||
} |
||||
|
||||
static inline int _xtensa_handle_one_int0(unsigned int mask) |
||||
{ |
||||
return 0; |
||||
} |
||||
static inline int _xtensa_handle_one_int6(unsigned int mask) |
||||
{ |
||||
return 0; |
||||
} |
||||
@ -0,0 +1,5 @@
@@ -0,0 +1,5 @@
|
||||
# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
|
||||
add_subdirectory(${SOC_SERIES}) |
||||
add_subdirectory(common) |
||||
@ -0,0 +1,16 @@
@@ -0,0 +1,16 @@
|
||||
# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
|
||||
config SOC_FAMILY_ESP32 |
||||
bool |
||||
|
||||
if SOC_FAMILY_ESP32 |
||||
|
||||
config SOC_FAMILY |
||||
string |
||||
default "espressif_esp32" |
||||
|
||||
source "soc/xtensa/espressif_esp32/common/Kconfig.soc" |
||||
source "soc/xtensa/espressif_esp32/*/Kconfig.soc" |
||||
|
||||
endif # SOC_FAMILY_ESP32 |
||||
@ -0,0 +1,5 @@
@@ -0,0 +1,5 @@
|
||||
# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
|
||||
source "soc/xtensa/espressif_esp32/common/Kconfig.defconfig.series" |
||||
source "soc/xtensa/espressif_esp32/*/Kconfig.defconfig.series" |
||||
@ -0,0 +1,4 @@
@@ -0,0 +1,4 @@
|
||||
# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
|
||||
source "soc/xtensa/espressif_esp32/*/Kconfig.series" |
||||
@ -0,0 +1,4 @@
@@ -0,0 +1,4 @@
|
||||
# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
|
||||
zephyr_include_directories(include) |
||||
@ -1,41 +1,44 @@
@@ -1,41 +1,44 @@
|
||||
# ESP32 board configuration |
||||
|
||||
# Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. |
||||
# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
|
||||
if SOC_ESP32S3 |
||||
if SOC_FAMILY_ESP32 |
||||
|
||||
if BOOTLOADER_MCUBOOT |
||||
config HAS_FLASH_LOAD_OFFSET |
||||
default y |
||||
# Xtensa default options for ESP32 family |
||||
config XTENSA_RESET_VECTOR |
||||
default n |
||||
|
||||
config MCUBOOT_GENERATE_UNSIGNED_IMAGE |
||||
default y |
||||
config XTENSA_USE_CORE_CRT1 |
||||
default n |
||||
|
||||
config MCUBOOT_GENERATE_CONFIRMED_IMAGE |
||||
default y |
||||
config GEN_ISR_TABLES |
||||
default y |
||||
|
||||
config ROM_START_OFFSET |
||||
default 0x20 |
||||
endif |
||||
config GEN_IRQ_VECTOR_TABLE |
||||
default n |
||||
|
||||
config SOC |
||||
default "esp32s3" |
||||
config CLOCK_CONTROL |
||||
default y |
||||
|
||||
config SOC_TOOLCHAIN_NAME |
||||
string |
||||
default "espressif_esp32s3" |
||||
config SYS_CLOCK_HW_CYCLES_PER_SEC |
||||
default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) |
||||
|
||||
config HEAP_MEM_POOL_SIZE |
||||
default 32768 |
||||
config XTENSA_CCOUNT_HZ |
||||
default SYS_CLOCK_HW_CYCLES_PER_SEC |
||||
|
||||
config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE |
||||
default n |
||||
|
||||
config SYS_CLOCK_HW_CYCLES_PER_SEC |
||||
default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) |
||||
if BOOTLOADER_MCUBOOT |
||||
|
||||
config XTENSA_CCOUNT_HZ |
||||
default SYS_CLOCK_HW_CYCLES_PER_SEC |
||||
config HAS_FLASH_LOAD_OFFSET |
||||
default y |
||||
config MCUBOOT_GENERATE_UNSIGNED_IMAGE |
||||
default y |
||||
config MCUBOOT_GENERATE_CONFIRMED_IMAGE |
||||
default y |
||||
config ROM_START_OFFSET |
||||
default 0x20 |
||||
|
||||
endif # BOOTLOADER_MCUBOOT |
||||
|
||||
endif |
||||
endif # SOC_FAMILY_ESP32 |
||||
@ -0,0 +1,194 @@
@@ -0,0 +1,194 @@
|
||||
# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
|
||||
if SOC_FAMILY_ESP32 |
||||
|
||||
config ESPTOOLPY_FLASHFREQ_80M |
||||
bool |
||||
|
||||
config FLASH_SIZE |
||||
int |
||||
|
||||
config FLASH_BASE_ADDRESS |
||||
hex |
||||
|
||||
config ESP_SPIRAM |
||||
bool "Support for external, SPI-connected RAM" |
||||
help |
||||
This enables support for an external SPI RAM chip, connected in |
||||
parallel with the main SPI flash chip. |
||||
|
||||
config ESP_HEAP_MIN_EXTRAM_THRESHOLD |
||||
int "Minimum threshold for external RAM allocation" |
||||
default 8192 |
||||
range 1024 131072 |
||||
depends on ESP_SPIRAM |
||||
help |
||||
Threshold to decide if memory will be allocated from DRAM |
||||
or SPIRAM. If value of allocation size is less than this value, |
||||
memory will be allocated from internal RAM. |
||||
|
||||
config ESP_HEAP_SEARCH_ALL_REGIONS |
||||
bool "Search for all available heap regions" |
||||
depends on ESP_SPIRAM |
||||
default y |
||||
help |
||||
This configuration enables searching all available heap |
||||
regions. If the region of desired capability is exhausted, |
||||
memory will be allocated from other available region. |
||||
|
||||
menu "SPI RAM config" |
||||
depends on ESP_SPIRAM |
||||
|
||||
choice SPIRAM_TYPE |
||||
prompt "Type of SPI RAM chip in use" |
||||
depends on ESP_SPIRAM |
||||
default SPIRAM_TYPE_ESPPSRAM16 |
||||
|
||||
config SPIRAM_TYPE_ESPPSRAM16 |
||||
bool "ESP-PSRAM16 or APS1604" |
||||
|
||||
config SPIRAM_TYPE_ESPPSRAM32 |
||||
bool "ESP-PSRAM32 or IS25WP032" |
||||
|
||||
config SPIRAM_TYPE_ESPPSRAM64 |
||||
bool "ESP-PSRAM64 or LY68L6400" |
||||
|
||||
endchoice # SPIRAM_TYPE |
||||
|
||||
config ESP_SPIRAM_SIZE |
||||
int "Size of SPIRAM part" |
||||
default 2097152 if SPIRAM_TYPE_ESPPSRAM16 |
||||
default 4194304 if SPIRAM_TYPE_ESPPSRAM32 |
||||
default 8388608 if SPIRAM_TYPE_ESPPSRAM64 |
||||
help |
||||
Specify size of SPIRAM part. |
||||
NOTE: If SPIRAM size is greater than 4MB, only |
||||
lower 4MB can be allocated using k_malloc(). |
||||
|
||||
choice SPIRAM_SPEED |
||||
prompt "Set RAM clock speed" |
||||
default SPIRAM_SPEED_40M |
||||
help |
||||
Select the speed for the SPI RAM chip. |
||||
If SPI RAM is enabled, we only support three combinations of SPI speed mode we supported now: |
||||
|
||||
1. Flash SPI running at 40MHz and RAM SPI running at 40MHz |
||||
2. Flash SPI running at 80MHz and RAM SPI running at 40MHz |
||||
3. Flash SPI running at 80MHz and RAM SPI running at 80MHz |
||||
|
||||
Note: If the third mode(80MHz+80MHz) is enabled for SPI RAM of type 32MBit, one of the HSPI/VSPI host |
||||
will be occupied by the system. Which SPI host to use can be selected by the config item |
||||
SPIRAM_OCCUPY_SPI_HOST. Application code should never touch HSPI/VSPI hardware in this case. The |
||||
option to select 80MHz will only be visible if the flash SPI speed is also 80MHz. |
||||
(ESPTOOLPY_FLASHFREQ_79M is true) |
||||
|
||||
config SPIRAM_SPEED_26M |
||||
bool "26MHz clock speed" |
||||
depends on SOC_SERIES_ESP32S2 |
||||
|
||||
config SPIRAM_SPEED_20M |
||||
bool "20MHz clock speed" |
||||
depends on SOC_SERIES_ESP32S2 |
||||
|
||||
config SPIRAM_SPEED_40M |
||||
bool "40MHz clock speed" |
||||
|
||||
config SPIRAM_SPEED_80M |
||||
depends on ESPTOOLPY_FLASHFREQ_80M |
||||
bool "80MHz clock speed" |
||||
|
||||
endchoice # SPIRAM_SPEED |
||||
|
||||
menu "PSRAM clock and cs IO for ESP32-DOWD" |
||||
|
||||
config D0WD_PSRAM_CLK_IO |
||||
int "PSRAM CLK IO number" |
||||
range 0 33 |
||||
default 17 |
||||
help |
||||
The PSRAM CLOCK IO can be any unused GPIO, user can config it based on hardware design. If user use |
||||
1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17. |
||||
|
||||
config D0WD_PSRAM_CS_IO |
||||
int "PSRAM CS IO number" |
||||
range 0 33 |
||||
default 16 |
||||
help |
||||
The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design. If user use |
||||
1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17. |
||||
|
||||
endmenu # PSRAM clock and cs IO for ESP32-DOWD |
||||
|
||||
menu "PSRAM clock and cs IO for ESP32-D2WD" |
||||
|
||||
config D2WD_PSRAM_CLK_IO |
||||
int "PSRAM CLK IO number" |
||||
range 0 33 |
||||
default 9 |
||||
help |
||||
User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram, |
||||
so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17. |
||||
|
||||
config D2WD_PSRAM_CS_IO |
||||
int "PSRAM CS IO number" |
||||
range 0 33 |
||||
default 10 |
||||
help |
||||
User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram, |
||||
so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17. |
||||
|
||||
endmenu # PSRAM clock and cs IO for ESP32-D2WD |
||||
|
||||
menu "PSRAM clock and cs IO for ESP32-PICO" |
||||
|
||||
config PICO_PSRAM_CS_IO |
||||
int "PSRAM CS IO number" |
||||
range 0 33 |
||||
default 10 |
||||
help |
||||
The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design. |
||||
|
||||
For ESP32-PICO chip, the psram share clock with flash, so user do not need to configure the clock |
||||
IO. |
||||
For the reference hardware design, please refer to |
||||
https://www.espressif.com/sites/default/files/documentation/esp32-pico-d4_datasheet_en.pdf |
||||
|
||||
endmenu # PSRAM clock and cs IO for ESP32-PICO |
||||
|
||||
config SPIRAM_CUSTOM_SPIWP_SD3_PIN |
||||
bool "Use custom SPI PSRAM WP(SD3) Pin when flash pins set in eFuse (read help)" |
||||
default y if SPIRAM_SPIWP_SD3_PIN != 7 # backwards compatibility, can remove in IDF 5 |
||||
default n |
||||
help |
||||
This setting is only used if the SPI flash pins have been overridden by setting the eFuses |
||||
SPI_PAD_CONFIG_xxx, and the SPI flash mode is DIO or DOUT. |
||||
|
||||
When this is the case, the eFuse config only defines 3 of the 4 Quad I/O data pins. The WP pin (aka |
||||
ESP32 pin "SD_DATA_3" or SPI flash pin "IO2") is not specified in eFuse. The psram only has QPI |
||||
mode, so a WP pin setting is necessary. |
||||
|
||||
If this config item is set to N (default), the correct WP pin will be automatically used for any |
||||
Espressif chip or module with integrated flash. If a custom setting is needed, set this config item |
||||
to Y and specify the GPIO number connected to the WP pin. |
||||
|
||||
When flash mode is set to QIO or QOUT, the PSRAM WP pin will be set the same as the SPI Flash WP pin |
||||
configured in the bootloader. |
||||
|
||||
config SPIRAM_SPIWP_SD3_PIN |
||||
int "Custom SPI PSRAM WP(SD3) Pin" |
||||
range 0 33 |
||||
default 7 |
||||
help |
||||
The option "Use custom SPI PSRAM WP(SD3) pin" must be set or this value is ignored |
||||
|
||||
If burning a customized set of SPI flash pins in eFuse and using DIO or DOUT mode for flash, set this |
||||
value to the GPIO number of the SPIRAM WP pin. |
||||
|
||||
config SPIRAM |
||||
bool |
||||
default y |
||||
|
||||
endmenu # SPI RAM config |
||||
|
||||
endif # SOC_FAMILY_ESP32 |
||||
@ -1,5 +1,5 @@
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. |
||||
* Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. |
||||
* |
||||
* SPDX-License-Identifier: Apache-2.0 |
||||
*/ |
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in new issue