diff --git a/drivers/interrupt_controller/CMakeLists.txt b/drivers/interrupt_controller/CMakeLists.txt index 93a41d3ec3f..2bb2dbe1633 100644 --- a/drivers/interrupt_controller/CMakeLists.txt +++ b/drivers/interrupt_controller/CMakeLists.txt @@ -15,8 +15,10 @@ zephyr_library_sources_ifdef(CONFIG_GIC_V3_ITS intc_gicv3_its.c) zephyr_library_sources_ifdef(CONFIG_GPIO_INTC_STM32WB0 intc_gpio_stm32wb0.c) zephyr_library_sources_ifdef(CONFIG_INTEL_VTD_ICTL intc_intel_vtd.c) zephyr_library_sources_ifdef(CONFIG_IOAPIC intc_ioapic.c) +zephyr_library_sources_ifdef(CONFIG_ITE_IT51XXX_INTC intc_ite_it51xxx.c) zephyr_library_sources_ifdef(CONFIG_ITE_IT8XXX2_INTC intc_ite_it8xxx2.c) zephyr_library_sources_ifdef(CONFIG_ITE_IT8XXX2_INTC_V2 intc_ite_it8xxx2_v2.c) +zephyr_library_sources_ifdef(CONFIG_ITE_IT51XXX_WUC wuc_ite_it51xxx.c) zephyr_library_sources_ifdef(CONFIG_ITE_IT8XXX2_WUC wuc_ite_it8xxx2.c) zephyr_library_sources_ifdef(CONFIG_LEON_IRQMP intc_irqmp.c) zephyr_library_sources_ifdef(CONFIG_LOAPIC intc_loapic.c intc_system_apic.c) diff --git a/drivers/interrupt_controller/Kconfig b/drivers/interrupt_controller/Kconfig index e5c2b028e11..3468cf4f3f2 100644 --- a/drivers/interrupt_controller/Kconfig +++ b/drivers/interrupt_controller/Kconfig @@ -66,6 +66,8 @@ source "drivers/interrupt_controller/Kconfig.loapic" source "drivers/interrupt_controller/Kconfig.dw" +source "drivers/interrupt_controller/Kconfig.it51xxx" + source "drivers/interrupt_controller/Kconfig.it8xxx2" source "drivers/interrupt_controller/Kconfig.stm32" diff --git a/drivers/interrupt_controller/Kconfig.it51xxx b/drivers/interrupt_controller/Kconfig.it51xxx new file mode 100644 index 00000000000..a3237c96906 --- /dev/null +++ b/drivers/interrupt_controller/Kconfig.it51xxx @@ -0,0 +1,26 @@ +# Copyright (c) 2025 ITE Corporation. All Rights Reserved. +# SPDX-License-Identifier: Apache-2.0 + +config HAS_ITE_INTC + bool + help + This option is selected when ITE_IT51XXX_INTC is enabled. + +config ITE_IT51XXX_INTC + def_bool DT_HAS_ITE_IT51XXX_INTC_ENABLED + depends on DT_HAS_ITE_IT51XXX_INTC_ENABLED + select HAS_ITE_INTC + help + This option mainly collects several interrupts from modules. + Configurable level-triggered and dege-triggered mode. + Configurable interrupt polarity of triggered mode. + Each interrupt source able to enabled/masked individually. + +config ITE_IT51XXX_WUC + bool "ITE it51xxx Wakeup controller (WUC) interface" + default y + depends on DT_HAS_ITE_IT51XXX_WUC_ENABLED + help + This option enables the wakeup controller interface for IT51XXX + family. + This is required for KSCAN, UART, eSPI, GPIO etc., interrupt support. diff --git a/drivers/interrupt_controller/intc_ite_it51xxx.c b/drivers/interrupt_controller/intc_ite_it51xxx.c new file mode 100644 index 00000000000..3e70f8449df --- /dev/null +++ b/drivers/interrupt_controller/intc_ite_it51xxx.c @@ -0,0 +1,210 @@ +/* + * Copyright (c) 2025 ITE Corporation. All Rights Reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include + +LOG_MODULE_REGISTER(intc_ite_it51xxx, LOG_LEVEL_DBG); + +/* it51xxx INTC registers definition */ +#define INTC_REG_OFFSET(n) ((n) < 3 ? 1 : 2) +#define INTC_GRPNISR(n) (4 * ((n) + INTC_REG_OFFSET(n))) +#define INTC_GRPNIER(n) (4 * ((n) + INTC_REG_OFFSET(n)) + 1) +#define INTC_GRPNIELMR(n) (4 * ((n) + INTC_REG_OFFSET(n)) + 2) +#define INTC_GRPNIPOLR(n) (4 * ((n) + INTC_REG_OFFSET(n)) + 3) +#define INTC_IVECT 0x10 + +#define II51XXX_INTC_GROUP_COUNT 29 +#define MAX_REGISR_IRQ_NUM 8 +#define IVECT_OFFSET_WITH_IRQ 0x10 + +static mm_reg_t intc_base = DT_REG_ADDR(DT_NODELABEL(intc)); +/* Interrupt number of INTC module */ +static uint8_t intc_irq; +static uint8_t ier_setting[II51XXX_INTC_GROUP_COUNT]; + +void ite_intc_save_and_disable_interrupts(void) +{ + volatile uint8_t _ier __unused; + /* Disable global interrupt for critical section */ + unsigned int key = irq_lock(); + + /* Save and disable interrupts */ + for (int i = 0; i < II51XXX_INTC_GROUP_COUNT; i++) { + ier_setting[i] = sys_read8(intc_base + INTC_GRPNIER(i)); + sys_write8(0, intc_base + INTC_GRPNIER(i)); + } + /* + * This load operation will guarantee the above modification of + * SOC's register can be seen by any following instructions. + * Note: Barrier instruction can not synchronize chip register, + * so we introduce workaround here. + */ + _ier = sys_read8(intc_base + INTC_GRPNIER(II51XXX_INTC_GROUP_COUNT - 1)); + + irq_unlock(key); +} + +void ite_intc_restore_interrupts(void) +{ + /* + * Ensure the highest priority interrupt will be the first fired + * interrupt when soc is ready to go. + */ + unsigned int key = irq_lock(); + + /* Restore interrupt state */ + for (int i = 0; i < II51XXX_INTC_GROUP_COUNT; i++) { + sys_write8(ier_setting[i], intc_base + INTC_GRPNIER(i)); + } + + irq_unlock(key); +} + +void ite_intc_isr_clear(unsigned int irq) +{ + uint32_t g, i; + + if (irq > CONFIG_NUM_IRQS) { + return; + } + g = irq / MAX_REGISR_IRQ_NUM; + i = irq % MAX_REGISR_IRQ_NUM; + + sys_write8(BIT(i), intc_base + INTC_GRPNISR(g)); +} + +void ite_intc_irq_enable(unsigned int irq) +{ + uint32_t g, i; + uint8_t en; + + if (irq > CONFIG_NUM_IRQS) { + return; + } + g = irq / MAX_REGISR_IRQ_NUM; + i = irq % MAX_REGISR_IRQ_NUM; + + /* critical section due to run a bit-wise OR operation */ + unsigned int key = irq_lock(); + + en = sys_read8(intc_base + INTC_GRPNIER(g)); + sys_write8(en | BIT(i), intc_base + INTC_GRPNIER(g)); + + irq_unlock(key); +} + +void ite_intc_irq_disable(unsigned int irq) +{ + uint32_t g, i; + uint8_t en; + + volatile uint8_t _ier __unused; + + if (irq > CONFIG_NUM_IRQS) { + return; + } + g = irq / MAX_REGISR_IRQ_NUM; + i = irq % MAX_REGISR_IRQ_NUM; + + /* critical section due to run a bit-wise OR operation */ + unsigned int key = irq_lock(); + + en = sys_read8(intc_base + INTC_GRPNIER(g)); + sys_write8(en & ~BIT(i), intc_base + INTC_GRPNIER(g)); + /* + * This load operation will guarantee the above modification of + * SOC's register can be seen by any following instructions. + */ + _ier = sys_read8(intc_base + INTC_GRPNIER(g)); + + irq_unlock(key); +} + +void ite_intc_irq_polarity_set(unsigned int irq, unsigned int flags) +{ + uint32_t g, i; + uint8_t tri; + + if ((irq > CONFIG_NUM_IRQS) || ((flags & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)) { + return; + } + g = irq / MAX_REGISR_IRQ_NUM; + i = irq % MAX_REGISR_IRQ_NUM; + + tri = sys_read8(intc_base + INTC_GRPNIPOLR(g)); + if ((flags & IRQ_TYPE_LEVEL_HIGH) || (flags & IRQ_TYPE_EDGE_RISING)) { + sys_write8(tri & ~BIT(i), intc_base + INTC_GRPNIPOLR(g)); + } else { + sys_write8(tri | BIT(i), intc_base + INTC_GRPNIPOLR(g)); + } + + tri = sys_read8(intc_base + INTC_GRPNIELMR(g)); + if ((flags & IRQ_TYPE_LEVEL_LOW) || (flags & IRQ_TYPE_LEVEL_HIGH)) { + sys_write8(tri & ~BIT(i), intc_base + INTC_GRPNIELMR(g)); + } else { + sys_write8(tri | BIT(i), intc_base + INTC_GRPNIELMR(g)); + } + + /* W/C interrupt status of the pin */ + sys_write8(BIT(i), intc_base + INTC_GRPNISR(g)); +} + +int ite_intc_irq_is_enable(unsigned int irq) +{ + uint32_t g, i; + uint8_t en; + + if (irq > CONFIG_NUM_IRQS) { + return 0; + } + g = irq / MAX_REGISR_IRQ_NUM; + i = irq % MAX_REGISR_IRQ_NUM; + + en = sys_read8(intc_base + INTC_GRPNIER(g)); + + return (en & BIT(i)); +} + +uint8_t ite_intc_get_irq_num(void) +{ + return intc_irq; +} + +uint8_t get_irq(void *arg) +{ + ARG_UNUSED(arg); + /* wait until two equal interrupt values are read */ + do { + /* Read interrupt number from interrupt vector register */ + intc_irq = sys_read8(intc_base + INTC_IVECT); + /* + * WORKAROUND: when the interrupt vector register (INTC_VECT) + * isn't latched in a load operation, we read it again to make + * sure the value we got is the correct value. + */ + } while (intc_irq != sys_read8(intc_base + INTC_IVECT)); + /* determine interrupt number */ + intc_irq -= IVECT_OFFSET_WITH_IRQ; + /* clear interrupt status */ + ite_intc_isr_clear(intc_irq); + /* return interrupt number */ + return intc_irq; +} + +void soc_interrupt_init(void) +{ + /* Ensure interrupts of soc are disabled at default */ + for (int i = 0; i < II51XXX_INTC_GROUP_COUNT; i++) { + sys_write8(0, intc_base + INTC_GRPNIER(i)); + } + + /* Enable M-mode external interrupt */ + csr_set(mie, MIP_MEIP); +} diff --git a/drivers/interrupt_controller/wuc_ite_it51xxx.c b/drivers/interrupt_controller/wuc_ite_it51xxx.c new file mode 100644 index 00000000000..41f3627e177 --- /dev/null +++ b/drivers/interrupt_controller/wuc_ite_it51xxx.c @@ -0,0 +1,150 @@ +/* + * Copyright (c) 2025 ITE Corporation. All Rights Reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT ite_it51xxx_wuc + +#include +#include +#include +#include +#include + +LOG_MODULE_REGISTER(wuc_ite_it51xxx, CONFIG_INTC_LOG_LEVEL); + +/* Driver config */ +struct it51xxx_wuc_cfg { + /* WUC wakeup edge mode register */ + uint8_t *reg_wuemr; + /* WUC wakeup edge sense register */ + uint8_t *reg_wuesr; + /* WUC wakeup enable register */ + uint8_t *reg_wuenr; + /* WUC level or edge mode register */ + uint8_t *reg_wuler; + bool wakeup_ctrl; + bool both_edge_trigger; +}; + +void it51xxx_wuc_enable(const struct device *dev, uint8_t mask) +{ + const struct it51xxx_wuc_cfg *config = dev->config; + volatile uint8_t *reg_wuenr = config->reg_wuenr; + + if (!config->wakeup_ctrl) { + LOG_ERR("Wakeup control(enable) is not supported."); + return; + } + /* + * WUC group only 1, 3, and 4 have enable/disable register, + * others are always enabled. + */ + if (reg_wuenr == IT51XXX_WUC_UNUSED_REG) { + return; + } + + /* Enable wakeup interrupt of the pin */ + *reg_wuenr |= mask; +} + +void it51xxx_wuc_disable(const struct device *dev, uint8_t mask) +{ + const struct it51xxx_wuc_cfg *config = dev->config; + volatile uint8_t *reg_wuenr = config->reg_wuenr; + + if (!config->wakeup_ctrl) { + LOG_ERR("Wakeup control(disable) is not supported."); + return; + } + /* + * WUC group only 1, 3, and 4 have enable/disable register, + * others are always enabled. + */ + if (reg_wuenr == IT51XXX_WUC_UNUSED_REG) { + return; + } + + /* Disable wakeup interrupt of the pin */ + *reg_wuenr &= ~mask; +} + +void it51xxx_wuc_clear_status(const struct device *dev, uint8_t mask) +{ + const struct it51xxx_wuc_cfg *config = dev->config; + volatile uint8_t *reg_wuesr = config->reg_wuesr; + + if (!config->wakeup_ctrl) { + LOG_ERR("Wakeup control of clear status is not supported."); + return; + } + + if (reg_wuesr == IT51XXX_WUC_UNUSED_REG) { + return; + } + + /* W/C wakeup interrupt status of the pin */ + *reg_wuesr = mask; +} + +void it51xxx_wuc_set_polarity(const struct device *dev, uint8_t mask, uint32_t flags) +{ + const struct it51xxx_wuc_cfg *config = dev->config; + volatile uint8_t *reg_wuemr = config->reg_wuemr; + volatile uint8_t *reg_wuler = config->reg_wuler; + volatile uint8_t *reg_wuesr = config->reg_wuesr; + + if (!config->wakeup_ctrl) { + LOG_ERR("Wakeup control of set polarity is not supported."); + return; + } + + if (reg_wuemr == IT51XXX_WUC_UNUSED_REG) { + return; + } + + if (flags & WUC_TYPE_LEVEL_TRIG) { + *reg_wuler |= mask; + if (flags & WUC_TYPE_LEVEL_HIGH) { + *reg_wuemr &= ~mask; + } else { + *reg_wuemr |= mask; + } + } else { + *reg_wuler &= ~mask; + if ((flags & WUC_TYPE_EDGE_BOTH) == WUC_TYPE_EDGE_RISING) { + /* Rising-edge trigger mode */ + *reg_wuemr &= ~mask; + } else { + if (((flags & WUC_TYPE_EDGE_BOTH) == WUC_TYPE_EDGE_FALLING) && + config->both_edge_trigger) { + LOG_WRN("Group 7, 10, 12 do not support falling edge mode."); + } + if (((flags & WUC_TYPE_EDGE_BOTH) == WUC_TYPE_EDGE_BOTH) && + !config->both_edge_trigger) { + LOG_WRN("Both edge trigger mode only support group 7, 10, 12.\n" + "Not support dev = %s", + dev->name); + } + /* Falling-edge or both edge trigger mode */ + *reg_wuemr |= mask; + } + } + /* W/C wakeup interrupt status of the pin */ + *reg_wuesr = mask; +} + +#define IT51XXX_WUC_INIT(inst) \ + static const struct it51xxx_wuc_cfg it51xxx_wuc_cfg_##inst = { \ + .reg_wuemr = (uint8_t *)DT_INST_REG_ADDR_BY_IDX(inst, 0), \ + .reg_wuesr = (uint8_t *)DT_INST_REG_ADDR_BY_IDX(inst, 1), \ + .reg_wuenr = (uint8_t *)DT_INST_REG_ADDR_BY_IDX(inst, 2), \ + .reg_wuler = (uint8_t *)DT_INST_REG_ADDR_BY_IDX(inst, 3), \ + .wakeup_ctrl = DT_INST_PROP(inst, wakeup_controller), \ + .both_edge_trigger = DT_INST_PROP(inst, both_edge_trigger), \ + }; \ + DEVICE_DT_INST_DEFINE(inst, NULL, NULL, NULL, &it51xxx_wuc_cfg_##inst, PRE_KERNEL_1, \ + CONFIG_KERNEL_INIT_PRIORITY_OBJECTS, NULL); + +DT_INST_FOREACH_STATUS_OKAY(IT51XXX_WUC_INIT) diff --git a/dts/bindings/interrupt-controller/ite,it51xxx-intc.yaml b/dts/bindings/interrupt-controller/ite,it51xxx-intc.yaml new file mode 100644 index 00000000000..3b22729b1b4 --- /dev/null +++ b/dts/bindings/interrupt-controller/ite,it51xxx-intc.yaml @@ -0,0 +1,15 @@ +# Copyright (c) 2025 ITE Corporation. All Rights Reserved. +# SPDX-License-Identifier: Apache-2.0 + +description: ITE Interrupt controller +compatible: "ite,it51xxx-intc" + +include: [interrupt-controller.yaml, base.yaml] + +properties: + reg: + required: true + +interrupt-cells: + - irq + - flags diff --git a/dts/bindings/interrupt-controller/ite,it51xxx-wuc-map.yaml b/dts/bindings/interrupt-controller/ite,it51xxx-wuc-map.yaml new file mode 100644 index 00000000000..4d32305e609 --- /dev/null +++ b/dts/bindings/interrupt-controller/ite,it51xxx-wuc-map.yaml @@ -0,0 +1,13 @@ +# Copyright (c) 2025 ITE Corporation. All Rights Reserved. +# SPDX-License-Identifier: Apache-2.0 + +description: ITE Wake-Up Controller (WUC) mapping child node + +compatible: "ite,it51xxx-wuc-map" + +child-binding: + description: Child node to present the mapping between input of WUC and its source device + properties: + wucs: + type: phandle-array + required: true diff --git a/dts/bindings/interrupt-controller/ite,it51xxx-wuc.yaml b/dts/bindings/interrupt-controller/ite,it51xxx-wuc.yaml new file mode 100644 index 00000000000..fa32f96b85b --- /dev/null +++ b/dts/bindings/interrupt-controller/ite,it51xxx-wuc.yaml @@ -0,0 +1,31 @@ +# Copyright (c) 2025 ITE Corporation. All Rights Reserved. +# SPDX-License-Identifier: Apache-2.0 + +description: ITE Wake-Up Controller (WUC) +compatible: "ite,it51xxx-wuc" + +include: [base.yaml] + +properties: + reg: + required: true + + wakeup-controller: + type: boolean + description: | + conveys that this node is a wakeup controller + + both-edge-trigger: + type: boolean + description: | + Rising-edge or falling-edge triggered is selected. + + "#wuc-cells": + type: int + required: true + description: | + number of items to expect in a wakeup controller specifier + const: 1 + +wuc-cells: + - mask diff --git a/dts/riscv/ite/it51xxx-wuc-map.dtsi b/dts/riscv/ite/it51xxx-wuc-map.dtsi new file mode 100644 index 00000000000..248fd20b302 --- /dev/null +++ b/dts/riscv/ite/it51xxx-wuc-map.dtsi @@ -0,0 +1,337 @@ +/* + * Copyright (c) 2025 ITE Corporation. All Rights Reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + /* Mapping between wuc bits and source device */ + it51xxx-wuc-map { + compatible = "ite,it51xxx-wuc-map"; + + /* WUC group 2 */ + wuc_wu20: wu20 { + wucs = <&wuc2 BIT(0)>; /* GPD0 */ + }; + wuc_wu21: wu21 { + wucs = <&wuc2 BIT(1)>; /* GPD1 */ + }; + wuc_wu22: wu22 { + wucs = <&wuc2 BIT(2)>; /* GPC4 */ + }; + wuc_wu23: wu23 { + wucs = <&wuc2 BIT(3)>; /* GPC6 */ + }; + wuc_wu24: wu24{ + wucs = <&wuc2 BIT(4)>; /* GPD2 */ + }; + wuc_wu25: wu25 { + wucs = <&wuc2 BIT(5)>; /* GPB3 */ + }; + + /* WUC group 3 */ + wuc_wu30: wu30 { + wucs = <&wuc3 BIT(0)>; /* KSI[0] */ + }; + wuc_wu31: wu31 { + wucs = <&wuc3 BIT(1)>; /* KSI[1] */ + }; + wuc_wu32: wu32 { + wucs = <&wuc3 BIT(2)>; /* KSI[2] */ + }; + wuc_wu33: wu33 { + wucs = <&wuc3 BIT(3)>; /* KSI[3] */ + }; + wuc_wu34: wu34{ + wucs = <&wuc3 BIT(4)>; /* KSI[4] */ + }; + wuc_wu35: wu35 { + wucs = <&wuc3 BIT(5)>; /* KSI[5] */ + }; + wuc_wu36: wu36 { + wucs = <&wuc3 BIT(6)>; /* KSI[6] */ + }; + wuc_wu37: wu37 { + wucs = <&wuc3 BIT(7)>; /* KSI[7] */ + }; + + /* WUC group 4 */ + wuc_wu40: wu40 { + wucs = <&wuc4 BIT(0)>; /* GPE5 */ + }; + wuc_wu42: wu42 { + wucs = <&wuc4 BIT(2)>; /* eSPI transaction */ + }; + wuc_wu45: wu45 { + wucs = <&wuc4 BIT(5)>; /* GPE6 */ + }; + wuc_wu46: wu46 { + wucs = <&wuc4 BIT(6)>; /* GPE7 */ + }; + + /* WUC group 6 */ + wuc_wu60: wu60 { + wucs = <&wuc6 BIT(0)>; /* GPH0 */ + }; + wuc_wu61: wu61 { + wucs = <&wuc6 BIT(1)>; /* GPH1 */ + }; + wuc_wu62: wu62 { + wucs = <&wuc6 BIT(2)>; /* GPH2 */ + }; + wuc_wu63: wu63 { + wucs = <&wuc6 BIT(3)>; /* GPH3 */ + }; + wuc_wu64: wu64 { + wucs = <&wuc6 BIT(4)>; /* GPF4 */ + }; + wuc_wu65: wu65 { + wucs = <&wuc6 BIT(5)>; /* GPF5 */ + }; + wuc_wu66: wu66 { + wucs = <&wuc6 BIT(6)>; /* GPF6 */ + }; + wuc_wu67: wu67 { + wucs = <&wuc6 BIT(7)>; /* GPF7 */ + }; + + /* WUC group 7 */ + wuc_wu70: wu70 { + wucs = <&wuc7 BIT(0)>; /* GPE0 */ + }; + wuc_wu71: wu71 { + wucs = <&wuc7 BIT(1)>; /* GPE1 */ + }; + wuc_wu72: wu72 { + wucs = <&wuc7 BIT(2)>; /* GPE2 */ + }; + wuc_wu73: wu73 { + wucs = <&wuc7 BIT(3)>; /* GPE3 */ + }; + wuc_wu74: wu74 { + wucs = <&wuc7 BIT(4)>; /* GPI4 */ + }; + wuc_wu75: wu75 { + wucs = <&wuc7 BIT(5)>; /* GPI5 */ + }; + wuc_wu76: wu76 { + wucs = <&wuc7 BIT(6)>; /* GPI6 */ + }; + wuc_wu77: wu77 { + wucs = <&wuc7 BIT(7)>; /* GPI7 */ + }; + + /* WUC group 8 */ + wuc_wu80: wu80 { + wucs = <&wuc8 BIT(0)>; /* GPA3 */ + }; + wuc_wu81: wu81 { + wucs = <&wuc8 BIT(1)>; /* GPA4 */ + }; + wuc_wu82: wu82 { + wucs = <&wuc8 BIT(2)>; /* GPA5 */ + }; + wuc_wu83: wu83 { + wucs = <&wuc8 BIT(3)>; /* GPA6 */ + }; + wuc_wu84: wu84 { + wucs = <&wuc8 BIT(4)>; /* GPB2 */ + }; + wuc_wu85: wu85 { + wucs = <&wuc8 BIT(5)>; /* GPC0 */ + }; + wuc_wu86: wu86 { + wucs = <&wuc8 BIT(6)>; /* GPC7 */ + }; + wuc_wu87: wu87 { + wucs = <&wuc8 BIT(7)>; /* GPD7 */ + }; + + /* WUC group 9 */ + wuc_wu88: wu88 { + wucs = <&wuc9 BIT(0)>; /* GPH4 */ + }; + wuc_wu89: wu89 { + wucs = <&wuc9 BIT(1)>; /* GPH5 */ + }; + wuc_wu90: wu90 { + wucs = <&wuc9 BIT(2)>; /* GPH6 */ + }; + wuc_wu91: wu91 { + wucs = <&wuc9 BIT(3)>; /* GPA0 */ + }; + wuc_wu92: wu92 { + wucs = <&wuc9 BIT(4)>; /* GPA1 */ + }; + wuc_wu93: wu93 { + wucs = <&wuc9 BIT(5)>; /* GPA2 */ + }; + wuc_wu95: wu95 { + wucs = <&wuc9 BIT(7)>; /* GPC2 */ + }; + + /* WUC group 10 */ + wuc_wu96: wu96 { + wucs = <&wuc10 BIT(0)>; /* GPF0 */ + }; + wuc_wu97: wu97 { + wucs = <&wuc10 BIT(1)>; /* GPF1 */ + }; + wuc_wu98: wu98 { + wucs = <&wuc10 BIT(2)>; /* GPF2 */ + }; + wuc_wu99: wu99 { + wucs = <&wuc10 BIT(3)>; /* GPF3 */ + }; + wuc_wu100: wu100 { + wucs = <&wuc10 BIT(4)>; /* GPA7 */ + }; + wuc_wu101: wu101 { + wucs = <&wuc10 BIT(5)>; /* GPB0 */ + }; + wuc_wu102: wu102 { + wucs = <&wuc10 BIT(6)>; /* GPB1 */ + }; + wuc_wu103: wu103 { + wucs = <&wuc10 BIT(7)>; /* GPB3 */ + }; + + /* WUC group 11 */ + wuc_wu104: wu104 { + wucs = <&wuc11 BIT(0)>; /* GPB5 */ + }; + wuc_wu105: wu105 { + wucs = <&wuc11 BIT(1)>; /* GPB6 */ + }; + wuc_wu107: wu107 { + wucs = <&wuc11 BIT(3)>; /* GPC1 */ + }; + wuc_wu108: wu108 { + wucs = <&wuc11 BIT(4)>; /* GPC3 */ + }; + wuc_wu109: wu109 { + wucs = <&wuc11 BIT(5)>; /* GPC5 */ + }; + wuc_wu110: wu110 { + wucs = <&wuc11 BIT(6)>; /* GPD3 */ + }; + wuc_wu111: wu111 { + wucs = <&wuc11 BIT(7)>; /* GPD4 */ + }; + + /* WUC group 12 */ + wuc_wu112: wu112 { + wucs = <&wuc12 BIT(0)>; /* GPD5 */ + }; + wuc_wu113: wu113 { + wucs = <&wuc12 BIT(1)>; /* GPD6 */ + }; + wuc_wu114: wu114 { + wucs = <&wuc12 BIT(2)>; /* GPE4 */ + }; + wuc_wu115: wu115 { + wucs = <&wuc12 BIT(3)>; /* GPG0 */ + }; + wuc_wu116: wu116 { + wucs = <&wuc12 BIT(4)>; /* GPG1 */ + }; + wuc_wu117: wu117 { + wucs = <&wuc12 BIT(5)>; /* GPG2 */ + }; + wuc_wu118: wu118 { + wucs = <&wuc12 BIT(6)>; /* GPG6 */ + }; + wuc_wu119: wu119 { + wucs = <&wuc12 BIT(7)>; /* GPI0 */ + }; + + /* WUC group 13 */ + wuc_wu120: wu120 { + wucs = <&wuc13 BIT(0)>; /* GPI1 */ + }; + wuc_wu121: wu121 { + wucs = <&wuc13 BIT(1)>; /* GPI2 */ + }; + wuc_wu122: wu122 { + wucs = <&wuc13 BIT(2)>; /* GPI3 */ + }; + wuc_wu127: wu127 { + wucs = <&wuc13 BIT(7)>; /* GPH7 */ + }; + + /* WUC group 14 */ + wuc_wu128: wu128 { + wucs = <&wuc14 BIT(0)>; /* GPJ0 */ + }; + wuc_wu129: wu129 { + wucs = <&wuc14 BIT(1)>; /* GPJ1 */ + }; + wuc_wu131: wu131 { + wucs = <&wuc14 BIT(3)>; /* GPJ3 */ + }; + wuc_wu132: wu132 { + wucs = <&wuc14 BIT(4)>; /* GPJ4 */ + }; + wuc_wu133: wu133 { + wucs = <&wuc14 BIT(5)>; /* GPJ5 */ + }; + wuc_wu134: wu134 { + wucs = <&wuc14 BIT(6)>; /* GPJ6 */ + }; + wuc_wu135: wu135 { + wucs = <&wuc14 BIT(7)>; /* GPJ7 */ + }; + + /* WUC group 15 */ + wuc_wu136: wu136 { + wucs = <&wuc15 BIT(0)>; /* GPL0 */ + }; + wuc_wu137: wu137 { + wucs = <&wuc15 BIT(1)>; /* GPL1 */ + }; + wuc_wu138: wu138 { + wucs = <&wuc15 BIT(2)>; /* GPL2 */ + }; + wuc_wu139: wu139 { + wucs = <&wuc15 BIT(3)>; /* GPL3 */ + }; + wuc_wu140: wu140 { + wucs = <&wuc15 BIT(4)>; /* GPL4 */ + }; + wuc_wu141: wu141 { + wucs = <&wuc15 BIT(5)>; /* GPL5 */ + }; + wuc_wu142: wu142 { + wucs = <&wuc15 BIT(6)>; /* GPL6 */ + }; + + /* WUC group 16 */ + wuc_wu144: wu144 { + wucs = <&wuc16 BIT(0)>; /* GPM0 */ + }; + wuc_wu145: wu145 { + wucs = <&wuc16 BIT(1)>; /* GPM1 */ + }; + wuc_wu146: wu146 { + wucs = <&wuc16 BIT(2)>; /* GPM2 */ + }; + wuc_wu147: wu147 { + wucs = <&wuc16 BIT(3)>; /* GPM3 */ + }; + wuc_wu148: wu148 { + wucs = <&wuc16 BIT(4)>; /* GPM4 */ + }; + wuc_wu149: wu149 { + wucs = <&wuc16 BIT(5)>; /* GPM5 */ + }; + wuc_wu150: wu150 { + wucs = <&wuc16 BIT(6)>; /* GPM6 */ + }; + + wuc_no_func: no_func { + wucs = <&wuc_fake 0>; + }; + }; +}; diff --git a/dts/riscv/ite/it51xxx.dtsi b/dts/riscv/ite/it51xxx.dtsi index b69fb4fcc7f..722a721742b 100644 --- a/dts/riscv/ite/it51xxx.dtsi +++ b/dts/riscv/ite/it51xxx.dtsi @@ -4,8 +4,11 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include #include #include +#include +#include / { #address-cells = <1>; @@ -62,9 +65,179 @@ reg = <0x00f01600 0x100>; }; + wuc1: wakeup-controller@f01b00 { + compatible = "ite,it51xxx-wuc"; + reg = <0x00f01b00 1 /* WUEMR1 */ + 0x00f01b04 1 /* WUESR1 */ + 0x00f01b08 1 /* WUENR1 */ + 0x00f01b3c 1>; /* WUBEMR1 */ + wakeup-controller; + #wuc-cells = <1>; + }; + + wuc2: wakeup-controller@f01b01 { + compatible = "ite,it51xxx-wuc"; + reg = <0x00f01b01 1 /* WUEMR2 */ + 0x00f01b05 1 /* WUESR2 */ + IT51XXX_WUC_UNUSED_REG 1 /* WUENR2 */ + 0x00f01b3d 1>; /* WUBEMR2 */ + wakeup-controller; + #wuc-cells = <1>; + }; + + wuc3: wakeup-controller@f01b02 { + compatible = "ite,it51xxx-wuc"; + reg = <0x00f01b02 1 /* WUEMR3 */ + 0x00f01b06 1 /* WUESR3 */ + 0x00f01b0a 1 /* WUENR3 */ + 0x00f01b3e 1>; /* WUBEMR3 */ + wakeup-controller; + #wuc-cells = <1>; + }; + + wuc4: wakeup-controller@f01b03 { + compatible = "ite,it51xxx-wuc"; + reg = <0x00f01b03 1 /* WUEMR4 */ + 0x00f01b07 1 /* WUESR4 */ + 0x00f01b0b 1 /* WUENR4 */ + 0x00f01b3f 1>; /* WUBEMR4 */ + wakeup-controller; + #wuc-cells = <1>; + }; + + wuc6: wakeup-controller@f01b10 { + compatible = "ite,it51xxx-wuc"; + reg = <0x00f01b10 1 /* WUEMR6 */ + 0x00f01b11 1 /* WUESR6 */ + IT51XXX_WUC_UNUSED_REG 1 /* WUENR6 */ + 0x00f01b13 1>; /* WUBEMR6 */ + wakeup-controller; + #wuc-cells = <1>; + }; + + wuc7: wakeup-controller@f01b14 { + compatible = "ite,it51xxx-wuc"; + reg = <0x00f01b14 1 /* WUEMR7 */ + 0x00f01b15 1 /* WUESR7 */ + IT51XXX_WUC_UNUSED_REG 1 /* WUENR7 */ + 0x00f01b17 1>; /* WUBEMR7 */ + wakeup-controller; + both-edge-trigger; + #wuc-cells = <1>; + }; + + wuc8: wakeup-controller@f01b18 { + compatible = "ite,it51xxx-wuc"; + reg = <0x00f01b18 1 /* WUEMR8 */ + 0x00f01b19 1 /* WUESR8 */ + IT51XXX_WUC_UNUSED_REG 1 /* WUENR8 */ + 0x00f01b1b 1>; /* WUBEMR8 */ + wakeup-controller; + #wuc-cells = <1>; + }; + + wuc9: wakeup-controller@f01b1c { + compatible = "ite,it51xxx-wuc"; + reg = <0x00f01b1c 1 /* WUEMR9 */ + 0x00f01b1d 1 /* WUESR9 */ + IT51XXX_WUC_UNUSED_REG 1 /* WUENR9 */ + 0x00f01b1f 1>; /* WUBEMR9 */ + wakeup-controller; + #wuc-cells = <1>; + }; + + wuc10: wakeup-controller@f01b20 { + compatible = "ite,it51xxx-wuc"; + reg = <0x00f01b20 1 /* WUEMR10 */ + 0x00f01b21 1 /* WUESR10 */ + IT51XXX_WUC_UNUSED_REG 1 /* WUENR10 */ + 0x00f01b23 1>; /* WUBEMR10 */ + wakeup-controller; + both-edge-trigger; + #wuc-cells = <1>; + }; + + wuc11: wakeup-controller@f01b24 { + compatible = "ite,it51xxx-wuc"; + reg = <0x00f01b24 1 /* WUEMR11 */ + 0x00f01b25 1 /* WUESR11 */ + IT51XXX_WUC_UNUSED_REG 1 /* WUENR11 */ + 0x00f01b27 1>; /* WUBEMR11 */ + wakeup-controller; + #wuc-cells = <1>; + }; + + wuc12: wakeup-controller@f01b28 { + compatible = "ite,it51xxx-wuc"; + reg = <0x00f01b28 1 /* WUEMR12 */ + 0x00f01b29 1 /* WUESR12 */ + IT51XXX_WUC_UNUSED_REG 1 /* WUENR12 */ + 0x00f01b2b 1>; /* WUBEMR12 */ + wakeup-controller; + both-edge-trigger; + #wuc-cells = <1>; + }; + + wuc13: wakeup-controller@f01b2c { + compatible = "ite,it51xxx-wuc"; + reg = <0x00f01b2c 1 /* WUEMR13 */ + 0x00f01b2d 1 /* WUESR13 */ + IT51XXX_WUC_UNUSED_REG 1 /* WUENR13 */ + 0x00f01b2f 1>; /* WUBEMR13 */ + wakeup-controller; + #wuc-cells = <1>; + }; + + wuc14: wakeup-controller@f01b30 { + compatible = "ite,it51xxx-wuc"; + reg = <0x00f01b30 1 /* WUEMR14 */ + 0x00f01b31 1 /* WUESR14 */ + IT51XXX_WUC_UNUSED_REG 1 /* WUENR14 */ + 0x00f01b33 1>; /* WUBEMR14 */ + wakeup-controller; + #wuc-cells = <1>; + }; + + wuc15: wakeup-controller@f01b34 { + compatible = "ite,it51xxx-wuc"; + reg = <0x00f01b34 1 /* WUEMR15 */ + 0x00f01b35 1 /* WUESR15 */ + IT51XXX_WUC_UNUSED_REG 1 /* WUENR15 */ + 0x00f01b37 1>; /* WUBEMR15 */ + wakeup-controller; + #wuc-cells = <1>; + }; + + wuc16: wakeup-controller@f01b38 { + compatible = "ite,it51xxx-wuc"; + reg = <0x00f01b38 1 /* WUEMR16 */ + 0x00f01b39 1 /* WUESR16 */ + IT51XXX_WUC_UNUSED_REG 1 /* WUENR16 */ + 0x00f01b3b 1>; /* WUBEMR16 */ + wakeup-controller; + #wuc-cells = <1>; + }; + + wuc_fake: wakeup-controller@0 { + compatible = "ite,it51xxx-wuc"; + reg = <0 1 + 0 1 + 0 1 + 0 1>; + #wuc-cells = <1>; + }; + gctrl: general-control@f02000 { compatible = "ite,it51xxx-gctrl"; reg = <0x00f02000 0x100>; }; + + intc: interrupt-controller@f04300 { + compatible = "ite,it51xxx-intc"; + #address-cells = <0>; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0x00f04300 0x0100>; + }; }; }; diff --git a/include/zephyr/drivers/interrupt_controller/wuc_ite_it51xxx.h b/include/zephyr/drivers/interrupt_controller/wuc_ite_it51xxx.h new file mode 100644 index 00000000000..f039381af75 --- /dev/null +++ b/include/zephyr/drivers/interrupt_controller/wuc_ite_it51xxx.h @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2025 ITE Corporation. All Rights Reserved + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_IT51XXX_WUC_H_ +#define ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_IT51XXX_WUC_H_ + +#include + +/** + * @name wakeup controller flags + * @{ + */ +/** WUC rising edge trigger mode */ +#define WUC_TYPE_EDGE_RISING BIT(0) +/** WUC falling edge trigger mode */ +#define WUC_TYPE_EDGE_FALLING BIT(1) +/** WUC both edge trigger mode */ +#define WUC_TYPE_EDGE_BOTH (WUC_TYPE_EDGE_RISING | WUC_TYPE_EDGE_FALLING) + +#define WUC_TYPE_LEVEL_TRIG BIT(2) +/** WUC level high trigger mode */ +#define WUC_TYPE_LEVEL_HIGH BIT(3) +/** WUC level low trigger mode */ +#define WUC_TYPE_LEVEL_LOW BIT(4) + +/** @} */ + +/** + * @brief A trigger condition on the corresponding input generates + * a wake-up signal to the power management control of EC + * + * @param dev Pointer to the device structure for the driver instance + * @param mask Pin mask of WUC group + */ +void it51xxx_wuc_enable(const struct device *dev, uint8_t mask); + +/** + * @brief A trigger condition on the corresponding input doesn't + * assert the wake-up signal (canceled not pending) + * + * @param dev Pointer to the device structure for the driver instance + * @param mask Pin mask of WUC group + */ +void it51xxx_wuc_disable(const struct device *dev, uint8_t mask); + +/** + * @brief Write-1-clear a trigger condition that occurs on the + * corresponding input + * + * @param dev Pointer to the device structure for the driver instance + * @param mask Pin mask of WUC group + */ +void it51xxx_wuc_clear_status(const struct device *dev, uint8_t mask); + +/** + * @brief Select the trigger edge mode on the corresponding input + * + * @param dev Pointer to the device structure for the driver instance + * @param mask Pin mask of WUC group + * @param flags Select the trigger edge mode + */ +void it51xxx_wuc_set_polarity(const struct device *dev, uint8_t mask, uint32_t flags); + +#endif /* ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_IT51XXX_WUC_H_ */ diff --git a/include/zephyr/dt-bindings/interrupt-controller/ite-it51xxx-intc.h b/include/zephyr/dt-bindings/interrupt-controller/ite-it51xxx-intc.h new file mode 100644 index 00000000000..c6e2c7c8f78 --- /dev/null +++ b/include/zephyr/dt-bindings/interrupt-controller/ite-it51xxx-intc.h @@ -0,0 +1,186 @@ +/* + * Copyright (c) 2025 ITE Corporation. All Rights Reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ITE_INTC_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ITE_INTC_H_ + +#define IRQ_TYPE_NONE 0 +#define IRQ_TYPE_EDGE_RISING 1 +#define IRQ_TYPE_EDGE_FALLING 2 +#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) +#define IRQ_TYPE_LEVEL_HIGH 4 +#define IRQ_TYPE_LEVEL_LOW 8 + +/* IRQ numbers of WUC */ +/* Group 0 of INTC */ +#define IT51XXX_IRQ_WU20 1 +#define IT51XXX_IRQ_KBC_OBE 2 +#define IT51XXX_IRQ_SMB_D 4 +#define IT51XXX_IRQ_WKINTD 5 +#define IT51XXX_IRQ_WU23 6 +/* Group 1 */ +#define IT51XXX_IRQ_SMB_A 9 +#define IT51XXX_IRQ_SMB_B 10 +#define IT51XXX_IRQ_WU26 12 +#define IT51XXX_IRQ_WKINTC 13 +#define IT51XXX_IRQ_WU25 14 +/* Group 2 */ +#define IT51XXX_IRQ_SMB_C 16 +#define IT51XXX_IRQ_WU24 17 +#define IT51XXX_IRQ_WU22 21 +/* Group 3 */ +#define IT51XXX_IRQ_KBC_IBF 24 +#define IT51XXX_IRQ_PMC1_IBF 25 +#define IT51XXX_IRQ_PMC2_IBF 27 +#define IT51XXX_IRQ_TIMER1 30 +#define IT51XXX_IRQ_WU21 31 +/* Group 5 */ +#define IT51XXX_IRQ_WU50 40 +#define IT51XXX_IRQ_WU51 41 +#define IT51XXX_IRQ_WU52 42 +#define IT51XXX_IRQ_WU53 43 +#define IT51XXX_IRQ_WU54 44 +#define IT51XXX_IRQ_WU55 45 +#define IT51XXX_IRQ_WU56 46 +#define IT51XXX_IRQ_WU57 47 +/* Group 6 */ +#define IT51XXX_IRQ_WU60 48 +#define IT51XXX_IRQ_WU61 49 +#define IT51XXX_IRQ_WU62 50 +#define IT51XXX_IRQ_WU63 51 +#define IT51XXX_IRQ_WU64 52 +#define IT51XXX_IRQ_WU65 53 +#define IT51XXX_IRQ_WU66 54 +#define IT51XXX_IRQ_WU67 55 +/* Group 7 */ +#define IT51XXX_IRQ_TIMER2 58 +/* Group 9 */ +#define IT51XXX_IRQ_WU70 72 +#define IT51XXX_IRQ_WU71 73 +#define IT51XXX_IRQ_WU72 74 +#define IT51XXX_IRQ_WU73 75 +#define IT51XXX_IRQ_WU74 76 +#define IT51XXX_IRQ_WU75 77 +#define IT51XXX_IRQ_WU76 78 +#define IT51XXX_IRQ_WU77 79 +/* Group 10 */ +#define IT51XXX_IRQ_WU88 85 +#define IT51XXX_IRQ_WU89 86 +#define IT51XXX_IRQ_WU90 87 +/* Group 11 */ +#define IT51XXX_IRQ_WU80 88 +#define IT51XXX_IRQ_WU81 89 +#define IT51XXX_IRQ_WU82 90 +#define IT51XXX_IRQ_WU83 91 +#define IT51XXX_IRQ_WU84 92 +#define IT51XXX_IRQ_WU85 93 +#define IT51XXX_IRQ_WU86 94 +#define IT51XXX_IRQ_WU87 95 +/* Group 12 */ +#define IT51XXX_IRQ_WU91 96 +#define IT51XXX_IRQ_WU92 97 +#define IT51XXX_IRQ_WU93 98 +#define IT51XXX_IRQ_WU95 100 +#define IT51XXX_IRQ_WU96 101 +#define IT51XXX_IRQ_WU97 102 +#define IT51XXX_IRQ_WU98 103 +/* Group 13 */ +#define IT51XXX_IRQ_WU99 104 +#define IT51XXX_IRQ_WU100 105 +#define IT51XXX_IRQ_WU101 106 +#define IT51XXX_IRQ_WU102 107 +#define IT51XXX_IRQ_WU103 108 +#define IT51XXX_IRQ_WU104 109 +#define IT51XXX_IRQ_WU105 110 +#define IT51XXX_IRQ_WU106 111 +/* Group 14 */ +#define IT51XXX_IRQ_WU107 112 +#define IT51XXX_IRQ_WU108 113 +#define IT51XXX_IRQ_WU109 114 +#define IT51XXX_IRQ_WU110 115 +#define IT51XXX_IRQ_WU111 116 +#define IT51XXX_IRQ_WU112 117 +#define IT51XXX_IRQ_WU113 118 +#define IT51XXX_IRQ_WU114 119 +/* Group 15 */ +#define IT51XXX_IRQ_WU115 120 +#define IT51XXX_IRQ_WU116 121 +#define IT51XXX_IRQ_WU117 122 +#define IT51XXX_IRQ_WU118 123 +#define IT51XXX_IRQ_WU119 124 +#define IT51XXX_IRQ_WU120 125 +#define IT51XXX_IRQ_WU121 126 +#define IT51XXX_IRQ_WU122 127 +/* Group 16 */ +#define IT51XXX_IRQ_WU128 128 +#define IT51XXX_IRQ_WU129 129 +#define IT51XXX_IRQ_WU131 131 +#define IT51XXX_IRQ_WU132 132 +#define IT51XXX_IRQ_WU133 133 +#define IT51XXX_IRQ_WU134 134 +#define IT51XXX_IRQ_WU135 135 +/* Group 17 */ +#define IT51XXX_IRQ_WU136 136 +#define IT51XXX_IRQ_WU137 137 +#define IT51XXX_IRQ_WU138 138 +#define IT51XXX_IRQ_WU139 139 +#define IT51XXX_IRQ_WU140 140 +#define IT51XXX_IRQ_WU141 141 +#define IT51XXX_IRQ_WU142 142 +/* Group 18 */ +#define IT51XXX_IRQ_WU127 148 +#define IT51XXX_IRQ_V_CMP 151 +/* Group 19 */ +#define IT51XXX_IRQ_PECI 152 +#define IT51XXX_IRQ_ESPI 153 +#define IT51XXX_IRQ_ESPI_VW 154 +#define IT51XXX_IRQ_PCH_P80 155 +#define IT51XXX_IRQ_TIMER3 157 +#define IT51XXX_IRQ_PLL_CHANGE 159 +/* Group 20 */ +#define IT51XXX_IRQ_SMB_E 160 +#define IT51XXX_IRQ_SMB_F 161 +#define IT51XXX_IRQ_WU40 163 +#define IT51XXX_IRQ_WU45 166 +/* Group 21 */ +#define IT51XXX_IRQ_WU46 168 +#define IT51XXX_IRQ_WU144 170 +#define IT51XXX_IRQ_WU145 171 +#define IT51XXX_IRQ_WU146 172 +#define IT51XXX_IRQ_WU147 173 +#define IT51XXX_IRQ_TIMER4 175 +/* Group 22 */ +#define IT51XXX_IRQ_WU148 176 +#define IT51XXX_IRQ_WU149 177 +#define IT51XXX_IRQ_WU150 178 +#define IT51XXX_IRQ_WU151 179 +#define IT51XXX_IRQ_I3C_M0 180 +#define IT51XXX_IRQ_I3C_M1 181 +#define IT51XXX_IRQ_I3C_S0 182 +#define IT51XXX_IRQ_I3C_S1 183 +/* Group 25 */ +#define IT51XXX_IRQ_SMB_SC 203 +#define IT51XXX_IRQ_SMB_SB 204 +#define IT51XXX_IRQ_SMB_SA 205 +#define IT51XXX_IRQ_TIMER1_DW 207 +/* Group 26 */ +#define IT51XXX_IRQ_TIMER2_DW 208 +#define IT51XXX_IRQ_TIMER3_DW 209 +#define IT51XXX_IRQ_TIMER4_DW 210 +#define IT51XXX_IRQ_TIMER5_DW 211 +#define IT51XXX_IRQ_TIMER6_DW 212 +#define IT51XXX_IRQ_TIMER7_DW 213 +#define IT51XXX_IRQ_TIMER8_DW 214 +/* Group 27 */ +#define IT51XXX_IRQ_PWM_TACH0 219 +#define IT51XXX_IRQ_PWM_TACH1 220 +#define IT51XXX_IRQ_PWM_TACH2 221 +#define IT51XXX_IRQ_SMB_G 222 +#define IT51XXX_IRQ_SMB_H 223 +/* Group 28 */ +#define IT51XXX_IRQ_SMB_I 224 + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ITE_INTC_H_ */ diff --git a/include/zephyr/dt-bindings/interrupt-controller/ite-it51xxx-wuc.h b/include/zephyr/dt-bindings/interrupt-controller/ite-it51xxx-wuc.h new file mode 100644 index 00000000000..99e2b9708c3 --- /dev/null +++ b/include/zephyr/dt-bindings/interrupt-controller/ite-it51xxx-wuc.h @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2025 ITE Corporation. All Rights Reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_IT51XXX_WUC_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_IT51XXX_WUC_H_ + +/** WUC reserved register of reg property */ +#define IT51XXX_WUC_UNUSED_REG 0 + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_IT51XXX_WUC_H_ */