From 66dceba537305ae2e0b3d5c9a345fa88fcdd1a99 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Patrick=20G=C3=BCnzel?= Date: Tue, 14 Jan 2025 09:18:49 +0100 Subject: [PATCH] driver: adjust res when oversampling MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The SAM0 ADC has an internal register to divide the accumulated results of oversampling the ADC by the amount of samples collected. This value has to be set by the driver and was missing. Signed-off-by: Patrick Günzel --- drivers/adc/adc_sam0.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/adc/adc_sam0.c b/drivers/adc/adc_sam0.c index b36f961de47..bc766b7278f 100644 --- a/drivers/adc/adc_sam0.c +++ b/drivers/adc/adc_sam0.c @@ -177,7 +177,6 @@ static int adc_sam0_channel_setup(const struct device *dev, #endif } - uint32_t inputctrl = 0; switch (channel_cfg->gain) { @@ -255,7 +254,6 @@ static int adc_sam0_channel_setup(const struct device *dev, break; } - return 0; } @@ -325,6 +323,12 @@ static int start_read(const struct device *dev, } adc->AVGCTRL.reg = ADC_AVGCTRL_SAMPLENUM(sequence->oversampling); + if (sequence->oversampling < 4) { + adc->AVGCTRL.reg |= ADC_AVGCTRL_ADJRES(sequence->oversampling); + } else { + adc->AVGCTRL.reg |= ADC_AVGCTRL_ADJRES(4); + } + /* AVGCTRL is not synchronized */ #ifdef CONFIG_SOC_SERIES_SAMD20