drivers: pinctrl: sam: add pinctrl for sama7g5

Support pull up/down, open drain for sam7g5's PIO.

Signed-off-by: Tony Han <tony.han@microchip.com>

drivers/pinctrl/CMakeLists.txt

@@ -20,6 +20,7 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_MSPM0 pinctrl_mspm0.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_RPI_PICO pinctrl_rpi_pico.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_SAM pinctrl_sam.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_SAM0 pinctrl_sam0.c)
+zephyr_library_sources_ifdef(CONFIG_PINCTRL_SAM_PIO4 pinctrl_sam_pio4.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_STM32 pinctrl_stm32.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_NXP_PORT pinctrl_nxp_port.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_MCHP_XEC pinctrl_mchp_xec.c)

drivers/pinctrl/Kconfig.sam

@@ -7,3 +7,11 @@ config PINCTRL_SAM
 	depends on DT_HAS_ATMEL_SAM_PINCTRL_ENABLED
 	help
 	  Atmel pin controller driver is used on SAM and SAM4L SoC series
+
+config PINCTRL_SAM_PIO4
+	bool "Microchip SAM Parallel Input/Output Controller driver"
+	default y
+	depends on DT_HAS_MICROCHIP_SAMA7G5_PINCTRL_ENABLED
+	help
+	  Microchip Parallel Input/Output Controller is used on SAMA5D2 and
+	  SAMA7G5 SoC series

drivers/pinctrl/pinctrl_sam_pio4.c

@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ */
+
+#include <zephyr/drivers/pinctrl.h>
+#include <soc.h>
+
+#define SAM_PIO_NPINS_PER_BANK          32
+#define SAM_PIO_BANK(pin_id)            (pin_id / SAM_PIO_NPINS_PER_BANK)
+#define SAM_PIO_LINE(pin_id)            (pin_id % SAM_PIO_NPINS_PER_BANK)
+#define SAM_PIO_BANK_OFFSET             0x40
+
+#define SAM_GET_PIN_NO(pinmux)          ((pinmux) & 0xff)
+#define SAM_GET_PIN_FUNC(pinmux)        ((pinmux >> 16) & 0xf)
+#define SAM_GET_PIN_IOSET(pinmux)       ((pinmux >> 20) & 0xf)
+
+static pio_registers_t * const pio_reg =
+	(pio_registers_t *)DT_REG_ADDR(DT_NODELABEL(pinctrl));
+
+static void pinctrl_configure_pin(pinctrl_soc_pin_t pin)
+{
+	uint32_t pin_id = SAM_GET_PIN_NO(pin.pin_mux);
+	uint32_t bank = SAM_PIO_BANK(pin_id);
+	uint32_t line = SAM_PIO_LINE(pin_id);
+	uint32_t func = SAM_GET_PIN_FUNC(pin.pin_mux);
+	uint32_t conf = 0;
+
+	pio_reg->PIO_GROUP[bank].PIO_MSKR = 1 << line;
+
+	conf = pio_reg->PIO_GROUP[bank].PIO_CFGR;
+	if (pin.drive_open_drain) {
+		conf |= PIO_CFGR_OPD(PIO_CFGR_OPD_ENABLED_Val);
+	}
+	if (pin.bias_disable) {
+		conf &= ~(PIO_CFGR_PUEN_Msk | PIO_CFGR_PDEN_Msk);
+	}
+	if (pin.bias_pull_down) {
+		conf |= PIO_CFGR_PDEN(PIO_CFGR_PDEN_ENABLED_Val);
+		conf &= ~PIO_CFGR_PUEN_Msk;
+	}
+	if (pin.bias_pull_up) {
+		conf |= PIO_CFGR_PUEN(PIO_CFGR_PUEN_ENABLED_Val);
+		conf &= ~PIO_CFGR_PDEN_Msk;
+	}
+	conf &= ~PIO_CFGR_FUNC_Msk;
+	conf |= PIO_CFGR_FUNC(func);
+
+	pio_reg->PIO_GROUP[bank].PIO_CFGR = conf;
+}
+
+int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
+			   uintptr_t reg)
+{
+	ARG_UNUSED(reg);
+
+	for (uint8_t i = 0U; i < pin_cnt; i++) {
+		pinctrl_configure_pin(*pins++);
+	}
+
+	return 0;
+}

dts/bindings/pinctrl/microchip,sama7g5-pinctrl.yaml

@@ -0,0 +1,38 @@
+# Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+description: |
+  Microchip SAMA7G5 Pinctrl container node
+
+compatible: "microchip,sama7g5-pinctrl"
+
+include: base.yaml
+
+properties:
+  reg:
+    required: true
+
+child-binding:
+  description: |
+    Each child node defines the configuration for a particular state.
+  child-binding:
+    description: |
+      The grandchild nodes group pins that share the same pin configuration.
+
+    include:
+      - name: pincfg-node.yaml
+        property-allowlist:
+          - bias-disable
+          - bias-pull-down
+          - bias-pull-up
+          - drive-open-drain
+
+    properties:
+      pinmux:
+        required: true
+        type: array
+        description: |
+          An array of pins sharing the same group properties. The pins should
+          be defined using pre-defined macros used by the SoC series.