diff --git a/soc/soc_legacy/riscv/virt/CMakeLists.txt b/soc/riscv/qemu_virt_riscv/CMakeLists.txt
similarity index 65%
rename from soc/soc_legacy/riscv/virt/CMakeLists.txt
rename to soc/riscv/qemu_virt_riscv/CMakeLists.txt
index 6a1826b29f9..ce57a74e239 100644
--- a/soc/soc_legacy/riscv/virt/CMakeLists.txt
+++ b/soc/riscv/qemu_virt_riscv/CMakeLists.txt
@@ -1,5 +1,5 @@
+# Copyright (c) 2024 Antmicro <www.antmicro.com>
 # SPDX-License-Identifier: Apache-2.0
 
-zephyr_sources(soc.c)
-
 set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "")
+add_subdirectory(common)
diff --git a/soc/soc_legacy/riscv/virt/Kconfig.soc b/soc/riscv/qemu_virt_riscv/Kconfig
similarity index 57%
rename from soc/soc_legacy/riscv/virt/Kconfig.soc
rename to soc/riscv/qemu_virt_riscv/Kconfig
index 59e553a9d7b..1c3382371bb 100644
--- a/soc/soc_legacy/riscv/virt/Kconfig.soc
+++ b/soc/riscv/qemu_virt_riscv/Kconfig
@@ -1,8 +1,7 @@
-# Copyright (c) 2020 Cobham Gaisler AB
+# Copyright (c) 2024 Antmicro <www.antmicro.com>
 # SPDX-License-Identifier: Apache-2.0
 
-config SOC_RISCV_VIRT
-	bool "QEMU RISC-V VirtIO Board"
+config SOC_FAMILY_QEMU_VIRT_RISCV
 	select ATOMIC_OPERATIONS_BUILTIN
 	select INCLUDE_RESET_VECTOR
 	select RISCV_ISA_EXT_M
@@ -11,3 +10,9 @@ config SOC_RISCV_VIRT
 	select RISCV
 	select RISCV_PRIVILEGED
 	select RISCV_HAS_PLIC
+
+if SOC_FAMILY_QEMU_VIRT_RISCV
+
+rsource "*/Kconfig"
+
+endif # SOC_FAMILY_QEMU_VIRT_RISCV
diff --git a/soc/soc_legacy/riscv/virt/Kconfig.defconfig b/soc/riscv/qemu_virt_riscv/Kconfig.defconfig
similarity index 77%
rename from soc/soc_legacy/riscv/virt/Kconfig.defconfig
rename to soc/riscv/qemu_virt_riscv/Kconfig.defconfig
index bed5ff8bec7..4eb51b6d889 100644
--- a/soc/soc_legacy/riscv/virt/Kconfig.defconfig
+++ b/soc/riscv/qemu_virt_riscv/Kconfig.defconfig
@@ -1,10 +1,8 @@
 # Copyright (c) 2020 Cobham Gaisler AB
+# Copyright (c) 2024 Antmicro <www.antmicro.com>
 # SPDX-License-Identifier: Apache-2.0
 
-if SOC_RISCV_VIRT
-
-config SOC
-	default "virt"
+if SOC_FAMILY_QEMU_VIRT_RISCV
 
 config SYS_CLOCK_HW_CYCLES_PER_SEC
 	default 10000000
@@ -30,4 +28,4 @@ config NUM_IRQS
 config PMP_SLOTS
 	default 16
 
-endif
+endif # SOC_FAMILY_QEMU_VIRT_RISCV
diff --git a/soc/riscv/qemu_virt_riscv/Kconfig.soc b/soc/riscv/qemu_virt_riscv/Kconfig.soc
new file mode 100644
index 00000000000..ba3a1bd5961
--- /dev/null
+++ b/soc/riscv/qemu_virt_riscv/Kconfig.soc
@@ -0,0 +1,10 @@
+# Copyright (c) 2024 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_FAMILY_QEMU_VIRT_RISCV
+	bool
+
+config SOC_FAMILY
+	default "qemu_virt_riscv" if SOC_FAMILY_QEMU_VIRT_RISCV
+
+rsource "*/Kconfig.soc"
diff --git a/soc/riscv/qemu_virt_riscv/common/CMakeLists.txt b/soc/riscv/qemu_virt_riscv/common/CMakeLists.txt
new file mode 100644
index 00000000000..77a7ba35d26
--- /dev/null
+++ b/soc/riscv/qemu_virt_riscv/common/CMakeLists.txt
@@ -0,0 +1,4 @@
+# Copyright (c) 2024 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_sources(soc.c)
diff --git a/soc/soc_legacy/riscv/virt/soc.c b/soc/riscv/qemu_virt_riscv/common/soc.c
similarity index 100%
rename from soc/soc_legacy/riscv/virt/soc.c
rename to soc/riscv/qemu_virt_riscv/common/soc.c
diff --git a/soc/riscv/qemu_virt_riscv/qemu_virt_riscv32/Kconfig b/soc/riscv/qemu_virt_riscv/qemu_virt_riscv32/Kconfig
new file mode 100644
index 00000000000..ff49d3fe3ab
--- /dev/null
+++ b/soc/riscv/qemu_virt_riscv/qemu_virt_riscv32/Kconfig
@@ -0,0 +1,8 @@
+# Copyright (c) 2024 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_QEMU_VIRT_RISCV32
+	select CPU_HAS_FPU
+	select RISCV_ISA_RV32I
+	select RISCV_ISA_EXT_ZICSR
+	select RISCV_ISA_EXT_ZIFENCEI
diff --git a/soc/riscv/qemu_virt_riscv/qemu_virt_riscv32/Kconfig.soc b/soc/riscv/qemu_virt_riscv/qemu_virt_riscv32/Kconfig.soc
new file mode 100644
index 00000000000..4b1ee59adc1
--- /dev/null
+++ b/soc/riscv/qemu_virt_riscv/qemu_virt_riscv32/Kconfig.soc
@@ -0,0 +1,9 @@
+# Copyright (c) 2024 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_QEMU_VIRT_RISCV32
+	bool
+	select SOC_FAMILY_QEMU_VIRT_RISCV
+
+config SOC
+	default "qemu_virt_riscv32" if SOC_QEMU_VIRT_RISCV32
diff --git a/soc/riscv/qemu_virt_riscv/qemu_virt_riscv32e/Kconfig b/soc/riscv/qemu_virt_riscv/qemu_virt_riscv32e/Kconfig
new file mode 100644
index 00000000000..9ad39ce22ad
--- /dev/null
+++ b/soc/riscv/qemu_virt_riscv/qemu_virt_riscv32e/Kconfig
@@ -0,0 +1,8 @@
+# Copyright (c) 2020 Cobham Gaisler AB
+# Copyright (c) 2024 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_QEMU_VIRT_RISCV32E
+	select RISCV_ISA_RV32E
+	select RISCV_ISA_EXT_ZICSR
+	select RISCV_ISA_EXT_ZIFENCEI
diff --git a/soc/riscv/qemu_virt_riscv/qemu_virt_riscv32e/Kconfig.soc b/soc/riscv/qemu_virt_riscv/qemu_virt_riscv32e/Kconfig.soc
new file mode 100644
index 00000000000..38b51ee58ff
--- /dev/null
+++ b/soc/riscv/qemu_virt_riscv/qemu_virt_riscv32e/Kconfig.soc
@@ -0,0 +1,9 @@
+# Copyright (c) 2024 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_QEMU_VIRT_RISCV32E
+	bool
+	select SOC_FAMILY_QEMU_VIRT_RISCV
+
+config SOC
+	default "qemu_virt_riscv32e" if SOC_QEMU_VIRT_RISCV32E
diff --git a/soc/riscv/qemu_virt_riscv/qemu_virt_riscv64/Kconfig b/soc/riscv/qemu_virt_riscv/qemu_virt_riscv64/Kconfig
new file mode 100644
index 00000000000..f8560c607f0
--- /dev/null
+++ b/soc/riscv/qemu_virt_riscv/qemu_virt_riscv64/Kconfig
@@ -0,0 +1,9 @@
+# Copyright (c) 2024 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_QEMU_VIRT_RISCV64
+	select 64BIT
+	select CPU_HAS_FPU_DOUBLE_PRECISION
+	select RISCV_ISA_RV64I
+	select RISCV_ISA_EXT_ZICSR
+	select RISCV_ISA_EXT_ZIFENCEI
diff --git a/soc/riscv/qemu_virt_riscv/qemu_virt_riscv64/Kconfig.soc b/soc/riscv/qemu_virt_riscv/qemu_virt_riscv64/Kconfig.soc
new file mode 100644
index 00000000000..cfcf51103de
--- /dev/null
+++ b/soc/riscv/qemu_virt_riscv/qemu_virt_riscv64/Kconfig.soc
@@ -0,0 +1,9 @@
+# Copyright (c) 2024 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_QEMU_VIRT_RISCV64
+	bool
+	select SOC_FAMILY_QEMU_VIRT_RISCV
+
+config SOC
+	default "qemu_virt_riscv64" if SOC_QEMU_VIRT_RISCV64
diff --git a/soc/riscv/qemu_virt_riscv/soc.yml b/soc/riscv/qemu_virt_riscv/soc.yml
new file mode 100644
index 00000000000..746051f76a9
--- /dev/null
+++ b/soc/riscv/qemu_virt_riscv/soc.yml
@@ -0,0 +1,6 @@
+family:
+- name: qemu_virt_riscv
+  socs:
+  - name: qemu_virt_riscv32
+  - name: qemu_virt_riscv32e
+  - name: qemu_virt_riscv64