dts: arm: st: Refactor DTSI files to use macro

Replaces raw hex codes by using STM32_CLOCK macro

Signed-off-by: Hubert Guan <hguan@ucsb.edu>

dts/arm/st/c0/stm32c0.dtsi

@@ -84,7 +84,7 @@
 			compatible = "st,stm32-flash-controller";
 			reg = <0x40022000 0x400>;
 			interrupts = <3 0>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000100>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 8U)>;
 
 			#address-cells = <1>;
 			#size-cells = <1>;
@@ -133,7 +133,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x50000000 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000001>;
+				clocks = <&rcc STM32_CLOCK(IOP, 0U)>;
 			};
 
 			gpiob: gpio@50000400 {
@@ -141,7 +141,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x50000400 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000002>;
+				clocks = <&rcc STM32_CLOCK(IOP, 1U)>;
 			};
 
 			gpioc: gpio@50000800 {
@@ -149,7 +149,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x50000800 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000004>;
+				clocks = <&rcc STM32_CLOCK(IOP, 2U)>;
 			};
 
 			gpiof: gpio@50001400 {
@@ -157,7 +157,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x50001400 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000020>;
+				clocks = <&rcc STM32_CLOCK(IOP, 5U)>;
 			};
 		};
 
@@ -165,7 +165,7 @@
 			compatible = "st,stm32-rtc";
 			reg = <0x40002800 0x400>;
 			interrupts = <2 0>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000400>;
+			clocks = <&rcc STM32_CLOCK(APB1, 10U)>;
 			prescaler = <32768>;
 			alarms-count = <1>;
 			alrm-exti-line = <19>;
@@ -175,7 +175,7 @@
 		wwdg: watchdog@40002c00 {
 			compatible = "st,stm32-window-watchdog";
 			reg = <0x40002C00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
+			clocks = <&rcc STM32_CLOCK(APB1, 11U)>;
 			interrupts = <0 2>;
 			status = "disabled";
 		};
@@ -189,7 +189,7 @@
 		usart1: serial@40013800 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40013800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00004000>;
+			clocks = <&rcc STM32_CLOCK(APB1_2, 14U)>;
 			resets = <&rctl STM32_RESET(APB1H, 14U)>;
 			interrupts = <27 0>;
 			status = "disabled";
@@ -198,7 +198,7 @@
 		usart2: serial@40004400 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40004400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 17U)>;
 			resets = <&rctl STM32_RESET(APB1L, 17U)>;
 			interrupts = <28 0>;
 			status = "disabled";
@@ -207,7 +207,7 @@
 		timers1: timers@40012c00 {
 			compatible = "st,stm32-timers";
 			reg = <0x40012C00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000800>;
+			clocks = <&rcc STM32_CLOCK(APB1_2, 11U)>;
 			resets = <&rctl STM32_RESET(APB1H, 11U)>;
 			interrupts = <13 0>, <14 0>;
 			interrupt-names = "brk_up_trg_com", "cc";
@@ -224,7 +224,7 @@
 		timers3: timers@40000400 {
 			compatible = "st,stm32-timers";
 			reg = <0x40000400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
+			clocks = <&rcc STM32_CLOCK(APB1, 1U)>;
 			resets = <&rctl STM32_RESET(APB1L, 1U)>;
 			interrupts = <16 0>;
 			interrupt-names = "global";
@@ -241,7 +241,7 @@
 		timers14: timers@40002000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40002000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00008000>;
+			clocks = <&rcc STM32_CLOCK(APB1_2, 15U)>;
 			resets = <&rctl STM32_RESET(APB1H, 15U)>;
 			interrupts = <19 0>;
 			interrupt-names = "global";
@@ -258,7 +258,7 @@
 		timers16: timers@40014400 {
 			compatible = "st,stm32-timers";
 			reg = <0x40014400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00020000>;
+			clocks = <&rcc STM32_CLOCK(APB1_2, 17U)>;
 			resets = <&rctl STM32_RESET(APB1H, 17U)>;
 			interrupts = <21 0>;
 			interrupt-names = "global";
@@ -275,7 +275,7 @@
 		timers17: timers@40014800 {
 			compatible = "st,stm32-timers";
 			reg = <0x40014800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00040000>;
+			clocks = <&rcc STM32_CLOCK(APB1_2, 18U)>;
 			resets = <&rctl STM32_RESET(APB1H, 18U)>;
 			interrupts = <22 0>;
 			interrupt-names = "global";
@@ -295,7 +295,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40005400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 21U)>;
 			interrupts = <23 0>;
 			interrupt-names = "combined";
 			status = "disabled";
@@ -304,7 +304,7 @@
 		adc1: adc@40012400 {
 			compatible = "st,stm32-adc";
 			reg = <0x40012400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00100000>;
+			clocks = <&rcc STM32_CLOCK(APB1_2, 20U)>;
 			interrupts = <12 0>;
 			status = "disabled";
 			#io-channel-cells = <1>;
@@ -322,7 +322,7 @@
 			#dma-cells = <3>;
 			reg = <0x40020000 0x400>;
 			interrupts = <9 0 10 0 10 0>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000001>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 0U)>;
 			dma-requests = <3>;
 			dma-offset = <0>;
 			status = "disabled";

dts/arm/st/c0/stm32c031.dtsi

@@ -16,7 +16,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x50000c00 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000008>;
+				clocks = <&rcc STM32_CLOCK(IOP, 3U)>;
 			};
 		};
 	};

dts/arm/st/f0/stm32f0.dtsi

@@ -86,7 +86,7 @@
 			compatible = "st,stm32-flash-controller", "st,stm32f1-flash-controller";
 			reg = <0x40022000 0x400>;
 			interrupts = <3 0>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000010>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 4U)>;
 
 			#address-cells = <1>;
 			#size-cells = <1>;
@@ -134,7 +134,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x48000000 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00020000>;
+				clocks = <&rcc STM32_CLOCK(AHB1, 17U)>;
 			};
 
 			gpiob: gpio@48000400 {
@@ -142,7 +142,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x48000400 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00040000>;
+				clocks = <&rcc STM32_CLOCK(AHB1, 18U)>;
 			};
 
 			gpioc: gpio@48000800 {
@@ -150,7 +150,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x48000800 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00080000>;
+				clocks = <&rcc STM32_CLOCK(AHB1, 19U)>;
 			};
 
 			gpiod: gpio@48000c00 {
@@ -158,7 +158,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x48000c00 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00100000>;
+				clocks = <&rcc STM32_CLOCK(AHB1, 20U)>;
 			};
 
 			gpiof: gpio@48001400 {
@@ -166,14 +166,14 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x48001400 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00400000>;
+				clocks = <&rcc STM32_CLOCK(AHB1, 22U)>;
 			};
 		};
 
 		usart1: serial@40013800 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40013800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 14U)>;
 			resets = <&rctl STM32_RESET(APB2, 14U)>;
 			interrupts = <27 0>;
 			status = "disabled";
@@ -185,7 +185,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40005400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>,
+			clocks = <&rcc STM32_CLOCK(APB1, 21U)>,
 				 /* I2C1 clock source should always be defined,
 				  * even for the default value
 				  */
@@ -200,7 +200,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40013000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 12U)>;
 			interrupts = <25 3>;
 			status = "disabled";
 		};
@@ -208,7 +208,7 @@
 		rtc: rtc@40002800 {
 			compatible = "st,stm32-rtc";
 			reg = <0x40002800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 28U)>;
 			interrupts = <2 0>;
 			prescaler = <32768>;
 			alarms-count = <1>;
@@ -225,7 +225,7 @@
 		wwdg: watchdog@40002c00 {
 			compatible = "st,stm32-window-watchdog";
 			reg = <0x40002C00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
+			clocks = <&rcc STM32_CLOCK(APB1, 11U)>;
 			interrupts = <0 2>;
 			status = "disabled";
 		};
@@ -233,7 +233,7 @@
 		timers1: timers@40012c00 {
 			compatible = "st,stm32-timers";
 			reg = <0x40012c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>;
+			clocks = <&rcc STM32_CLOCK(APB2, 11U)>;
 			resets = <&rctl STM32_RESET(APB2, 11U)>;
 			interrupts = <13 0>, <14 0>;
 			interrupt-names = "brk_up_trg_com", "cc";
@@ -250,7 +250,7 @@
 		timers3: timers@40000400 {
 			compatible = "st,stm32-timers";
 			reg = <0x40000400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
+			clocks = <&rcc STM32_CLOCK(APB1, 1U)>;
 			resets = <&rctl STM32_RESET(APB1, 1U)>;
 			interrupts = <16 0>;
 			interrupt-names = "global";
@@ -272,7 +272,7 @@
 		timers14: timers@40002000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40002000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000100>;
+			clocks = <&rcc STM32_CLOCK(APB1, 8U)>;
 			resets = <&rctl STM32_RESET(APB1, 8U)>;
 			interrupts = <19 0>;
 			interrupt-names = "global";
@@ -294,7 +294,7 @@
 		timers16: timers@40014400 {
 			compatible = "st,stm32-timers";
 			reg = <0x40014400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00020000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 17U)>;
 			resets = <&rctl STM32_RESET(APB2, 17U)>;
 			interrupts = <21 0>;
 			interrupt-names = "global";
@@ -316,7 +316,7 @@
 		timers17: timers@40014800 {
 			compatible = "st,stm32-timers";
 			reg = <0x40014800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00040000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 18U)>;
 			resets = <&rctl STM32_RESET(APB2, 18U)>;
 			interrupts = <22 0>;
 			interrupt-names = "global";
@@ -338,7 +338,7 @@
 		adc1: adc@40012400 {
 			compatible = "st,stm32-adc";
 			reg = <0x40012400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000200>;
+			clocks = <&rcc STM32_CLOCK(APB2, 9U)>;
 			interrupts = <12 0>;
 			status = "disabled";
 			#io-channel-cells = <1>;
@@ -355,7 +355,7 @@
 			compatible = "st,stm32-dma-v2bis";
 			#dma-cells = <2>;
 			reg = <0x40020000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 0U)>;
 			interrupts = <9 0 10 0 10 0 11 0 11 0>;
 			status = "disabled";
 		};

dts/arm/st/f0/stm32f030X8.dtsi

@@ -21,7 +21,7 @@
 		usart2: serial@40004400 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40004400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 17U)>;
 			resets = <&rctl STM32_RESET(APB1, 17U)>;
 			interrupts = <28 0>;
 			status = "disabled";
@@ -33,7 +33,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40005800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
 			interrupts = <24 0>;
 			interrupt-names = "combined";
 			status = "disabled";
@@ -44,7 +44,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40003800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
 			interrupts = <26 3>;
 			status = "disabled";
 		};
@@ -52,7 +52,7 @@
 		timers6: timers@40001000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40001000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
+			clocks = <&rcc STM32_CLOCK(APB1, 4U)>;
 			resets = <&rctl STM32_RESET(APB1, 4U)>;
 			interrupts = <17 0>;
 			interrupt-names = "global";
@@ -63,7 +63,7 @@
 		timers15: timers@40014000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40014000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00010000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 16U)>;
 			resets = <&rctl STM32_RESET(APB2, 16U)>;
 			interrupts = <20 0>;
 			interrupt-names = "global";

dts/arm/st/f0/stm32f030Xc.dtsi

@@ -29,7 +29,7 @@
 		usart3: serial@40004800 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40004800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
 			resets = <&rctl STM32_RESET(APB1, 18U)>;
 			interrupts = <29 0>;
 			status = "disabled";
@@ -38,7 +38,7 @@
 		usart4: serial@40004c00 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40004c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
 			resets = <&rctl STM32_RESET(APB1, 19U)>;
 			interrupts = <29 0>;
 			status = "disabled";
@@ -47,7 +47,7 @@
 		usart5: serial@40005000 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40005000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
 			resets = <&rctl STM32_RESET(APB1, 20U)>;
 			interrupts = <29 0>;
 			status = "disabled";
@@ -56,7 +56,7 @@
 		usart6: serial@40011400 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40011400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
+			clocks = <&rcc STM32_CLOCK(APB2, 5U)>;
 			resets = <&rctl STM32_RESET(APB2, 5U)>;
 			interrupts = <29 0>;
 			status = "disabled";
@@ -65,7 +65,7 @@
 		timers7: timers@40001400 {
 			compatible = "st,stm32-timers";
 			reg = <0x40001400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
+			clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
 			resets = <&rctl STM32_RESET(APB1, 5U)>;
 			interrupts = <18 0>;
 			interrupt-names = "global";

dts/arm/st/f0/stm32f031.dtsi

@@ -13,7 +13,7 @@
 		timers2: timers@40000000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40000000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
+			clocks = <&rcc STM32_CLOCK(APB1, 0U)>;
 			resets = <&rctl STM32_RESET(APB1, 0U)>;
 			interrupts = <15 0>;
 			interrupt-names = "global";

dts/arm/st/f0/stm32f042.dtsi

@@ -24,7 +24,7 @@
 		usart2: serial@40004400 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40004400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 17U)>;
 			resets = <&rctl STM32_RESET(APB1, 17U)>;
 			interrupts = <28 0>;
 			status = "disabled";
@@ -35,7 +35,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40003800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
 			interrupts = <26 3>;
 			status = "disabled";
 		};
@@ -44,14 +44,14 @@
 			compatible = "st,stm32-bxcan";
 			reg = <0x40006400 0x400>;
 			interrupts = <30 0>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 25U)>;
 			status = "disabled";
 		};
 
 		timers15: timers@40014000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40014000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00010000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 16U)>;
 			resets = <&rctl STM32_RESET(APB2, 16U)>;
 			interrupts = <20 0>;
 			interrupt-names = "global";
@@ -73,7 +73,7 @@
 			num-bidir-endpoints = <8>;
 			ram-size = <1024>;
 			phys = <&usb_fs_phy>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>,
+			clocks = <&rcc STM32_CLOCK(APB1, 23U)>,
 				 <&rcc STM32_SRC_PLLCLK USB_SEL(1)>;
 			status = "disabled";
 		};

dts/arm/st/f0/stm32f051.dtsi

@@ -13,7 +13,7 @@
 		usart2: serial@40004400 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40004400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 17U)>;
 			resets = <&rctl STM32_RESET(APB1, 17U)>;
 			interrupts = <28 0>;
 			status = "disabled";
@@ -25,7 +25,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40005800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
 			interrupts = <24 0>;
 			interrupt-names = "combined";
 			status = "disabled";
@@ -36,7 +36,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40003800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
 			interrupts = <26 3>;
 			status = "disabled";
 		};
@@ -44,7 +44,7 @@
 		timers6: timers@40001000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40001000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
+			clocks = <&rcc STM32_CLOCK(APB1, 4U)>;
 			resets = <&rctl STM32_RESET(APB1, 4U)>;
 			interrupts = <17 0>;
 			interrupt-names = "global";
@@ -55,7 +55,7 @@
 		timers15: timers@40014000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40014000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00010000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 16U)>;
 			resets = <&rctl STM32_RESET(APB2, 16U)>;
 			interrupts = <20 0>;
 			interrupt-names = "global";
@@ -72,7 +72,7 @@
 		dac1: dac@40007400 {
 			compatible = "st,stm32-dac";
 			reg = <0x40007400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 29U)>;
 			status = "disabled";
 			#io-channel-cells = <1>;
 		};

dts/arm/st/f0/stm32f070.dtsi

@@ -13,7 +13,7 @@
 		usart2: serial@40004400 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40004400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 17U)>;
 			resets = <&rctl STM32_RESET(APB1, 17U)>;
 			interrupts = <28 0>;
 			status = "disabled";
@@ -22,7 +22,7 @@
 		timers15: timers@40014000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40014000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00010000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 16U)>;
 			resets = <&rctl STM32_RESET(APB2, 16U)>;
 			interrupts = <20 0>;
 			interrupt-names = "global";
@@ -44,7 +44,7 @@
 			num-bidir-endpoints = <8>;
 			ram-size = <1024>;
 			phys = <&usb_fs_phy>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>,
+			clocks = <&rcc STM32_CLOCK(APB1, 23U)>,
 				 <&rcc STM32_SRC_PLLCLK USB_SEL(1)>;
 			status = "disabled";
 		};

dts/arm/st/f0/stm32f070Xb.dtsi

@@ -28,7 +28,7 @@
 		usart3: serial@40004800 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40004800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
 			resets = <&rctl STM32_RESET(APB1, 18U)>;
 			interrupts = <29 0>;
 			status = "disabled";
@@ -37,7 +37,7 @@
 		usart4: serial@40004c00 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40004c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
 			resets = <&rctl STM32_RESET(APB1, 19U)>;
 			interrupts = <29 0>;
 			status = "disabled";
@@ -49,7 +49,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40005800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
 			interrupts = <24 0>;
 			interrupt-names = "combined";
 			status = "disabled";
@@ -60,7 +60,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40003800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
 			interrupts = <26 3>;
 			status = "disabled";
 		};
@@ -68,7 +68,7 @@
 		timers6: timers@40001000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40001000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
+			clocks = <&rcc STM32_CLOCK(APB1, 4U)>;
 			resets = <&rctl STM32_RESET(APB1, 4U)>;
 			interrupts = <17 0>;
 			interrupt-names = "global";
@@ -79,7 +79,7 @@
 		timers7: timers@40001400 {
 			compatible = "st,stm32-timers";
 			reg = <0x40001400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
+			clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
 			resets = <&rctl STM32_RESET(APB1, 5U)>;
 			interrupts = <18 0>;
 			interrupt-names = "global";

dts/arm/st/f0/stm32f071.dtsi

@@ -31,7 +31,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x48001000 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00200000>;
+				clocks = <&rcc STM32_CLOCK(AHB1, 21U)>;
 			};
 		};
 
@@ -44,7 +44,7 @@
 		usart3: serial@40004800 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40004800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
 			resets = <&rctl STM32_RESET(APB1, 18U)>;
 			interrupts = <29 0>;
 			status = "disabled";
@@ -53,7 +53,7 @@
 		usart4: serial@40004c00 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40004c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
 			resets = <&rctl STM32_RESET(APB1, 19U)>;
 			interrupts = <29 0>;
 			status = "disabled";
@@ -62,7 +62,7 @@
 		timers7: timers@40001400 {
 			compatible = "st,stm32-timers";
 			reg = <0x40001400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
+			clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
 			resets = <&rctl STM32_RESET(APB1, 5U)>;
 			interrupts = <18 0>;
 			interrupt-names = "global";

dts/arm/st/f0/stm32f072.dtsi

@@ -14,7 +14,7 @@
 			compatible = "st,stm32-bxcan";
 			reg = <0x40006400 0x400>;
 			interrupts = <30 0>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 25U)>;
 			status = "disabled";
 		};
 
@@ -26,7 +26,7 @@
 			num-bidir-endpoints = <8>;
 			ram-size = <1024>;
 			phys = <&usb_fs_phy>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>,
+			clocks = <&rcc STM32_CLOCK(APB1, 23U)>,
 				 <&rcc STM32_SRC_PLLCLK USB_SEL(1)>;
 			status = "disabled";
 		};

dts/arm/st/f0/stm32f091.dtsi

@@ -19,7 +19,7 @@
 		usart5: serial@40005000 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40005000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
 			resets = <&rctl STM32_RESET(APB1, 20U)>;
 			interrupts = <29 0>;
 			status = "disabled";
@@ -28,7 +28,7 @@
 		usart6: serial@40011400 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40011400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
+			clocks = <&rcc STM32_CLOCK(APB2, 5U)>;
 			resets = <&rctl STM32_RESET(APB2, 5U)>;
 			interrupts = <29 0>;
 			status = "disabled";
@@ -37,7 +37,7 @@
 		usart7: serial@40011800 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40011800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000040>;
+			clocks = <&rcc STM32_CLOCK(APB2, 6U)>;
 			resets = <&rctl STM32_RESET(APB2, 6U)>;
 			interrupts = <29 0>;
 			status = "disabled";
@@ -46,7 +46,7 @@
 		usart8: serial@40011c00 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40011c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000080>;
+			clocks = <&rcc STM32_CLOCK(APB2, 7U)>;
 			resets = <&rctl STM32_RESET(APB2, 7U)>;
 			interrupts = <29 0>;
 			status = "disabled";
@@ -56,7 +56,7 @@
 			compatible = "st,stm32-bxcan";
 			reg = <0x40006400 0x400>;
 			interrupts = <30 0>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 25U)>;
 			status = "disabled";
 		};
 
@@ -65,7 +65,7 @@
 			#dma-cells = <2>;
 			reg = <0x40020400 0x400>;
 			interrupts = <10 0 10 0 11 0 11 0 11 0>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 1U)>;
 			status = "disabled";
 		};
 	};

dts/arm/st/f1/stm32f1.dtsi

@@ -85,7 +85,7 @@
 			compatible = "st,stm32-flash-controller", "st,stm32f1-flash-controller";
 			reg = <0x40022000 0x400>;
 			interrupts = <3 0>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000010>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 4U)>;
 
 			#address-cells = <1>;
 			#size-cells = <1>;
@@ -136,7 +136,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x40010800 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000004>;
+				clocks = <&rcc STM32_CLOCK(APB2, 2U)>;
 			};
 
 			gpiob: gpio@40010c00 {
@@ -144,7 +144,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x40010c00 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000008>;
+				clocks = <&rcc STM32_CLOCK(APB2, 3U)>;
 			};
 
 			gpioc: gpio@40011000 {
@@ -152,7 +152,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x40011000 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000010>;
+				clocks = <&rcc STM32_CLOCK(APB2, 4U)>;
 			};
 
 			gpiod: gpio@40011400 {
@@ -160,7 +160,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x40011400 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
+				clocks = <&rcc STM32_CLOCK(APB2, 5U)>;
 			};
 
 			gpioe: gpio@40011800 {
@@ -168,14 +168,14 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x40011800 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000040>;
+				clocks = <&rcc STM32_CLOCK(APB2, 6U)>;
 			};
 		};
 
 		usart1: serial@40013800 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40013800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 14U)>;
 			resets = <&rctl STM32_RESET(APB2, 14U)>;
 			interrupts = <37 0>;
 			status = "disabled";
@@ -184,7 +184,7 @@
 		usart2: serial@40004400 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40004400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 17U)>;
 			resets = <&rctl STM32_RESET(APB1, 17U)>;
 			interrupts = <38 0>;
 			status = "disabled";
@@ -193,7 +193,7 @@
 		usart3: serial@40004800 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40004800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
 			resets = <&rctl STM32_RESET(APB1, 18U)>;
 			interrupts = <39 0>;
 			status = "disabled";
@@ -205,7 +205,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40005400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 21U)>;
 			interrupts = <31 0>, <32 0>;
 			interrupt-names = "event", "error";
 			status = "disabled";
@@ -217,7 +217,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40005800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
 			interrupts = <33 0>, <34 0>;
 			interrupt-names = "event", "error";
 			status = "disabled";
@@ -228,7 +228,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40013000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 12U)>;
 			interrupts = <35 5>;
 			status = "disabled";
 		};
@@ -242,7 +242,7 @@
 		wwdg: watchdog@40002c00 {
 			compatible = "st,stm32-window-watchdog";
 			reg = <0x40002C00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
+			clocks = <&rcc STM32_CLOCK(APB1, 11U)>;
 			interrupts = <0 7>;
 			status = "disabled";
 		};
@@ -250,7 +250,7 @@
 		timers1: timers@40012c00 {
 			compatible = "st,stm32-timers";
 			reg = <0x40012c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>;
+			clocks = <&rcc STM32_CLOCK(APB2, 11U)>;
 			resets = <&rctl STM32_RESET(APB2, 11U)>;
 			interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
 			interrupt-names = "brk", "up", "trgcom", "cc";
@@ -267,7 +267,7 @@
 		timers2: timers@40000000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40000000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
+			clocks = <&rcc STM32_CLOCK(APB1, 0U)>;
 			resets = <&rctl STM32_RESET(APB1, 0U)>;
 			interrupts = <28 0>;
 			interrupt-names = "global";
@@ -289,7 +289,7 @@
 		timers3: timers@40000400 {
 			compatible = "st,stm32-timers";
 			reg = <0x40000400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
+			clocks = <&rcc STM32_CLOCK(APB1, 1U)>;
 			resets = <&rctl STM32_RESET(APB1, 1U)>;
 			interrupts = <29 0>;
 			interrupt-names = "global";
@@ -311,7 +311,7 @@
 		timers4: timers@40000800 {
 			compatible = "st,stm32-timers";
 			reg = <0x40000800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
+			clocks = <&rcc STM32_CLOCK(APB1, 2U)>;
 			resets = <&rctl STM32_RESET(APB1, 2U)>;
 			interrupts = <30 0>;
 			interrupt-names = "global";
@@ -334,7 +334,7 @@
 			compatible = "st,stm32-rtc";
 			reg = <0x40002800 0x400>;
 			interrupts = <41 0>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 28U)>;
 			prescaler = <32768>;
 			status = "disabled";
 		};
@@ -342,7 +342,7 @@
 		adc1: adc@40012400 {
 			compatible = "st,stm32f1-adc", "st,stm32-adc";
 			reg = <0x40012400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000200>;
+			clocks = <&rcc STM32_CLOCK(APB2, 9U)>;
 			interrupts = <18 0>;
 			status = "disabled";
 			#io-channel-cells = <1>;
@@ -355,7 +355,7 @@
 			compatible = "st,stm32-dma-v2bis";
 			#dma-cells = <2>;
 			reg = <0x40020000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 0U)>;
 			interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0>;
 			status = "disabled";
 		};

dts/arm/st/f1/stm32f100Xb.dtsi

@@ -39,7 +39,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40003800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
 			interrupts = <36 5>;
 			status = "disabled";
 		};
@@ -47,7 +47,7 @@
 		dac1: dac@40007400 {
 			compatible = "st,stm32-dac";
 			reg = <0x40007400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 29U)>;
 			status = "disabled";
 			#io-channel-cells = <1>;
 		};

dts/arm/st/f1/stm32f100Xe.dtsi

@@ -26,7 +26,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40003c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
 			interrupts = <51 5>;
 			status = "disabled";
 		};

dts/arm/st/f1/stm32f103X8.dtsi

@@ -30,7 +30,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40003800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
 			interrupts = <36 5>;
 			status = "disabled";
 		};
@@ -43,7 +43,7 @@
 			num-bidir-endpoints = <8>;
 			ram-size = <512>;
 			status = "disabled";
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 23U)>;
 			phys = <&usb_fs_phy>;
 		};
 
@@ -52,7 +52,7 @@
 			reg = <0x40006400 0x400>;
 			interrupts = <19 0>, <20 0>, <21 0>, <22 0>;
 			interrupt-names = "TX", "RX0", "RX1", "SCE";
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 25U)>;
 			status = "disabled";
 		};
 	};

dts/arm/st/f1/stm32f103Xc.dtsi

@@ -26,7 +26,7 @@
 		uart4: serial@40004c00 {
 			compatible = "st,stm32-uart";
 			reg = <0x40004c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
 			resets = <&rctl STM32_RESET(APB1, 19U)>;
 			interrupts = <52 0>;
 			status = "disabled";
@@ -35,7 +35,7 @@
 		uart5: serial@40005000 {
 			compatible = "st,stm32-uart";
 			reg = <0x40005000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
 			resets = <&rctl STM32_RESET(APB1, 20U)>;
 			interrupts = <53 0>;
 			status = "disabled";
@@ -44,7 +44,7 @@
 		timers5: timers@40000c00 {
 			compatible = "st,stm32-timers";
 			reg = <0x40000c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
+			clocks = <&rcc STM32_CLOCK(APB1, 3U)>;
 			resets = <&rctl STM32_RESET(APB1, 3U)>;
 			interrupts = <50 0>;
 			interrupt-names = "global";
@@ -61,7 +61,7 @@
 		timers6: timers@40001000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40001000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
+			clocks = <&rcc STM32_CLOCK(APB1, 4U)>;
 			resets = <&rctl STM32_RESET(APB1, 4U)>;
 			interrupts = <54 0>;
 			interrupt-names = "global";
@@ -72,7 +72,7 @@
 		timers7: timers@40001400 {
 			compatible = "st,stm32-timers";
 			reg = <0x40001400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
+			clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
 			resets = <&rctl STM32_RESET(APB1, 5U)>;
 			interrupts = <55 0>;
 			interrupt-names = "global";
@@ -85,7 +85,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0X40003c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
 			interrupts = <51 5>;
 			status = "disabled";
 		};
@@ -93,7 +93,7 @@
 		dac1: dac@40007400 {
 			compatible = "st,stm32-dac";
 			reg = <0x40007400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 29U)>;
 			status = "disabled";
 			#io-channel-cells = <1>;
 		};
@@ -106,7 +106,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x40011c00 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000080>;
+				clocks = <&rcc STM32_CLOCK(APB2, 7U)>;
 			};
 
 			gpiog: gpio@40012000 {
@@ -114,14 +114,14 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x40012000 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000100>;
+				clocks = <&rcc STM32_CLOCK(APB2, 8U)>;
 			};
 		};
 
 		adc2: adc@40012800 {
 			compatible = "st,stm32-adc";
 			reg = <0x40012800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000400>;
+			clocks = <&rcc STM32_CLOCK(APB2, 10U)>;
 			/* Shares vector with ADC1 */
 			interrupts = <18 0>;
 			status = "disabled";
@@ -131,7 +131,7 @@
 		adc3: adc@40013c00 {
 			compatible = "st,stm32-adc";
 			reg = <0x40013c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00008000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 15U)>;
 			interrupts = <47 0>;
 			status = "disabled";
 			#io-channel-cells = <1>;
@@ -140,7 +140,7 @@
 		timers8: timers@40013400 {
 			compatible = "st,stm32-timers";
 			reg = <0x40013400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 13U)>;
 			resets = <&rctl STM32_RESET(APB2, 13U)>;
 			interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
 			interrupt-names = "brk", "up", "trgcom", "cc";
@@ -158,7 +158,7 @@
 			compatible = "st,stm32-dma-v2bis";
 			#dma-cells = <2>;
 			reg = <0x40020400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 1U)>;
 			interrupts = < 56 0 57 0 58 0 59 0 60 0>;
 			status = "disabled";
 		};

dts/arm/st/f1/stm32f103Xg.dtsi

@@ -32,7 +32,7 @@
 		timers9: timers@40014c00 {
 			compatible = "st,stm32-timers";
 			reg = <0x40014c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00080000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 19U)>;
 			resets = <&rctl STM32_RESET(APB2, 19U)>;
 			/* Shared with TIM1_BRK */
 			interrupts = <24 0>;
@@ -49,7 +49,7 @@
 		timers10: timers@40015000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40015000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 20U)>;
 			resets = <&rctl STM32_RESET(APB2, 20U)>;
 			/* Shared with TIM1_UP */
 			interrupts = <25 0>;
@@ -66,7 +66,7 @@
 		timers11: timers@40015400 {
 			compatible = "st,stm32-timers";
 			reg = <0x40015400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00200000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 21U)>;
 			resets = <&rctl STM32_RESET(APB2, 21U)>;
 			/* Shared with TIM1_TRG_COM */
 			interrupts = <26 0>;
@@ -83,7 +83,7 @@
 		timers12: timers@40001800 {
 			compatible = "st,stm32-timers";
 			reg = <0x40001800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000040>;
+			clocks = <&rcc STM32_CLOCK(APB1, 6U)>;
 			resets = <&rctl STM32_RESET(APB1, 6U)>;
 			/* Shared with TIM8_BRK */
 			interrupts = <43 0>;
@@ -100,7 +100,7 @@
 		timers13: timers@40001c00 {
 			compatible = "st,stm32-timers";
 			reg = <0x40001c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000080>;
+			clocks = <&rcc STM32_CLOCK(APB1, 7U)>;
 			resets = <&rctl STM32_RESET(APB1, 7U)>;
 			/* Shared with TIM8_UP */
 			interrupts = <44 0>;
@@ -117,7 +117,7 @@
 		timers14: timers@40002000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40002000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000100>;
+			clocks = <&rcc STM32_CLOCK(APB1, 8U)>;
 			resets = <&rctl STM32_RESET(APB1, 8U)>;
 			/* Shared with TIM8_TRG_COM */
 			interrupts = <45 0>;

dts/arm/st/f1/stm32f105.dtsi

@@ -39,7 +39,7 @@
 			reg = <0x40006400 0x400>;
 			interrupts = <19 0>, <20 0>, <21 0>, <22 0>;
 			interrupt-names = "TX", "RX0", "RX1", "SCE";
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 25U)>;
 			status = "disabled";
 		};
 
@@ -49,14 +49,14 @@
 			interrupts = <63 0>, <64 0>, <65 0>, <66 0>;
 			interrupt-names = "TX", "RX0", "RX1", "SCE";
 			/* also enabling clock for can1 (master instance) */
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x06000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 26U)>;
 			status = "disabled";
 		};
 
 		dac1: dac@40007400 {
 			compatible = "st,stm32-dac";
 			reg = <0x40007400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 29U)>;
 			status = "disabled";
 			#io-channel-cells = <1>;
 		};
@@ -64,7 +64,7 @@
 		uart4: serial@40004c00 {
 			compatible = "st,stm32-uart";
 			reg = <0x40004c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
 			resets = <&rctl STM32_RESET(APB1, 19U)>;
 			interrupts = <52 0>;
 			status = "disabled";
@@ -73,7 +73,7 @@
 		uart5: serial@40005000 {
 			compatible = "st,stm32-uart";
 			reg = <0x40005000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
 			resets = <&rctl STM32_RESET(APB1, 20U)>;
 			interrupts = <53 0>;
 			status = "disabled";
@@ -84,7 +84,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40003800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
 			interrupts = <36 5>;
 			status = "disabled";
 		};
@@ -94,7 +94,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40003c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
 			interrupts = <51 5>;
 			status = "disabled";
 		};
@@ -102,7 +102,7 @@
 		timers5: timers@40000c00 {
 			compatible = "st,stm32-timers";
 			reg = <0x40000c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
+			clocks = <&rcc STM32_CLOCK(APB1, 3U)>;
 			resets = <&rctl STM32_RESET(APB1, 3U)>;
 			interrupts = <50 0>;
 			interrupt-names = "global";
@@ -119,7 +119,7 @@
 		timers6: timers@40001000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40001000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
+			clocks = <&rcc STM32_CLOCK(APB1, 4U)>;
 			resets = <&rctl STM32_RESET(APB1, 4U)>;
 			interrupts = <54 0>;
 			interrupt-names = "global";
@@ -130,7 +130,7 @@
 		timers7: timers@40001400 {
 			compatible = "st,stm32-timers";
 			reg = <0x40001400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
+			clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
 			resets = <&rctl STM32_RESET(APB1, 5U)>;
 			interrupts = <55 0>;
 			interrupt-names = "global";
@@ -145,7 +145,7 @@
 			interrupt-names = "otgfs";
 			num-bidir-endpoints = <4>;
 			ram-size = <1280>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00001000>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 12U)>;
 			phys = <&otgfs_phy>;
 			status = "disabled";
 		};

dts/arm/st/f1/stm32f107.dtsi

@@ -14,7 +14,7 @@
 			compatible = "st,stm32-dma-v2bis";
 			#dma-cells = <2>;
 			reg = <0x40020400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 1U)>;
 			interrupts = <56 0 57 0 58 0 59 0 60 0>;
 			status = "disabled";
 		};
@@ -25,9 +25,9 @@
 			interrupts = <61 0>;
 			clock-names = "stmmaceth", "mac-clk-tx",
 				      "mac-clk-rx";
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00004000>,
-				 <&rcc STM32_CLOCK_BUS_AHB1 0x00008000>,
-				 <&rcc STM32_CLOCK_BUS_AHB1 0x00010000>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 14U)>,
+				 <&rcc STM32_CLOCK(AHB1, 15U)>,
+				 <&rcc STM32_CLOCK(AHB1, 16U)>;
 			status = "disabled";
 		};
 	};

dts/arm/st/f2/stm32f2.dtsi

@@ -129,7 +129,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x40020000 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000001>;
+				clocks = <&rcc STM32_CLOCK(AHB1, 0U)>;
 			};
 
 			gpiob: gpio@40020400 {
@@ -137,7 +137,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x40020400 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000002>;
+				clocks = <&rcc STM32_CLOCK(AHB1, 1U)>;
 			};
 
 			gpioc: gpio@40020800 {
@@ -145,7 +145,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x40020800 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000004>;
+				clocks = <&rcc STM32_CLOCK(AHB1, 2U)>;
 			};
 
 			gpiod: gpio@40020c00 {
@@ -153,7 +153,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x40020c00 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000008>;
+				clocks = <&rcc STM32_CLOCK(AHB1, 3U)>;
 			};
 
 			gpioe: gpio@40021000 {
@@ -161,7 +161,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x40021000 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000010>;
+				clocks = <&rcc STM32_CLOCK(AHB1, 4U)>;
 			};
 
 			gpiof: gpio@40021400 {
@@ -169,7 +169,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x40021400 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000020>;
+				clocks = <&rcc STM32_CLOCK(AHB1, 5U)>;
 			};
 
 			gpiog: gpio@40021800 {
@@ -177,7 +177,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x40021800 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000040>;
+				clocks = <&rcc STM32_CLOCK(AHB1, 6U)>;
 			};
 
 			gpioh: gpio@40021c00 {
@@ -185,7 +185,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x40021c00 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000080>;
+				clocks = <&rcc STM32_CLOCK(AHB1, 7U)>;
 			};
 
 			gpioi: gpio@40022000 {
@@ -193,14 +193,14 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x40022000 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000100>;
+				clocks = <&rcc STM32_CLOCK(AHB1, 8U)>;
 			};
 		};
 
 		rtc: rtc@40002800 {
 			compatible = "st,stm32-rtc";
 			reg = <0x40002800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 28U)>;
 			interrupts = <41 0>;
 			prescaler = <32768>;
 			alarms-count = <2>;
@@ -223,7 +223,7 @@
 		wwdg: watchdog@40002c00 {
 			compatible = "st,stm32-window-watchdog";
 			reg = <0x40002C00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
+			clocks = <&rcc STM32_CLOCK(APB1, 11U)>;
 			interrupts = <0 7>;
 			status = "disabled";
 		};
@@ -231,7 +231,7 @@
 		usart1: serial@40011000 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40011000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000010>;
+			clocks = <&rcc STM32_CLOCK(APB2, 4U)>;
 			resets = <&rctl STM32_RESET(APB2, 4U)>;
 			interrupts = <37 0>;
 			status = "disabled";
@@ -240,7 +240,7 @@
 		usart2: serial@40004400 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40004400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 17U)>;
 			resets = <&rctl STM32_RESET(APB1, 17U)>;
 			interrupts = <38 0>;
 			status = "disabled";
@@ -249,7 +249,7 @@
 		usart3: serial@40004800 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40004800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
 			resets = <&rctl STM32_RESET(APB1, 18U)>;
 			interrupts = <39 0>;
 			status = "disabled";
@@ -258,7 +258,7 @@
 		usart6: serial@40011400 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40011400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
+			clocks = <&rcc STM32_CLOCK(APB2, 5U)>;
 			resets = <&rctl STM32_RESET(APB2, 5U)>;
 			interrupts = <71 0>;
 			status = "disabled";
@@ -267,7 +267,7 @@
 		uart4: serial@40004c00 {
 			compatible ="st,stm32-uart";
 			reg = <0x40004c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
 			resets = <&rctl STM32_RESET(APB1, 19U)>;
 			interrupts = <52 0>;
 			status = "disabled";
@@ -276,7 +276,7 @@
 		uart5: serial@40005000 {
 			compatible = "st,stm32-uart";
 			reg = <0x40005000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
 			resets = <&rctl STM32_RESET(APB1, 20U)>;
 			interrupts = <53 0>;
 			status = "disabled";
@@ -287,7 +287,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40013000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 12U)>;
 			interrupts = <35 5>;
 			status = "disabled";
 		};
@@ -297,7 +297,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40003800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
 			interrupts = <36 5>;
 			status = "disabled";
 		};
@@ -307,7 +307,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40003c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
 			interrupts = <51 5>;
 			status = "disabled";
 		};
@@ -318,7 +318,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40005400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 21U)>;
 			interrupts = <31 0>, <32 0>;
 			interrupt-names = "event", "error";
 			status = "disabled";
@@ -330,7 +330,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40005800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
 			interrupts = <33 0>, <34 0>;
 			interrupt-names = "event", "error";
 			status = "disabled";
@@ -342,7 +342,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40005c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 23U)>;
 			interrupts = <72 0>, <73 0>;
 			interrupt-names = "event", "error";
 			status = "disabled";
@@ -356,7 +356,7 @@
 			num-bidir-endpoints = <4>;
 			ram-size = <1280>;
 			maximum-speed = "full-speed";
-			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000080>,
+			clocks = <&rcc STM32_CLOCK(AHB2, 7U)>,
 				 <&rcc STM32_SRC_PLL_Q NO_SEL>;
 			phys = <&otgfs_phy>;
 			status = "disabled";
@@ -365,7 +365,7 @@
 		adc1: adc@40012000 {
 			compatible = "st,stm32f4-adc", "st,stm32-adc";
 			reg = <0x40012000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000100>;
+			clocks = <&rcc STM32_CLOCK(APB2, 8U)>;
 			interrupts = <18 0>;
 			status = "disabled";
 			#io-channel-cells = <1>;
@@ -383,7 +383,7 @@
 			#dma-cells = <4>;
 			reg = <0x40026000 0x400>;
 			interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0 47 0>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x200000>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 21U)>;
 			status = "disabled";
 		};
 
@@ -392,7 +392,7 @@
 			#dma-cells = <4>;
 			reg = <0x40026400 0x400>;
 			interrupts = <56 0 57 0 58 0 59 0 60 0 68 0 69 0 70 0>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x400000>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 22U)>;
 			st,mem2mem;
 			status = "disabled";
 		};
@@ -400,7 +400,7 @@
 		dac1: dac@40007400 {
 			compatible = "st,stm32-dac";
 			reg = <0x40007400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 29U)>;
 			status = "disabled";
 			#io-channel-cells = <1>;
 		};
@@ -408,7 +408,7 @@
 		timers1: timers@40010000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40010000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000001>;
+			clocks = <&rcc STM32_CLOCK(APB2, 0U)>;
 			resets = <&rctl STM32_RESET(APB2, 0U)>;
 			interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
 			interrupt-names = "brk", "up", "trgcom", "cc";
@@ -425,7 +425,7 @@
 		timers2: timers@40000000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40000000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
+			clocks = <&rcc STM32_CLOCK(APB1, 0U)>;
 			resets = <&rctl STM32_RESET(APB1, 0U)>;
 			interrupts = <28 0>;
 			interrupt-names = "global";
@@ -442,7 +442,7 @@
 		timers3: timers@40000400 {
 			compatible = "st,stm32-timers";
 			reg = <0x40000400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
+			clocks = <&rcc STM32_CLOCK(APB1, 1U)>;
 			resets = <&rctl STM32_RESET(APB1, 1U)>;
 			interrupts = <29 0>;
 			interrupt-names = "global";
@@ -464,7 +464,7 @@
 		timers4: timers@40000800 {
 			compatible = "st,stm32-timers";
 			reg = <0x40000800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
+			clocks = <&rcc STM32_CLOCK(APB1, 2U)>;
 			resets = <&rctl STM32_RESET(APB1, 2U)>;
 			interrupts = <30 0>;
 			interrupt-names = "global";
@@ -486,7 +486,7 @@
 		timers5: timers@40000c00 {
 			compatible = "st,stm32-timers";
 			reg = <0x40000c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
+			clocks = <&rcc STM32_CLOCK(APB1, 3U)>;
 			resets = <&rctl STM32_RESET(APB1, 3U)>;
 			interrupts = <50 0>;
 			interrupt-names = "global";
@@ -508,7 +508,7 @@
 		timers6: timers@40001000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40001000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
+			clocks = <&rcc STM32_CLOCK(APB1, 4U)>;
 			resets = <&rctl STM32_RESET(APB1, 4U)>;
 			interrupts = <54 0>;
 			interrupt-names = "global";
@@ -524,7 +524,7 @@
 		timers7: timers@40001400 {
 			compatible = "st,stm32-timers";
 			reg = <0x40001400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
+			clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
 			resets = <&rctl STM32_RESET(APB1, 5U)>;
 			interrupts = <55 0>;
 			interrupt-names = "global";
@@ -540,7 +540,7 @@
 		timers8: timers@40010400 {
 			compatible = "st,stm32-timers";
 			reg = <0x40010400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000002>;
+			clocks = <&rcc STM32_CLOCK(APB2, 1U)>;
 			resets = <&rctl STM32_RESET(APB2, 1U)>;
 			interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
 			interrupt-names = "brk", "up", "trgcom", "cc";
@@ -557,7 +557,7 @@
 		timers9: timers@40014000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40014000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00010000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 16U)>;
 			resets = <&rctl STM32_RESET(APB2, 16U)>;
 			interrupts = <24 0>;
 			interrupt-names = "global";
@@ -579,7 +579,7 @@
 		timers10: timers@40014400 {
 			compatible = "st,stm32-timers";
 			reg = <0x40014400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00020000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 17U)>;
 			resets = <&rctl STM32_RESET(APB2, 17U)>;
 			interrupts = <25 0>;
 			interrupt-names = "global";
@@ -601,7 +601,7 @@
 		timers11: timers@40014800 {
 			compatible = "st,stm32-timers";
 			reg = <0x40014800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00040000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 18U)>;
 			resets = <&rctl STM32_RESET(APB2, 18U)>;
 			interrupts = <26 0>;
 			interrupt-names = "global";
@@ -623,7 +623,7 @@
 		timers12: timers@40001800 {
 			compatible = "st,stm32-timers";
 			reg = <0x40001800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000040>;
+			clocks = <&rcc STM32_CLOCK(APB1, 6U)>;
 			resets = <&rctl STM32_RESET(APB1, 6U)>;
 			interrupts = <43 0>;
 			interrupt-names = "global";
@@ -645,7 +645,7 @@
 		timers13: timers@40001c00 {
 			compatible = "st,stm32-timers";
 			reg = <0x40001c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000080>;
+			clocks = <&rcc STM32_CLOCK(APB1, 7U)>;
 			resets = <&rctl STM32_RESET(APB1, 7U)>;
 			interrupts = <44 0>;
 			interrupt-names = "global";
@@ -667,7 +667,7 @@
 		timers14: timers@40002000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40002000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000100>;
+			clocks = <&rcc STM32_CLOCK(APB1, 8U)>;
 			resets = <&rctl STM32_RESET(APB1, 8U)>;
 			interrupts = <45 0>;
 			interrupt-names = "global";
@@ -690,14 +690,14 @@
 			compatible = "st,stm32-rng";
 			reg = <0x50060800 0x400>;
 			interrupts = <80 0>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000040>;
+			clocks = <&rcc STM32_CLOCK(AHB2, 6U)>;
 			status = "disabled";
 		};
 
 		backup_sram: memory@40024000 {
 			compatible = "zephyr,memory-region", "st,stm32-backup-sram";
 			reg = <0x40024000 DT_SIZE_K(4)>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00040000>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 18U)>;
 			zephyr,memory-region = "BACKUP_SRAM";
 			status = "disabled";
 		};

dts/arm/st/f2/stm32f207.dtsi

@@ -16,10 +16,10 @@
 			interrupts = <61 0>;
 			clock-names = "stmmaceth", "mac-clk-tx",
 				      "mac-clk-rx", "mac-clk-ptp";
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x02000000>,
-				 <&rcc STM32_CLOCK_BUS_AHB1 0x04000000>,
-				 <&rcc STM32_CLOCK_BUS_AHB1 0x08000000>,
-				 <&rcc STM32_CLOCK_BUS_AHB1 0x10000000>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 25U)>,
+				 <&rcc STM32_CLOCK(AHB1, 26U)>,
+				 <&rcc STM32_CLOCK(AHB1, 27U)>,
+				 <&rcc STM32_CLOCK(AHB1, 28U)>;
 			status = "disabled";
 		};
 	};

dts/arm/st/f3/stm32f3.dtsi

@@ -79,7 +79,7 @@
 			compatible = "st,stm32-flash-controller", "st,stm32f1-flash-controller";
 			reg = <0x40022000 0x400>;
 			interrupts = <4 0>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000010>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 4U)>;
 
 			#address-cells = <1>;
 			#size-cells = <1>;
@@ -131,7 +131,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x48000000 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00020000>;
+				clocks = <&rcc STM32_CLOCK(AHB1, 17U)>;
 			};
 
 			gpiob: gpio@48000400 {
@@ -139,7 +139,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x48000400 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00040000>;
+				clocks = <&rcc STM32_CLOCK(AHB1, 18U)>;
 			};
 
 			gpioc: gpio@48000800 {
@@ -147,7 +147,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x48000800 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00080000>;
+				clocks = <&rcc STM32_CLOCK(AHB1, 19U)>;
 			};
 
 			gpiod: gpio@48000c00 {
@@ -155,7 +155,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x48000c00 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00100000>;
+				clocks = <&rcc STM32_CLOCK(AHB1, 20U)>;
 			};
 
 			gpiof: gpio@48001400 {
@@ -163,7 +163,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x48001400 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00400000>;
+				clocks = <&rcc STM32_CLOCK(AHB1, 22U)>;
 			};
 		};
 
@@ -176,7 +176,7 @@
 		wwdg: watchdog@40002c00 {
 			compatible = "st,stm32-window-watchdog";
 			reg = <0x40002C00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
+			clocks = <&rcc STM32_CLOCK(APB1, 11U)>;
 			interrupts = <0 7>;
 			status = "disabled";
 		};
@@ -184,7 +184,7 @@
 		usart1: serial@40013800 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40013800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 14U)>;
 			resets = <&rctl STM32_RESET(APB2, 14U)>;
 			interrupts = <37 0>;
 			status = "disabled";
@@ -193,7 +193,7 @@
 		usart2: serial@40004400 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40004400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 17U)>;
 			resets = <&rctl STM32_RESET(APB1, 17U)>;
 			interrupts = <38 0>;
 			status = "disabled";
@@ -202,7 +202,7 @@
 		usart3: serial@40004800 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40004800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
 			resets = <&rctl STM32_RESET(APB1, 18U)>;
 			interrupts = <39 0>;
 			status = "disabled";
@@ -211,7 +211,7 @@
 		uart4: serial@40004c00 {
 			compatible = "st,stm32-uart";
 			reg = <0x40004c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
 			resets = <&rctl STM32_RESET(APB1, 19U)>;
 			interrupts = <52 0>;
 			status = "disabled";
@@ -223,7 +223,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40005400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>,
+			clocks = <&rcc STM32_CLOCK(APB1, 21U)>,
 				 /* I2C clock source should always be defined,
 				  * even for the default value
 				  */
@@ -238,7 +238,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40013000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 12U)>;
 			interrupts = <35 5>;
 			status = "disabled";
 		};
@@ -246,7 +246,7 @@
 		dac1: dac@40007400 {
 			compatible = "st,stm32-dac";
 			reg = <0x40007400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 29U)>;
 			status = "disabled";
 			#io-channel-cells = <1>;
 		};
@@ -259,14 +259,14 @@
 			num-bidir-endpoints = <8>;
 			ram-size = <512>;
 			phys = <&usb_fs_phy>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 23U)>;
 			status = "disabled";
 		};
 
 		timers2: timers@40000000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40000000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
+			clocks = <&rcc STM32_CLOCK(APB1, 0U)>;
 			resets = <&rctl STM32_RESET(APB1, 0U)>;
 			interrupts = <28 0>;
 			interrupt-names = "global";
@@ -288,7 +288,7 @@
 		timers3: timers@40000400 {
 			compatible = "st,stm32-timers";
 			reg = <0x40000400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
+			clocks = <&rcc STM32_CLOCK(APB1, 1U)>;
 			resets = <&rctl STM32_RESET(APB1, 1U)>;
 			interrupts = <29 0>;
 			interrupt-names = "global";
@@ -310,7 +310,7 @@
 		timers6: timers@40001000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40001000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
+			clocks = <&rcc STM32_CLOCK(APB1, 4U)>;
 			resets = <&rctl STM32_RESET(APB1, 4U)>;
 			interrupts = <54 0>;
 			interrupt-names = "global";
@@ -326,7 +326,7 @@
 		timers7: timers@40001400 {
 			compatible = "st,stm32-timers";
 			reg = <0x40001400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
+			clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
 			resets = <&rctl STM32_RESET(APB1, 5U)>;
 			interrupts = <55 0>;
 			interrupt-names = "global";
@@ -342,7 +342,7 @@
 		timers15: timers@40014000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40014000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00010000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 16U)>;
 			resets = <&rctl STM32_RESET(APB2, 16U)>;
 			interrupts = <24 0>;
 			interrupt-names = "global";
@@ -364,7 +364,7 @@
 		timers16: timers@40014400 {
 			compatible = "st,stm32-timers";
 			reg = <0x40014400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00020000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 17U)>;
 			resets = <&rctl STM32_RESET(APB2, 17U)>;
 			interrupts = <25 0>;
 			interrupt-names = "global";
@@ -386,7 +386,7 @@
 		timers17: timers@40014800 {
 			compatible = "st,stm32-timers";
 			reg = <0x40014800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00040000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 18U)>;
 			resets = <&rctl STM32_RESET(APB2, 18U)>;
 			interrupts = <26 0>;
 			interrupt-names = "global";
@@ -408,7 +408,7 @@
 		rtc: rtc@40002800 {
 			compatible = "st,stm32-rtc";
 			reg = <0x40002800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 28U)>;
 			interrupts = <41 0>;
 			prescaler = <32768>;
 			alarms-count = <2>;
@@ -421,7 +421,7 @@
 			reg = <0x40006400 0x400>;
 			interrupts = <19 0>, <20 0>, <21 0>, <22 0>;
 			interrupt-names = "TX", "RX0", "RX1", "SCE";
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 25U)>;
 			status = "disabled";
 		};
 
@@ -429,7 +429,7 @@
 			compatible = "st,stm32-dma-v2bis";
 			#dma-cells = <2>;
 			reg = <0x40020000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 0U)>;
 			interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0>;
 			status = "disabled";
 		};

dts/arm/st/f3/stm32f302.dtsi

@@ -22,7 +22,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40005800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>,
+			clocks = <&rcc STM32_CLOCK(APB1, 22U)>,
 				 /* I2C clock source should always be defined,
 				  * even for the default value
 				  */
@@ -38,7 +38,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40007800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x40000000>,
+			clocks = <&rcc STM32_CLOCK(APB1, 30U)>,
 				 /* I2C clock source should always be defined,
 				  * even for the default value
 				  */
@@ -53,7 +53,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40003800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
 			interrupts = <36 5>;
 			status = "disabled";
 		};
@@ -63,7 +63,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0X40003c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
 			interrupts = <51 5>;
 			status = "disabled";
 		};
@@ -71,7 +71,7 @@
 		timers1: timers@40012c00 {
 			compatible = "st,stm32-timers";
 			reg = <0x40012c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>;
+			clocks = <&rcc STM32_CLOCK(APB2, 11U)>;
 			resets = <&rctl STM32_RESET(APB2, 11U)>;
 			interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
 			interrupt-names = "brk", "up", "trgcom", "cc";
@@ -88,7 +88,7 @@
 		timers4: timers@40000800 {
 			compatible = "st,stm32-timers";
 			reg = <0x40000800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
+			clocks = <&rcc STM32_CLOCK(APB1, 2U)>;
 			resets = <&rctl STM32_RESET(APB1, 2U)>;
 			interrupts = <30 0>;
 			interrupt-names = "global";
@@ -105,7 +105,7 @@
 		adc1: adc@50000000 {
 			compatible = "st,stm32-adc";
 			reg = <0x50000000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x10000000>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 28U)>;
 			interrupts = <18 0>;
 			status = "disabled";
 			#io-channel-cells = <1>;

dts/arm/st/f3/stm32f302Xc.dtsi

@@ -23,7 +23,7 @@
 			compatible = "st,stm32-dma-v2bis";
 			#dma-cells = <2>;
 			reg = <0x40020400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 1U)>;
 			interrupts = <56 0 57 0 58 0 59 0 60 0>;
 			status = "disabled";
 		};
@@ -31,7 +31,7 @@
 		uart5: serial@40005000 {
 			compatible = "st,stm32-uart";
 			reg = <0x40005000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
 			interrupts = <53 0>;
 			status = "disabled";
 		};
@@ -42,7 +42,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x48001000 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00200000>;
+				clocks = <&rcc STM32_CLOCK(AHB1, 21U)>;
 			};
 		};
 	};

dts/arm/st/f3/stm32f303.dtsi

@@ -22,7 +22,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40005800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>,
+			clocks = <&rcc STM32_CLOCK(APB1, 22U)>,
 				 /* I2C clock source should always be defined,
 				  * even for the default value
 				  */
@@ -37,7 +37,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40003800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
 			interrupts = <36 5>;
 			status = "disabled";
 		};
@@ -47,7 +47,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40003c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
 			interrupts = <51 5>;
 			status = "disabled";
 		};
@@ -55,7 +55,7 @@
 		uart5: serial@40005000 {
 			compatible = "st,stm32-uart";
 			reg = <0x40005000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
 			resets = <&rctl STM32_RESET(APB1, 20U)>;
 			interrupts = <53 0>;
 			status = "disabled";
@@ -68,14 +68,14 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x48001000 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00200000>;
+				clocks = <&rcc STM32_CLOCK(AHB1, 21U)>;
 			};
 		};
 
 		timers1: timers@40012c00 {
 			compatible = "st,stm32-timers";
 			reg = <0x40012c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>;
+			clocks = <&rcc STM32_CLOCK(APB2, 11U)>;
 			resets = <&rctl STM32_RESET(APB2, 11U)>;
 			interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
 			interrupt-names = "brk", "up", "trgcom", "cc";
@@ -92,7 +92,7 @@
 		timers4: timers@40000800 {
 			compatible = "st,stm32-timers";
 			reg = <0x40000800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
+			clocks = <&rcc STM32_CLOCK(APB1, 2U)>;
 			resets = <&rctl STM32_RESET(APB1, 2U)>;
 			interrupts = <30 0>;
 			interrupt-names = "global";
@@ -109,7 +109,7 @@
 		timers8: timers@40013400 {
 			compatible = "st,stm32-timers";
 			reg = <0x40013400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 13U)>;
 			resets = <&rctl STM32_RESET(APB2, 13U)>;
 			interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
 			interrupt-names = "brk", "up", "trgcom", "cc";
@@ -126,7 +126,7 @@
 		timers20: timers@40015000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40015000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 20U)>;
 			resets = <&rctl STM32_RESET(APB2, 20U)>;
 			interrupts = <77 0>, <78 0>, <79 0>, <80 0>;
 			interrupt-names = "brk", "up", "trgcom", "cc";
@@ -143,7 +143,7 @@
 		adc1: adc@50000000 {
 			compatible = "st,stm32-adc";
 			reg = <0x50000000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x10000000>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 28U)>;
 			interrupts = <18 0>;
 			status = "disabled";
 			vref-mv = <3000>;
@@ -159,7 +159,7 @@
 		adc2: adc@50000100 {
 			compatible = "st,stm32-adc";
 			reg = <0x50000100 0x4c>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x10000000>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 28U)>;
 			interrupts = <18 0>;
 			status = "disabled";
 			vref-mv = <3000>;

dts/arm/st/f3/stm32f303X8.dtsi

@@ -28,7 +28,7 @@
 		dac2: dac@40009800 {
 			compatible = "st,stm32-dac";
 			reg = <0x40009800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x04000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 26U)>;
 			status = "disabled";
 			#io-channel-cells = <1>;
 		};

dts/arm/st/f3/stm32f303Xb.dtsi

@@ -29,7 +29,7 @@
 			compatible = "st,stm32-dma-v2bis";
 			#dma-cells = <2>;
 			reg = <0x40020400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 1U)>;
 			interrupts = <56 0 57 0 58 0 59 0 60 0>;
 			status = "disabled";
 		};

dts/arm/st/f3/stm32f303Xe.dtsi

@@ -29,7 +29,7 @@
 			compatible = "st,stm32-dma-v2bis";
 			#dma-cells = <2>;
 			reg = <0x40020400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 1U)>;
 			interrupts = <56 0 57 0 58 0 59 0 60 0>;
 			status = "disabled";
 		};

dts/arm/st/f3/stm32f334.dtsi

@@ -14,7 +14,7 @@
 		timers1: timers@40012c00 {
 			compatible = "st,stm32-timers";
 			reg = <0x40012c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>;
+			clocks = <&rcc STM32_CLOCK(APB2, 11U)>;
 			resets = <&rctl STM32_RESET(APB2, 11U)>;
 			interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
 			interrupt-names = "brk", "up", "trgcom", "cc";
@@ -31,7 +31,7 @@
 		adc1: adc@50000000 {
 			compatible = "st,stm32-adc";
 			reg = <0x50000000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x10000000>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 28U)>;
 			interrupts = <18 0>;
 			status = "disabled";
 			#io-channel-cells = <1>;

dts/arm/st/f3/stm32f334X8.dtsi

@@ -28,7 +28,7 @@
 		dac2: dac@40009800 {
 			compatible = "st,stm32-dac";
 			reg = <0x40009800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x04000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 26U)>;
 			status = "disabled";
 			#io-channel-cells = <1>;
 		};

dts/arm/st/f3/stm32f373.dtsi

@@ -25,7 +25,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x48001000 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00200000>;
+				clocks = <&rcc STM32_CLOCK(AHB1, 21U)>;
 			};
 		};
 
@@ -35,7 +35,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40005800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>,
+			clocks = <&rcc STM32_CLOCK(APB1, 22U)>,
 				 /* I2C clock source should always be defined,
 				  * even for the default value
 				  */
@@ -50,7 +50,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40003800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
 			interrupts = <36 5>;
 			status = "disabled";
 		};
@@ -60,7 +60,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40003c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
 			interrupts = <51 5>;
 			status = "disabled";
 		};
@@ -68,7 +68,7 @@
 		timers4: timers@40000800 {
 			compatible = "st,stm32-timers";
 			reg = <0x40000800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
+			clocks = <&rcc STM32_CLOCK(APB1, 2U)>;
 			resets = <&rctl STM32_RESET(APB1, 2U)>;
 			interrupts = <30 0>;
 			interrupt-names = "global";
@@ -85,7 +85,7 @@
 		timers5: timers@40000c00 {
 			compatible = "st,stm32-timers";
 			reg = <0x40000c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
+			clocks = <&rcc STM32_CLOCK(APB1, 3U)>;
 			resets = <&rctl STM32_RESET(APB1, 3U)>;
 			interrupts = <50 0>;
 			interrupt-names = "global";
@@ -102,7 +102,7 @@
 		timers12: timers@40001800 {
 			compatible = "st,stm32-timers";
 			reg = <0x40001800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000040>;
+			clocks = <&rcc STM32_CLOCK(APB1, 6U)>;
 			resets = <&rctl STM32_RESET(APB1, 6U)>;
 			interrupts = <43 0>;
 			interrupt-names = "global";
@@ -119,7 +119,7 @@
 		timers13: timers@40001c00 {
 			compatible = "st,stm32-timers";
 			reg = <0x40001c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000080>;
+			clocks = <&rcc STM32_CLOCK(APB1, 7U)>;
 			resets = <&rctl STM32_RESET(APB1, 7U)>;
 			interrupts = <44 0>;
 			interrupt-names = "global";
@@ -136,7 +136,7 @@
 		timers14: timers@40002000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40002000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000100>;
+			clocks = <&rcc STM32_CLOCK(APB1, 8U)>;
 			resets = <&rctl STM32_RESET(APB1, 8U)>;
 			interrupts = <45 0>;
 			interrupt-names = "global";
@@ -153,7 +153,7 @@
 		timers18: timers@40009c00 {
 			compatible = "st,stm32-timers";
 			reg = <0x40009c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000200>;
+			clocks = <&rcc STM32_CLOCK(APB1, 9U)>;
 			resets = <&rctl STM32_RESET(APB1, 9U)>;
 			interrupts = <27 0>;
 			interrupt-names = "global";
@@ -170,7 +170,7 @@
 		timers19: timers@40015c00 {
 			compatible = "st,stm32-timers";
 			reg = <0x40015c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00080000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 19U)>;
 			resets = <&rctl STM32_RESET(APB2, 19U)>;
 			interrupts = <78 0>;
 			interrupt-names = "global";
@@ -187,7 +187,7 @@
 		adc1: adc@40012400 {
 			compatible = "st,stm32f1-adc", "st,stm32-adc";
 			reg = <0x40012400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000200>;
+			clocks = <&rcc STM32_CLOCK(APB2, 9U)>;
 			interrupts = <18 0>;
 			status = "disabled";
 			#io-channel-cells = <1>;

dts/arm/st/f3/stm32f373Xc.dtsi

@@ -22,7 +22,7 @@
 		dma2: dma@40020400 {
 			compatible = "st,stm32-dma-v2bis";
 			reg = <0x40020400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 1U)>;
 			interrupts = <56 0 57 0 58 0 59 0 60 0>;
 			status = "disabled";
 		};
@@ -30,7 +30,7 @@
 		dac2: dac@40009800 {
 			compatible = "st,stm32-dac";
 			reg = <0x40009800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x04000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 26U)>;
 			status = "disabled";
 			#io-channel-cells = <1>;
 		};

dts/arm/st/f4/stm32f4.dtsi

@@ -160,7 +160,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x40020000 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000001>;
+				clocks = <&rcc STM32_CLOCK(AHB1, 0U)>;
 			};
 
 			gpiob: gpio@40020400 {
@@ -168,7 +168,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x40020400 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000002>;
+				clocks = <&rcc STM32_CLOCK(AHB1, 1U)>;
 			};
 
 			gpioc: gpio@40020800 {
@@ -176,7 +176,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x40020800 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000004>;
+				clocks = <&rcc STM32_CLOCK(AHB1, 2U)>;
 			};
 
 			gpiod: gpio@40020c00 {
@@ -184,7 +184,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x40020c00 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000008>;
+				clocks = <&rcc STM32_CLOCK(AHB1, 3U)>;
 			};
 
 			gpioe: gpio@40021000 {
@@ -192,7 +192,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x40021000 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000010>;
+				clocks = <&rcc STM32_CLOCK(AHB1, 4U)>;
 			};
 
 			gpiof: gpio@40021400 {
@@ -200,7 +200,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x40021400 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000020>;
+				clocks = <&rcc STM32_CLOCK(AHB1, 5U)>;
 			};
 
 			gpiog: gpio@40021800 {
@@ -208,7 +208,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x40021800 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000040>;
+				clocks = <&rcc STM32_CLOCK(AHB1, 6U)>;
 			};
 
 			gpioh: gpio@40021c00 {
@@ -216,7 +216,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x40021c00 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000080>;
+				clocks = <&rcc STM32_CLOCK(AHB1, 7U)>;
 			};
 		};
 
@@ -229,7 +229,7 @@
 		wwdg: watchdog@40002c00 {
 			compatible = "st,stm32-window-watchdog";
 			reg = <0x40002C00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
+			clocks = <&rcc STM32_CLOCK(APB1, 11U)>;
 			interrupts = <0 7>;
 			status = "disabled";
 		};
@@ -237,7 +237,7 @@
 		usart1: serial@40011000 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40011000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000010>;
+			clocks = <&rcc STM32_CLOCK(APB2, 4U)>;
 			resets = <&rctl STM32_RESET(APB2, 4U)>;
 			interrupts = <37 0>;
 			status = "disabled";
@@ -246,7 +246,7 @@
 		usart2: serial@40004400 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40004400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 17U)>;
 			resets = <&rctl STM32_RESET(APB1, 17U)>;
 			interrupts = <38 0>;
 			status = "disabled";
@@ -255,7 +255,7 @@
 		usart6: serial@40011400 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40011400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
+			clocks = <&rcc STM32_CLOCK(APB2, 5U)>;
 			resets = <&rctl STM32_RESET(APB2, 5U)>;
 			interrupts = <71 0>;
 			status = "disabled";
@@ -267,7 +267,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40005400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 21U)>;
 			interrupts = <31 0>, <32 0>;
 			interrupt-names = "event", "error";
 			status = "disabled";
@@ -279,7 +279,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40005800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
 			interrupts = <33 0>, <34 0>;
 			interrupt-names = "event", "error";
 			status = "disabled";
@@ -291,7 +291,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40005c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 23U)>;
 			interrupts = <72 0>, <73 0>;
 			interrupt-names = "event", "error";
 			status = "disabled";
@@ -302,7 +302,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40013000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 12U)>;
 			interrupts = <35 5>;
 			status = "disabled";
 		};
@@ -316,7 +316,7 @@
 			ram-size = <1280>;
 			maximum-speed = "full-speed";
 			phys = <&otgfs_phy>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000080>,
+			clocks = <&rcc STM32_CLOCK(AHB2, 7U)>,
 				 <&rcc STM32_SRC_PLL_Q NO_SEL>;
 			status = "disabled";
 		};
@@ -324,7 +324,7 @@
 		timers1: timers@40010000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40010000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000001>;
+			clocks = <&rcc STM32_CLOCK(APB2, 0U)>;
 			resets = <&rctl STM32_RESET(APB2, 0U)>;
 			interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
 			interrupt-names = "brk", "up", "trgcom", "cc";
@@ -347,7 +347,7 @@
 		timers2: timers@40000000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40000000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
+			clocks = <&rcc STM32_CLOCK(APB1, 0U)>;
 			resets = <&rctl STM32_RESET(APB1, 0U)>;
 			interrupts = <28 0>;
 			interrupt-names = "global";
@@ -375,7 +375,7 @@
 		timers3: timers@40000400 {
 			compatible = "st,stm32-timers";
 			reg = <0x40000400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
+			clocks = <&rcc STM32_CLOCK(APB1, 1U)>;
 			resets = <&rctl STM32_RESET(APB1, 1U)>;
 			interrupts = <29 0>;
 			interrupt-names = "global";
@@ -403,7 +403,7 @@
 		timers4: timers@40000800 {
 			compatible = "st,stm32-timers";
 			reg = <0x40000800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
+			clocks = <&rcc STM32_CLOCK(APB1, 2U)>;
 			resets = <&rctl STM32_RESET(APB1, 2U)>;
 			interrupts = <30 0>;
 			interrupt-names = "global";
@@ -431,7 +431,7 @@
 		timers5: timers@40000c00 {
 			compatible = "st,stm32-timers";
 			reg = <0x40000c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
+			clocks = <&rcc STM32_CLOCK(APB1, 3U)>;
 			resets = <&rctl STM32_RESET(APB1, 3U)>;
 			interrupts = <50 0>;
 			interrupt-names = "global";
@@ -459,7 +459,7 @@
 		timers9: timers@40014000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40014000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00010000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 16U)>;
 			resets = <&rctl STM32_RESET(APB2, 16U)>;
 			interrupts = <24 0>;
 			interrupt-names = "global";
@@ -481,7 +481,7 @@
 		timers10: timers@40014400 {
 			compatible = "st,stm32-timers";
 			reg = <0x40014400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00020000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 17U)>;
 			resets = <&rctl STM32_RESET(APB2, 17U)>;
 			interrupts = <25 0>;
 			interrupt-names = "global";
@@ -503,7 +503,7 @@
 		timers11: timers@40014800 {
 			compatible = "st,stm32-timers";
 			reg = <0x40014800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00040000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 18U)>;
 			resets = <&rctl STM32_RESET(APB2, 18U)>;
 			interrupts = <26 0>;
 			interrupt-names = "global";
@@ -526,7 +526,7 @@
 			compatible = "st,stm32-rtc";
 			reg = <0x40002800 0x400>;
 			interrupts = <41 0>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 28U)>;
 			prescaler = <32768>;
 			alarms-count = <2>;
 			alrm-exti-line = <17>;
@@ -542,7 +542,7 @@
 		adc1: adc@40012000 {
 			compatible = "st,stm32f4-adc", "st,stm32-adc";
 			reg = <0x40012000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000100>;
+			clocks = <&rcc STM32_CLOCK(APB2, 8U)>;
 			interrupts = <18 0>;
 			status = "disabled";
 			#io-channel-cells = <1>;
@@ -560,7 +560,7 @@
 			#dma-cells = <4>;
 			reg = <0x40026000 0x400>;
 			interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0 47 0>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x200000>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 21U)>;
 			status = "disabled";
 		};
 
@@ -569,7 +569,7 @@
 			#dma-cells = <4>;
 			reg = <0x40026400 0x400>;
 			interrupts = <56 0 57 0 58 0 59 0 60 0 68 0 69 0 70 0>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x400000>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 22U)>;
 			st,mem2mem;
 			status = "disabled";
 		};
@@ -577,7 +577,7 @@
 		sdmmc1: sdmmc@40012c00 {
 			compatible = "st,stm32-sdmmc";
 			reg = <0x40012c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>,
+			clocks = <&rcc STM32_CLOCK(APB2, 11U)>,
 				 <&rcc STM32_SRC_PLL_Q NO_SEL>;
 			resets = <&rctl STM32_RESET(APB2, 11U)>;
 			interrupts = <49 0>;

dts/arm/st/f4/stm32f401.dtsi

@@ -23,7 +23,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40003800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
 			interrupts = <36 5>;
 			status = "disabled";
 		};
@@ -33,7 +33,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40003c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
 			interrupts = <51 5>;
 			status = "disabled";
 		};
@@ -43,7 +43,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40013400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 13U)>;
 			interrupts = <84 5>;
 			status = "disabled";
 		};
@@ -53,7 +53,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40003800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
 			interrupts = <36 5>;
 			dmas = <&dma1 4 0 0x400 0x3
 				&dma1 3 0 0x400 0x3>;
@@ -66,7 +66,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40003c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
 			interrupts = <51 5>;
 			dmas = <&dma1 5 0 0x400 0x3
 				&dma1 0 0 0x400 0x3>;

dts/arm/st/f4/stm32f405.dtsi

@@ -23,7 +23,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x40021400 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000020>;
+				clocks = <&rcc STM32_CLOCK(AHB1, 5U)>;
 			};
 
 			gpiog: gpio@40021800 {
@@ -31,7 +31,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x40021800 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000040>;
+				clocks = <&rcc STM32_CLOCK(AHB1, 6U)>;
 			};
 
 			gpioi: gpio@40022000 {
@@ -39,14 +39,14 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x40022000 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000100>;
+				clocks = <&rcc STM32_CLOCK(AHB1, 8U)>;
 			};
 		};
 
 		usart3: serial@40004800 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40004800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
 			resets = <&rctl STM32_RESET(APB1, 18U)>;
 			interrupts = <39 0>;
 			status = "disabled";
@@ -55,7 +55,7 @@
 		uart4: serial@40004c00 {
 			compatible ="st,stm32-uart";
 			reg = <0x40004c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
 			resets = <&rctl STM32_RESET(APB1, 19U)>;
 			interrupts = <52 0>;
 			status = "disabled";
@@ -64,7 +64,7 @@
 		uart5: serial@40005000 {
 			compatible = "st,stm32-uart";
 			reg = <0x40005000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
 			resets = <&rctl STM32_RESET(APB1, 20U)>;
 			interrupts = <53 0>;
 			status = "disabled";
@@ -73,7 +73,7 @@
 		timers6: timers@40001000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40001000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
+			clocks = <&rcc STM32_CLOCK(APB1, 4U)>;
 			resets = <&rctl STM32_RESET(APB1, 4U)>;
 			interrupts = <54 0>;
 			interrupt-names = "global";
@@ -89,7 +89,7 @@
 		timers7: timers@40001400 {
 			compatible = "st,stm32-timers";
 			reg = <0x40001400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
+			clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
 			resets = <&rctl STM32_RESET(APB1, 5U)>;
 			interrupts = <55 0>;
 			interrupt-names = "global";
@@ -105,7 +105,7 @@
 		timers8: timers@40010400 {
 			compatible = "st,stm32-timers";
 			reg = <0x40010400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000002>;
+			clocks = <&rcc STM32_CLOCK(APB2, 1U)>;
 			resets = <&rctl STM32_RESET(APB2, 1U)>;
 			interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
 			interrupt-names = "brk", "up", "trgcom", "cc";
@@ -128,7 +128,7 @@
 		timers12: timers@40001800 {
 			compatible = "st,stm32-timers";
 			reg = <0x40001800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000040>;
+			clocks = <&rcc STM32_CLOCK(APB1, 6U)>;
 			resets = <&rctl STM32_RESET(APB1, 6U)>;
 			interrupts = <43 0>;
 			interrupt-names = "global";
@@ -150,7 +150,7 @@
 		timers13: timers@40001c00 {
 			compatible = "st,stm32-timers";
 			reg = <0x40001c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000080>;
+			clocks = <&rcc STM32_CLOCK(APB1, 7U)>;
 			resets = <&rctl STM32_RESET(APB1, 7U)>;
 			interrupts = <44 0>;
 			interrupt-names = "global";
@@ -172,7 +172,7 @@
 		timers14: timers@40002000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40002000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000100>;
+			clocks = <&rcc STM32_CLOCK(APB1, 8U)>;
 			resets = <&rctl STM32_RESET(APB1, 8U)>;
 			interrupts = <45 0>;
 			interrupt-names = "global";
@@ -200,7 +200,7 @@
 			ram-size = <4096>;
 			maximum-speed = "full-speed";
 			phys = <&otghs_fs_phy>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x20000000>,
+			clocks = <&rcc STM32_CLOCK(AHB1, 29U)>,
 				 <&rcc STM32_SRC_PLL_Q NO_SEL>;
 			status = "disabled";
 		};
@@ -210,7 +210,7 @@
 			reg = <0x40006400 0x400>;
 			interrupts = <19 0>, <20 0>, <21 0>, <22 0>;
 			interrupt-names = "TX", "RX0", "RX1", "SCE";
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 25U)>;
 			status = "disabled";
 		};
 
@@ -220,7 +220,7 @@
 			interrupts = <63 0>, <64 0>, <65 0>, <66 0>;
 			interrupt-names = "TX", "RX0", "RX1", "SCE";
 			/* also enabling clock for can1 (master instance) */
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x06000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 26U)>;
 			master-can-reg = <0x40006400>;
 			status = "disabled";
 		};
@@ -229,14 +229,14 @@
 			compatible = "st,stm32-rng";
 			reg = <0x50060800 0x400>;
 			interrupts = <80 0>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000040>;
+			clocks = <&rcc STM32_CLOCK(AHB2, 6U)>;
 			status = "disabled";
 		};
 
 		backup_sram: memory@40024000 {
 			compatible = "zephyr,memory-region", "st,stm32-backup-sram";
 			reg = <0x40024000 DT_SIZE_K(4)>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00040000>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 18U)>;
 			zephyr,memory-region = "BACKUP_SRAM";
 			status = "disabled";
 		};
@@ -244,7 +244,7 @@
 		adc2: adc@40012100 {
 			compatible = "st,stm32-adc";
 			reg = <0x40012100 0x050>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000200>;
+			clocks = <&rcc STM32_CLOCK(APB2, 9U)>;
 			interrupts = <18 0>;
 			status = "disabled";
 			#io-channel-cells = <1>;
@@ -260,7 +260,7 @@
 		adc3: adc@40012200 {
 			compatible = "st,stm32-adc";
 			reg = <0x40012200 0x050>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000400>;
+			clocks = <&rcc STM32_CLOCK(APB2, 10U)>;
 			interrupts = <18 0>;
 			status = "disabled";
 			#io-channel-cells = <1>;
@@ -276,7 +276,7 @@
 		dac1: dac@40007400 {
 			compatible = "st,stm32-dac";
 			reg = <0x40007400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 29U)>;
 			status = "disabled";
 			#io-channel-cells = <1>;
 		};

dts/arm/st/f4/stm32f407.dtsi

@@ -16,10 +16,10 @@
 			interrupts = <61 0>;
 			clock-names = "stmmaceth", "mac-clk-tx",
 				      "mac-clk-rx", "mac-clk-ptp";
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x02000000>,
-				 <&rcc STM32_CLOCK_BUS_AHB1 0x04000000>,
-				 <&rcc STM32_CLOCK_BUS_AHB1 0x08000000>,
-				 <&rcc STM32_CLOCK_BUS_AHB1 0x10000000>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 25U)>,
+				 <&rcc STM32_CLOCK(AHB1, 26U)>,
+				 <&rcc STM32_CLOCK(AHB1, 27U)>,
+				 <&rcc STM32_CLOCK(AHB1, 28U)>;
 			status = "disabled";
 		};
 	};

dts/arm/st/f4/stm32f410.dtsi

@@ -20,7 +20,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40003800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
 			interrupts = <36 5>;
 			status = "disabled";
 		};
@@ -30,7 +30,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40015000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 20U)>;
 			interrupts = <85 5>;
 			status = "disabled";
 		};
@@ -40,7 +40,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40013000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 12U)>;
 			interrupts = <35 5>;
 			dmas = <&dma2 3 3 0x400 0x3
 				&dma2 2 3 0x400 0x3>;
@@ -53,7 +53,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40003800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
 			interrupts = <36 5>;
 			dmas = <&dma1 4 0 0x400 0x3
 				&dma1 3 0 0x400 0x3>;
@@ -66,7 +66,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40015000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 20U)>;
 			interrupts = <85 5>;
 			dmas = <&dma2 6 7 0x400 0x3
 				&dma2 5 7 0x400 0x3>;
@@ -77,7 +77,7 @@
 		timers6: timers@40001000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40001000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
+			clocks = <&rcc STM32_CLOCK(APB1, 4U)>;
 			resets = <&rctl STM32_RESET(APB1, 4U)>;
 			interrupts = <54 0>;
 			interrupt-names = "global";
@@ -93,7 +93,7 @@
 		dac1: dac@40007400 {
 			compatible = "st,stm32-dac";
 			reg = <0x40007400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 29U)>;
 			status = "disabled";
 			#io-channel-cells = <1>;
 		};
@@ -102,7 +102,7 @@
 			compatible = "st,stm32-rng";
 			reg = <0x40080000 0x400>;
 			interrupts = <80 0>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x80000000>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 31U)>;
 			status = "disabled";
 		};
 	};

dts/arm/st/f4/stm32f411.dtsi

@@ -15,7 +15,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40015000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 20U)>;
 			interrupts = <85 5>;
 			status = "disabled";
 		};
@@ -25,7 +25,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40013000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 12U)>;
 			interrupts = <35 5>;
 			dmas = <&dma2 3 3 0x400 0x3
 				&dma2 2 3 0x400 0x3>;
@@ -38,7 +38,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40013400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 13U)>;
 			interrupts = <84 5>;
 			dmas = <&dma2 1 4 0x400 0x3
 				&dma2 0 4 0x400 0x3>;
@@ -51,7 +51,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40015000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 20U)>;
 			interrupts = <85 5>;
 			dmas = <&dma2 6 7 0x400 0x3
 				&dma2 5 7 0x400 0x3>;

dts/arm/st/f4/stm32f412.dtsi

@@ -29,7 +29,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x40021400 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000020>;
+				clocks = <&rcc STM32_CLOCK(AHB1, 5U)>;
 			};
 
 			gpiog: gpio@40021800 {
@@ -37,14 +37,14 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x40021800 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000040>;
+				clocks = <&rcc STM32_CLOCK(AHB1, 6U)>;
 			};
 		};
 
 		usart3: serial@40004800 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40004800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
 			resets = <&rctl STM32_RESET(APB1, 18U)>;
 			interrupts = <39 0>;
 			status = "disabled";
@@ -55,7 +55,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40003c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
 			interrupts = <51 5>;
 			status = "disabled";
 		};
@@ -65,7 +65,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40013400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 13U)>;
 			interrupts = <84 5>;
 			status = "disabled";
 		};
@@ -75,7 +75,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40013400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 13U)>;
 			interrupts = <84 5>;
 			dmas = <&dma2 1 4 0x400 0x3
 				&dma2 0 4 0x400 0x3>;
@@ -86,7 +86,7 @@
 		timers7: timers@40001400 {
 			compatible = "st,stm32-timers";
 			reg = <0x40001400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
+			clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
 			resets = <&rctl STM32_RESET(APB1, 5U)>;
 			interrupts = <55 0>;
 			interrupt-names = "global";
@@ -102,7 +102,7 @@
 		timers8: timers@40010400 {
 			compatible = "st,stm32-timers";
 			reg = <0x40010400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000002>;
+			clocks = <&rcc STM32_CLOCK(APB2, 1U)>;
 			resets = <&rctl STM32_RESET(APB2, 1U)>;
 			interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
 			interrupt-names = "brk", "up", "trgcom", "cc";
@@ -125,7 +125,7 @@
 		timers12: timers@40001800 {
 			compatible = "st,stm32-timers";
 			reg = <0x40001800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000040>;
+			clocks = <&rcc STM32_CLOCK(APB1, 6U)>;
 			resets = <&rctl STM32_RESET(APB1, 6U)>;
 			interrupts = <43 0>;
 			interrupt-names = "global";
@@ -147,7 +147,7 @@
 		timers13: timers@40001c00 {
 			compatible = "st,stm32-timers";
 			reg = <0x40001c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000080>;
+			clocks = <&rcc STM32_CLOCK(APB1, 7U)>;
 			resets = <&rctl STM32_RESET(APB1, 7U)>;
 			interrupts = <44 0>;
 			interrupt-names = "global";
@@ -169,7 +169,7 @@
 		timers14: timers@40002000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40002000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000100>;
+			clocks = <&rcc STM32_CLOCK(APB1, 8U)>;
 			resets = <&rctl STM32_RESET(APB1, 8U)>;
 			interrupts = <45 0>;
 			interrupt-names = "global";
@@ -192,7 +192,7 @@
 			compatible = "st,stm32-rng";
 			reg = <0x50060800 0x400>;
 			interrupts = <80 0>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000040>;
+			clocks = <&rcc STM32_CLOCK(AHB2, 6U)>;
 			status = "disabled";
 		};
 
@@ -201,7 +201,7 @@
 		};
 
 		sdmmc1: sdmmc@40012c00 {
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>,
+			clocks = <&rcc STM32_CLOCK(APB2, 11U)>,
 				 <&rcc STM32_SRC_SYSCLK SDIO_SEL(1)>;
 		};
 
@@ -211,7 +211,7 @@
 			#size-cells = <0x0>;
 			reg = <0xa0001000 0x400>;
 			interrupts = <92 0>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00000002>;
+			clocks = <&rcc STM32_CLOCK(AHB3, 1U)>;
 			status = "disabled";
 		};
 
@@ -220,7 +220,7 @@
 			reg = <0x40006400 0x400>;
 			interrupts = <19 0>, <20 0>, <21 0>, <22 0>;
 			interrupt-names = "TX", "RX0", "RX1", "SCE";
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 25U)>;
 			status = "disabled";
 		};
 
@@ -230,7 +230,7 @@
 			interrupts = <63 0>, <64 0>, <65 0>, <66 0>;
 			interrupt-names = "TX", "RX0", "RX1", "SCE";
 			/* also enabling clock for can1 (master instance) */
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x06000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 26U)>;
 			master-can-reg = <0x40006400>;
 			status = "disabled";
 		};

dts/arm/st/f4/stm32f413.dtsi

@@ -13,7 +13,7 @@
 		uart4: serial@40004c00 {
 			compatible ="st,stm32-uart";
 			reg = <0x40004c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
 			resets = <&rctl STM32_RESET(APB1, 19U)>;
 			interrupts = <52 0>;
 			status = "disabled";
@@ -22,7 +22,7 @@
 		uart5: serial@40005000 {
 			compatible = "st,stm32-uart";
 			reg = <0x40005000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
 			resets = <&rctl STM32_RESET(APB1, 20U)>;
 			interrupts = <53 0>;
 			status = "disabled";
@@ -31,7 +31,7 @@
 		uart7: serial@40007800 {
 			compatible = "st,stm32-uart";
 			reg = <0x40007800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x40000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 30U)>;
 			resets = <&rctl STM32_RESET(APB1, 30U)>;
 			interrupts = <82 0>;
 			status = "disabled";
@@ -40,7 +40,7 @@
 		uart8: serial@40007c00 {
 			compatible = "st,stm32-uart";
 			reg = <0x40007c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 31U)>;
 			resets = <&rctl STM32_RESET(APB1, 31U)>;
 			interrupts = <83 0>;
 			status = "disabled";
@@ -49,7 +49,7 @@
 		uart9: serial@40011800 {
 			compatible = "st,stm32-uart";
 			reg = <0x40011800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000040>;
+			clocks = <&rcc STM32_CLOCK(APB2, 6U)>;
 			resets = <&rctl STM32_RESET(APB2, 6U)>;
 			interrupts = <88 0>;
 			status = "disabled";
@@ -58,7 +58,7 @@
 		uart10: serial@40011c00 {
 			compatible = "st,stm32-uart";
 			reg = <0x40011c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000080>;
+			clocks = <&rcc STM32_CLOCK(APB2, 7U)>;
 			resets = <&rctl STM32_RESET(APB2, 7U)>;
 			interrupts = <89 0>;
 			status = "disabled";
@@ -67,7 +67,7 @@
 		dac1: dac@40007400 {
 			compatible = "st,stm32-dac";
 			reg = <0x40007400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 29U)>;
 			status = "disabled";
 			#io-channel-cells = <1>;
 		};
@@ -77,7 +77,7 @@
 			reg = <0x40006c00 0x400>;
 			interrupts = <74 0>, <75 0>, <76 0>, <77 0>;
 			interrupt-names = "TX", "RX0", "RX1", "SCE";
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x08000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 27U)>;
 			status = "disabled";
 		};
 	};

dts/arm/st/f4/stm32f415.dtsi

@@ -13,7 +13,7 @@
 		cryp: cryp@50060000 {
 			compatible = "st,stm32-cryp";
 			reg = <0x50060000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
+			clocks = <&rcc STM32_CLOCK(AHB2, 4U)>;
 			resets = <&rctl STM32_RESET(AHB2, 4U)>;
 			interrupts = <79 0>;
 			status = "disabled";

dts/arm/st/f4/stm32f417.dtsi

@@ -13,7 +13,7 @@
 		cryp: cryp@50060000 {
 			compatible = "st,stm32-cryp";
 			reg = <0x50060000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
+			clocks = <&rcc STM32_CLOCK(AHB2, 4U)>;
 			resets = <&rctl STM32_RESET(AHB2, 4U)>;
 			interrupts = <79 0>;
 			status = "disabled";

dts/arm/st/f4/stm32f423.dtsi

@@ -13,7 +13,7 @@
 		aes: aes@50060000 {
 			compatible = "st,stm32-aes";
 			reg = <0x50060000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
+			clocks = <&rcc STM32_CLOCK(AHB2, 4U)>;
 			resets = <&rctl STM32_RESET(AHB2, 4U)>;
 			interrupts = <79 0>;
 			status = "disabled";

dts/arm/st/f4/stm32f427.dtsi

@@ -20,7 +20,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x40022400 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000200>;
+				clocks = <&rcc STM32_CLOCK(AHB1, 9U)>;
 			};
 
 			gpiok: gpio@40022800 {
@@ -28,14 +28,14 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x40022800 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000400>;
+				clocks = <&rcc STM32_CLOCK(AHB1, 10U)>;
 			};
 		};
 
 		uart7: serial@40007800 {
 			compatible = "st,stm32-uart";
 			reg = <0x40007800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x40000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 30U)>;
 			resets = <&rctl STM32_RESET(APB1, 30U)>;
 			interrupts = <82 0>;
 			status = "disabled";
@@ -44,7 +44,7 @@
 		uart8: serial@40007c00 {
 			compatible = "st,stm32-uart";
 			reg = <0x40007c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 31U)>;
 			resets = <&rctl STM32_RESET(APB1, 31U)>;
 			interrupts = <83 0>;
 			status = "disabled";
@@ -55,7 +55,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40013400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 13U)>;
 			interrupts = <84 5>;
 			status = "disabled";
 		};
@@ -68,7 +68,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40015000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 20U)>;
 			interrupts = <85 5>;
 			status = "disabled";
 		};
@@ -81,7 +81,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40015400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00200000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 21U)>;
 			interrupts = <86 5>;
 			status = "disabled";
 		};
@@ -89,7 +89,7 @@
 		fmc: memory-controller@a0000000 {
 			compatible = "st,stm32-fmc";
 			reg = <0xa0000000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00000001>;
+			clocks = <&rcc STM32_CLOCK(AHB3, 0U)>;
 			status = "disabled";
 
 			sdram: sdram {

dts/arm/st/f4/stm32f429.dtsi

@@ -14,7 +14,7 @@
 		dac1: dac@40007400 {
 			compatible = "st,stm32-dac";
 			reg = <0x40007400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 29U)>;
 			status = "disabled";
 			#io-channel-cells = <1>;
 		};
@@ -24,7 +24,7 @@
 			reg = <0x40016800 0x200>;
 			interrupts = <88 0>, <89 0>;
 			interrupt-names = "ltdc", "ltdc_er";
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x04000000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 26U)>;
 			resets = <&rctl STM32_RESET(APB2, 26U)>;
 			status = "disabled";
 		};

dts/arm/st/f4/stm32f437.dtsi

@@ -14,7 +14,7 @@
 		cryp: cryp@50060000 {
 			compatible = "st,stm32-cryp";
 			reg = <0x50060000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
+			clocks = <&rcc STM32_CLOCK(AHB2, 4U)>;
 			resets = <&rctl STM32_RESET(AHB2, 4U)>;
 			interrupts = <79 0>;
 			status = "disabled";

dts/arm/st/f4/stm32f446.dtsi

@@ -23,7 +23,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40013000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 12U)>;
 			interrupts = <35 5>;
 			dmas = <&dma2 3 3 0x400 0x3
 				&dma2 2 3 0x400 0x3>;
@@ -34,7 +34,7 @@
 		usart3: serial@40004800 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40004800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
 			resets = <&rctl STM32_RESET(APB1, 18U)>;
 			interrupts = <39 0>;
 			status = "disabled";
@@ -43,7 +43,7 @@
 		uart4: serial@40004c00 {
 			compatible ="st,stm32-uart";
 			reg = <0x40004c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
 			resets = <&rctl STM32_RESET(APB1, 19U)>;
 			interrupts = <52 0>;
 			status = "disabled";
@@ -52,7 +52,7 @@
 		uart5: serial@40005000 {
 			compatible = "st,stm32-uart";
 			reg = <0x40005000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
 			resets = <&rctl STM32_RESET(APB1, 20U)>;
 			interrupts = <53 0>;
 			status = "disabled";
@@ -63,7 +63,7 @@
 			reg = <0x40006400 0x400>;
 			interrupts = <19 0>, <20 0>, <21 0>, <22 0>;
 			interrupt-names = "TX", "RX0", "RX1", "SCE";
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 25U)>;
 			status = "disabled";
 		};
 
@@ -73,14 +73,14 @@
 			interrupts = <63 0>, <64 0>, <65 0>, <66 0>;
 			interrupt-names = "TX", "RX0", "RX1", "SCE";
 			/* also enabling clock for can1 (master instance) */
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x06000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 26U)>;
 			master-can-reg = <0x40006400>;
 			status = "disabled";
 		};
 
 		usbotg_fs: usb@50000000 {
 			num-bidir-endpoints = <6>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000080>,
+			clocks = <&rcc STM32_CLOCK(AHB2, 7U)>,
 				 <&rcc STM32_SRC_PLL_Q CK48M_SEL(0)>;
 		};
 
@@ -93,7 +93,7 @@
 			ram-size = <4096>;
 			maximum-speed = "full-speed";
 			phys = <&otghs_fs_phy>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x20000000>,
+			clocks = <&rcc STM32_CLOCK(AHB1, 29U)>,
 				 <&rcc STM32_SRC_PLL_Q CK48M_SEL(0)>;
 			status = "disabled";
 		};
@@ -101,7 +101,7 @@
 		backup_sram: memory@40024000 {
 			compatible = "zephyr,memory-region", "st,stm32-backup-sram";
 			reg = <0x40024000 DT_SIZE_K(4)>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00040000>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 18U)>;
 			zephyr,memory-region = "BACKUP_SRAM";
 			status = "disabled";
 		};
@@ -109,7 +109,7 @@
 		adc2: adc@40012100 {
 			compatible = "st,stm32-adc";
 			reg = <0x40012100 0x050>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000200>;
+			clocks = <&rcc STM32_CLOCK(APB2, 9U)>;
 			interrupts = <18 0>;
 			status = "disabled";
 			#io-channel-cells = <1>;
@@ -125,7 +125,7 @@
 		adc3: adc@40012200 {
 			compatible = "st,stm32-adc";
 			reg = <0x40012200 0x050>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000400>;
+			clocks = <&rcc STM32_CLOCK(APB2, 10U)>;
 			interrupts = <18 0>;
 			status = "disabled";
 			#io-channel-cells = <1>;
@@ -141,7 +141,7 @@
 		dac1: dac@40007400 {
 			compatible = "st,stm32-dac";
 			reg = <0x40007400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 29U)>;
 			status = "disabled";
 			#io-channel-cells = <1>;
 		};
@@ -149,7 +149,7 @@
 		fmc: memory-controller@a0000000 {
 			compatible = "st,stm32-fmc";
 			reg = <0xa0000000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00000001>;
+			clocks = <&rcc STM32_CLOCK(AHB3, 0U)>;
 			status = "disabled";
 
 			sdram: sdram {

dts/arm/st/f4/stm32f469.dtsi

@@ -11,13 +11,13 @@
 		compatible = "st,stm32f469", "st,stm32f4", "simple-bus";
 
 		sdmmc1: sdmmc@40012c00 {
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>,
+			clocks = <&rcc STM32_CLOCK(APB2, 11U)>,
 				 <&rcc STM32_SRC_SYSCLK SDMMC_SEL(1)>;
 		};
 
 		usbotg_fs: usb@50000000 {
 			num-bidir-endpoints = <6>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000080>,
+			clocks = <&rcc STM32_CLOCK(AHB2, 7U)>,
 				 <&rcc STM32_SRC_PLL_Q CLK48M_SEL(0)>;
 		};
 

dts/arm/st/f7/stm32f7.dtsi

@@ -104,7 +104,7 @@
 		fmc: memory-controller@a0000000 {
 			compatible = "st,stm32-fmc";
 			reg = <0xa0000000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00000001>;
+			clocks = <&rcc STM32_CLOCK(AHB3, 0U)>;
 			status = "disabled";
 
 			sdram: sdram {
@@ -169,7 +169,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x40020000 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000001>;
+				clocks = <&rcc STM32_CLOCK(AHB1, 0U)>;
 			};
 
 			gpiob: gpio@40020400 {
@@ -177,7 +177,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x40020400 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000002>;
+				clocks = <&rcc STM32_CLOCK(AHB1, 1U)>;
 			};
 
 			gpioc: gpio@40020800 {
@@ -185,7 +185,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x40020800 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000004>;
+				clocks = <&rcc STM32_CLOCK(AHB1, 2U)>;
 			};
 
 			gpiod: gpio@40020C00 {
@@ -193,7 +193,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x40020C00 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000008>;
+				clocks = <&rcc STM32_CLOCK(AHB1, 3U)>;
 			};
 
 			gpioe: gpio@40021000 {
@@ -201,7 +201,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x40021000 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000010>;
+				clocks = <&rcc STM32_CLOCK(AHB1, 4U)>;
 			};
 
 			gpiof: gpio@40021400 {
@@ -209,7 +209,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x40021400 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000020>;
+				clocks = <&rcc STM32_CLOCK(AHB1, 5U)>;
 			};
 
 			gpiog: gpio@40021800 {
@@ -217,7 +217,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x40021800 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000040>;
+				clocks = <&rcc STM32_CLOCK(AHB1, 6U)>;
 			};
 
 			gpioh: gpio@40021C00 {
@@ -225,7 +225,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x40021C00 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000080>;
+				clocks = <&rcc STM32_CLOCK(AHB1, 7U)>;
 			};
 
 			gpioi: gpio@40022000 {
@@ -233,7 +233,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x40022000 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000100>;
+				clocks = <&rcc STM32_CLOCK(AHB1, 8U)>;
 			};
 		};
 
@@ -246,7 +246,7 @@
 		wwdg: watchdog@40002c00 {
 			compatible = "st,stm32-window-watchdog";
 			reg = <0x40002C00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
+			clocks = <&rcc STM32_CLOCK(APB1, 11U)>;
 			interrupts = <0 7>;
 			status = "disabled";
 		};
@@ -254,7 +254,7 @@
 		usart1: serial@40011000 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40011000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000010>;
+			clocks = <&rcc STM32_CLOCK(APB2, 4U)>;
 			resets = <&rctl STM32_RESET(APB2, 4U)>;
 			interrupts = <37 0>;
 			status = "disabled";
@@ -263,7 +263,7 @@
 		usart2: serial@40004400 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40004400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 17U)>;
 			resets = <&rctl STM32_RESET(APB1, 17U)>;
 			interrupts = <38 0>;
 			status = "disabled";
@@ -272,7 +272,7 @@
 		usart3: serial@40004800 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40004800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
 			resets = <&rctl STM32_RESET(APB1, 18U)>;
 			interrupts = <39 0>;
 			status = "disabled";
@@ -281,7 +281,7 @@
 		uart4: serial@40004c00 {
 			compatible ="st,stm32-uart";
 			reg = <0x40004c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
 			resets = <&rctl STM32_RESET(APB1, 19U)>;
 			interrupts = <52 0>;
 			status = "disabled";
@@ -290,7 +290,7 @@
 		uart5: serial@40005000 {
 			compatible = "st,stm32-uart";
 			reg = <0x40005000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
 			resets = <&rctl STM32_RESET(APB1, 20U)>;
 			interrupts = <53 0>;
 			status = "disabled";
@@ -299,7 +299,7 @@
 		usart6: serial@40011400 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40011400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
+			clocks = <&rcc STM32_CLOCK(APB2, 5U)>;
 			resets = <&rctl STM32_RESET(APB2, 5U)>;
 			interrupts = <71 0>;
 			status = "disabled";
@@ -308,7 +308,7 @@
 		uart7: serial@40007800 {
 			compatible = "st,stm32-uart";
 			reg = <0x40007800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x40000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 30U)>;
 			resets = <&rctl STM32_RESET(APB1, 30U)>;
 			interrupts = <82 0>;
 			status = "disabled";
@@ -317,7 +317,7 @@
 		uart8: serial@40007c00 {
 			compatible = "st,stm32-uart";
 			reg = <0x40007c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 31U)>;
 			resets = <&rctl STM32_RESET(APB1, 31U)>;
 			interrupts = <83 0>;
 			status = "disabled";
@@ -329,7 +329,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40005400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 21U)>;
 			interrupts = <31 0>, <32 0>;
 			interrupt-names = "event", "error";
 			status = "disabled";
@@ -341,7 +341,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40005800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
 			interrupts = <33 0>, <34 0>;
 			interrupt-names = "event", "error";
 			status = "disabled";
@@ -353,7 +353,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40005c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 23U)>;
 			interrupts = <72 0>, <73 0>;
 			interrupt-names = "event", "error";
 			status = "disabled";
@@ -364,7 +364,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40013000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 12U)>;
 			interrupts = <35 5>;
 			status = "disabled";
 		};
@@ -374,7 +374,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40003800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
 			interrupts = <36 5>;
 			status = "disabled";
 		};
@@ -384,7 +384,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40003c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
 			interrupts = <51 5>;
 			status = "disabled";
 		};
@@ -394,7 +394,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40013400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 13U)>;
 			interrupts = <84 5>;
 			status = "disabled";
 		};
@@ -404,7 +404,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40015000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 20U)>;
 			interrupts = <85 5>;
 			status = "disabled";
 		};
@@ -414,14 +414,14 @@
 			reg = <0x40006400 0x400>;
 			interrupts = <19 0>, <20 0>, <21 0>, <22 0>;
 			interrupt-names = "TX", "RX0", "RX1", "SCE";
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 25U)>;
 			status = "disabled";
 		};
 
 		timers1: timers@40010000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40010000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000001>;
+			clocks = <&rcc STM32_CLOCK(APB2, 0U)>;
 			resets = <&rctl STM32_RESET(APB2, 0U)>;
 			interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
 			interrupt-names = "brk", "up", "trgcom", "cc";
@@ -438,7 +438,7 @@
 		timers2: timers@40000000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40000000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
+			clocks = <&rcc STM32_CLOCK(APB1, 0U)>;
 			resets = <&rctl STM32_RESET(APB1, 0U)>;
 			interrupts = <28 0>;
 			interrupt-names = "global";
@@ -460,7 +460,7 @@
 		timers3: timers@40000400 {
 			compatible = "st,stm32-timers";
 			reg = <0x40000400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
+			clocks = <&rcc STM32_CLOCK(APB1, 1U)>;
 			resets = <&rctl STM32_RESET(APB1, 1U)>;
 			interrupts = <29 0>;
 			interrupt-names = "global";
@@ -482,7 +482,7 @@
 		timers4: timers@40000800 {
 			compatible = "st,stm32-timers";
 			reg = <0x40000800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
+			clocks = <&rcc STM32_CLOCK(APB1, 2U)>;
 			resets = <&rctl STM32_RESET(APB1, 2U)>;
 			interrupts = <30 0>;
 			interrupt-names = "global";
@@ -504,7 +504,7 @@
 		timers5: timers@40000c00 {
 			compatible = "st,stm32-timers";
 			reg = <0x40000c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
+			clocks = <&rcc STM32_CLOCK(APB1, 3U)>;
 			resets = <&rctl STM32_RESET(APB1, 3U)>;
 			interrupts = <50 0>;
 			interrupt-names = "global";
@@ -526,7 +526,7 @@
 		timers6: timers@40001000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40001000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
+			clocks = <&rcc STM32_CLOCK(APB1, 4U)>;
 			resets = <&rctl STM32_RESET(APB1, 4U)>;
 			interrupts = <54 0>;
 			interrupt-names = "global";
@@ -542,7 +542,7 @@
 		timers7: timers@40001400 {
 			compatible = "st,stm32-timers";
 			reg = <0x40001400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
+			clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
 			resets = <&rctl STM32_RESET(APB1, 5U)>;
 			interrupts = <55 0>;
 			interrupt-names = "global";
@@ -558,7 +558,7 @@
 		timers8: timers@40010400 {
 			compatible = "st,stm32-timers";
 			reg = <0x40010400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000002>;
+			clocks = <&rcc STM32_CLOCK(APB2, 1U)>;
 			resets = <&rctl STM32_RESET(APB2, 1U)>;
 			interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
 			interrupt-names = "brk", "up", "trgcom", "cc";
@@ -575,7 +575,7 @@
 		timers9: timers@40014000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40014000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00010000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 16U)>;
 			resets = <&rctl STM32_RESET(APB2, 16U)>;
 			interrupts = <24 0>;
 			interrupt-names = "global";
@@ -597,7 +597,7 @@
 		timers10: timers@40014400 {
 			compatible = "st,stm32-timers";
 			reg = <0x40014400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00020000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 17U)>;
 			resets = <&rctl STM32_RESET(APB2, 17U)>;
 			interrupts = <25 0>;
 			interrupt-names = "global";
@@ -619,7 +619,7 @@
 		timers11: timers@40014800 {
 			compatible = "st,stm32-timers";
 			reg = <0x40014800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00040000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 18U)>;
 			resets = <&rctl STM32_RESET(APB2, 18U)>;
 			interrupts = <26 0>;
 			interrupt-names = "global";
@@ -641,7 +641,7 @@
 		timers12: timers@40001800 {
 			compatible = "st,stm32-timers";
 			reg = <0x40001800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000040>;
+			clocks = <&rcc STM32_CLOCK(APB1, 6U)>;
 			resets = <&rctl STM32_RESET(APB1, 6U)>;
 			interrupts = <43 0>;
 			interrupt-names = "global";
@@ -663,7 +663,7 @@
 		timers13: timers@40001c00 {
 			compatible = "st,stm32-timers";
 			reg = <0x40001c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000080>;
+			clocks = <&rcc STM32_CLOCK(APB1, 7U)>;
 			resets = <&rctl STM32_RESET(APB1, 7U)>;
 			interrupts = <44 0>;
 			interrupt-names = "global";
@@ -685,7 +685,7 @@
 		timers14: timers@40002000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40002000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000100>;
+			clocks = <&rcc STM32_CLOCK(APB1, 8U)>;
 			resets = <&rctl STM32_RESET(APB1, 8U)>;
 			interrupts = <45 0>;
 			interrupt-names = "global";
@@ -713,7 +713,7 @@
 			ram-size = <1280>;
 			maximum-speed = "full-speed";
 			phys = <&otgfs_phy>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000080>,
+			clocks = <&rcc STM32_CLOCK(AHB2, 7U)>,
 				 <&rcc STM32_SRC_PLL_Q CK48M_SEL(0)>;
 			status = "disabled";
 		};
@@ -726,7 +726,7 @@
 			num-bidir-endpoints = <9>;
 			ram-size = <4096>;
 			maximum-speed = "full-speed";
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x20000000>,
+			clocks = <&rcc STM32_CLOCK(AHB1, 29U)>,
 				 <&rcc STM32_SRC_PLL_Q CK48M_SEL(0)>;
 			phys = <&otghs_fs_phy>;
 			status = "disabled";
@@ -736,7 +736,7 @@
 			compatible = "st,stm32-rtc";
 			reg = <0x40002800 0x300>;
 			interrupts = <41 0>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 28U)>;
 			prescaler = <32768>;
 			alarms-count = <2>;
 			alrm-exti-line = <17>;
@@ -752,7 +752,7 @@
 		adc1: adc@40012000 {
 			compatible = "st,stm32f4-adc", "st,stm32-adc";
 			reg = <0x40012000 0x50>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000100>;
+			clocks = <&rcc STM32_CLOCK(APB2, 8U)>;
 			interrupts = <18 0>;
 			status = "disabled";
 			#io-channel-cells = <1>;
@@ -768,7 +768,7 @@
 		adc2: adc@40012100 {
 			compatible = "st,stm32f4-adc", "st,stm32-adc";
 			reg = <0x40012100 0x50>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000200>;
+			clocks = <&rcc STM32_CLOCK(APB2, 9U)>;
 			interrupts = <18 0>;
 			status = "disabled";
 			#io-channel-cells = <1>;
@@ -784,7 +784,7 @@
 		adc3: adc@40012200 {
 			compatible = "st,stm32f4-adc", "st,stm32-adc";
 			reg = <0x40012200 0x50>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000400>;
+			clocks = <&rcc STM32_CLOCK(APB2, 10U)>;
 			interrupts = <18 0>;
 			status = "disabled";
 			#io-channel-cells = <1>;
@@ -800,7 +800,7 @@
 		dac1: dac@40007400 {
 			compatible = "st,stm32-dac";
 			reg = <0x40007400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 29U)>;
 			status = "disabled";
 			#io-channel-cells = <1>;
 		};
@@ -810,7 +810,7 @@
 			#dma-cells = <4>;
 			reg = <0x40026000 0x400>;
 			interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0 47 0>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x200000>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 21U)>;
 			status = "disabled";
 		};
 
@@ -819,7 +819,7 @@
 			#dma-cells = <4>;
 			reg = <0x40026400 0x400>;
 			interrupts = <56 0 57 0 58 0 59 0 60 0 68 0 69 0 70 0>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x400000>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 22U)>;
 			st,mem2mem;
 			status = "disabled";
 		};
@@ -828,7 +828,7 @@
 			compatible = "st,stm32-rng";
 			reg = <0x50060800 0x400>;
 			interrupts = <80 0>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000040>,
+			clocks = <&rcc STM32_CLOCK(AHB2, 6U)>,
 				 <&rcc STM32_SRC_PLL_Q CK48M_SEL(0)>;
 			status = "disabled";
 		};
@@ -836,7 +836,7 @@
 		sdmmc1: sdmmc@40012c00 {
 			compatible = "st,stm32-sdmmc";
 			reg = <0x40012c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>,
+			clocks = <&rcc STM32_CLOCK(APB2, 11U)>,
 				 <&rcc STM32_SRC_PLL_Q SDMMC1_SEL(0)>;
 			resets = <&rctl STM32_RESET(APB2, 11U)>;
 			interrupts = <49 0>;
@@ -846,7 +846,7 @@
 		backup_sram: memory@40024000 {
 			compatible = "zephyr,memory-region", "st,stm32-backup-sram";
 			reg = <0x40024000 DT_SIZE_K(4)>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00040000>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 18U)>;
 			zephyr,memory-region = "BACKUP_SRAM";
 			status = "disabled";
 		};
@@ -857,7 +857,7 @@
 			#size-cells = <0x0>;
 			reg = <0xa0001000 0x34>;
 			interrupts = <92 0>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x2>;
+			clocks = <&rcc STM32_CLOCK(AHB3, 1U)>;
 			status = "disabled";
 		};
 	};

dts/arm/st/f7/stm32f722.dtsi

@@ -35,7 +35,7 @@
 		sdmmc2: sdmmc@40011c00 {
 			compatible = "st,stm32-sdmmc";
 			reg = <0x40011c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000080>,
+			clocks = <&rcc STM32_CLOCK(APB2, 7U)>,
 				<&rcc STM32_SRC_PLL_Q SDMMC2_SEL(0)>;
 			resets = <&rctl STM32_RESET(APB2, 7U)>;
 			interrupts = <103 0>;

dts/arm/st/f7/stm32f745.dtsi

@@ -32,7 +32,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x40022400 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000200>;
+				clocks = <&rcc STM32_CLOCK(AHB1, 9U)>;
 			};
 
 			gpiok: gpio@40022800 {
@@ -40,7 +40,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x40022800 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000400>;
+				clocks = <&rcc STM32_CLOCK(AHB1, 10U)>;
 			};
 		};
 
@@ -50,7 +50,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40006000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x01000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 24U)>;
 			interrupts = <95 0>, <96 0>;
 			interrupt-names = "event", "error";
 			status = "disabled";
@@ -61,7 +61,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40015400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00200000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 21U)>;
 			interrupts = <86 5>;
 			status = "disabled";
 		};
@@ -71,7 +71,7 @@
 			reg = <0x40006800 0x400>;
 			interrupts = <63 0>, <64 0>, <65 0>, <66 0>;
 			interrupt-names = "TX", "RX0", "RX1", "SCE";
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x04000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 26U)>;
 			status = "disabled";
 		};
 
@@ -81,10 +81,10 @@
 			interrupts = <61 0>;
 			clock-names = "stmmaceth", "mac-clk-tx",
 				      "mac-clk-rx", "mac-clk-ptp";
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x02000000>,
-				 <&rcc STM32_CLOCK_BUS_AHB1 0x04000000>,
-				 <&rcc STM32_CLOCK_BUS_AHB1 0x08000000>,
-				 <&rcc STM32_CLOCK_BUS_AHB1 0x10000000>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 25U)>,
+				 <&rcc STM32_CLOCK(AHB1, 26U)>,
+				 <&rcc STM32_CLOCK(AHB1, 27U)>,
+				 <&rcc STM32_CLOCK(AHB1, 28U)>;
 			status = "disabled";
 		};
 	};

dts/arm/st/f7/stm32f746.dtsi

@@ -16,7 +16,7 @@
 			reg = <0x40016800 0x200>;
 			interrupts = <88 0>, <89 0>;
 			interrupt-names = "ltdc", "ltdc_err";
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x04000000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 26U)>;
 			resets = <&rctl STM32_RESET(APB2, 26U)>;
 			status = "disabled";
 		};

dts/arm/st/f7/stm32f765.dtsi

@@ -34,7 +34,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x40022400 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000200>;
+				clocks = <&rcc STM32_CLOCK(AHB1, 9U)>;
 			};
 
 			gpiok: gpio@40022800 {
@@ -42,7 +42,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x40022800 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000400>;
+				clocks = <&rcc STM32_CLOCK(AHB1, 10U)>;
 			};
 		};
 
@@ -52,7 +52,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40006000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x01000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 24U)>;
 			interrupts = <95 0>, <96 0>;
 			interrupt-names = "event", "error";
 			status = "disabled";
@@ -63,7 +63,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40015400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00200000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 21U)>;
 			interrupts = <86 5>;
 			status = "disabled";
 		};
@@ -74,17 +74,17 @@
 			interrupts = <61 0>;
 			clock-names = "stmmaceth", "mac-clk-tx",
 				      "mac-clk-rx", "mac-clk-ptp";
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x02000000>,
-				 <&rcc STM32_CLOCK_BUS_AHB1 0x04000000>,
-				 <&rcc STM32_CLOCK_BUS_AHB1 0x08000000>,
-				 <&rcc STM32_CLOCK_BUS_AHB1 0x10000000>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 25U)>,
+				 <&rcc STM32_CLOCK(AHB1, 26U)>,
+				 <&rcc STM32_CLOCK(AHB1, 27U)>,
+				 <&rcc STM32_CLOCK(AHB1, 28U)>;
 			status = "disabled";
 		};
 
 		sdmmc2: sdmmc@40011c00 {
 			compatible = "st,stm32-sdmmc";
 			reg = <0x40011c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000080>,
+			clocks = <&rcc STM32_CLOCK(APB2, 7U)>,
 				 <&rcc STM32_SRC_PLL_Q SDMMC2_SEL(0)>;
 			resets = <&rctl STM32_RESET(APB2, 7U)>;
 			interrupts = <103 0>;

dts/arm/st/f7/stm32f767.dtsi

@@ -17,7 +17,7 @@
 			reg = <0x40016800 0x200>;
 			interrupts = <88 0>, <89 0>;
 			interrupt-names = "ltdc", "ltdc_err";
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x04000000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 26U)>;
 			resets = <&rctl STM32_RESET(APB2, 26U)>;
 			status = "disabled";
 		};

dts/arm/st/g0/stm32g0.dtsi

@@ -98,7 +98,7 @@
 			compatible = "st,stm32-flash-controller", "st,stm32g0-flash-controller";
 			reg = <0x40022000 0x400>;
 			interrupts = <3 0>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000100>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 8U)>;
 
 			#address-cells = <1>;
 			#size-cells = <1>;
@@ -147,7 +147,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x50000000 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000001>;
+				clocks = <&rcc STM32_CLOCK(IOP, 0U)>;
 			};
 
 			gpiob: gpio@50000400 {
@@ -155,7 +155,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x50000400 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000002>;
+				clocks = <&rcc STM32_CLOCK(IOP, 1U)>;
 			};
 
 			gpioc: gpio@50000800 {
@@ -163,7 +163,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x50000800 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000004>;
+				clocks = <&rcc STM32_CLOCK(IOP, 2U)>;
 			};
 
 			gpiod: gpio@50000c00 {
@@ -171,7 +171,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x50000c00 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000008>;
+				clocks = <&rcc STM32_CLOCK(IOP, 3U)>;
 			};
 
 			gpiof: gpio@50001400 {
@@ -179,7 +179,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x50001400 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000020>;
+				clocks = <&rcc STM32_CLOCK(IOP, 5U)>;
 			};
 		};
 
@@ -187,7 +187,7 @@
 			compatible = "st,stm32-rtc";
 			reg = <0x40002800 0x400>;
 			interrupts = <2 0>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000400>;
+			clocks = <&rcc STM32_CLOCK(APB1, 10U)>;
 			prescaler = <32768>;
 			alarms-count = <2>;
 			alrm-exti-line = <19>;
@@ -215,7 +215,7 @@
 		wwdg: watchdog@40002c00 {
 			compatible = "st,stm32-window-watchdog";
 			reg = <0x40002C00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
+			clocks = <&rcc STM32_CLOCK(APB1, 11U)>;
 			interrupts = <0 2>;
 			status = "disabled";
 		};
@@ -223,7 +223,7 @@
 		usart1: serial@40013800 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40013800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00004000>;
+			clocks = <&rcc STM32_CLOCK(APB1_2, 14U)>;
 			resets = <&rctl STM32_RESET(APB1H, 14U)>;
 			interrupts = <27 0>;
 			status = "disabled";
@@ -232,7 +232,7 @@
 		usart2: serial@40004400 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40004400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 17U)>;
 			resets = <&rctl STM32_RESET(APB1L, 17U)>;
 			interrupts = <28 0>;
 			status = "disabled";
@@ -240,7 +240,7 @@
 
 		lptim1: timers@40007c00 {
 			compatible = "st,stm32-lptim";
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 31U)>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40007c00 0x400>;
@@ -252,7 +252,7 @@
 		timers1: timers@40012c00 {
 			compatible = "st,stm32-timers";
 			reg = <0x40012C00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000800>;
+			clocks = <&rcc STM32_CLOCK(APB1_2, 11U)>;
 			resets = <&rctl STM32_RESET(APB1H, 11U)>;
 			interrupts = <13 0>, <14 0>;
 			interrupt-names = "brk_up_trg_com", "cc";
@@ -274,7 +274,7 @@
 		timers3: timers@40000400 {
 			compatible = "st,stm32-timers";
 			reg = <0x40000400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
+			clocks = <&rcc STM32_CLOCK(APB1, 1U)>;
 			resets = <&rctl STM32_RESET(APB1L, 1U)>;
 			interrupts = <16 0>;
 			interrupt-names = "global";
@@ -296,7 +296,7 @@
 		timers14: timers@40002000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40002000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00008000>;
+			clocks = <&rcc STM32_CLOCK(APB1_2, 15U)>;
 			resets = <&rctl STM32_RESET(APB1H, 15U)>;
 			interrupts = <19 0>;
 			interrupt-names = "global";
@@ -318,7 +318,7 @@
 		timers16: timers@40014400 {
 			compatible = "st,stm32-timers";
 			reg = <0x40014400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00020000>;
+			clocks = <&rcc STM32_CLOCK(APB1_2, 17U)>;
 			resets = <&rctl STM32_RESET(APB1H, 17U)>;
 			interrupts = <21 0>;
 			interrupt-names = "global";
@@ -340,7 +340,7 @@
 		timers17: timers@40014800 {
 			compatible = "st,stm32-timers";
 			reg = <0x40014800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00040000>;
+			clocks = <&rcc STM32_CLOCK(APB1_2, 18U)>;
 			resets = <&rctl STM32_RESET(APB1H, 18U)>;
 			interrupts = <22 0>;
 			interrupt-names = "global";
@@ -365,7 +365,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40005400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 21U)>;
 			interrupts = <23 0>;
 			interrupt-names = "combined";
 			status = "disabled";
@@ -377,7 +377,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40005800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
 			interrupts = <24 0>;
 			interrupt-names = "combined";
 			status = "disabled";
@@ -388,7 +388,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40013000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00001000>;
+			clocks = <&rcc STM32_CLOCK(APB1_2, 12U)>;
 			interrupts = <25 0>;
 			status = "disabled";
 		};
@@ -398,7 +398,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40003800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
 			interrupts = <26 0>;
 			status = "disabled";
 		};
@@ -406,7 +406,7 @@
 		adc1: adc@40012400 {
 			compatible = "st,stm32-adc";
 			reg = <0x40012400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00100000>;
+			clocks = <&rcc STM32_CLOCK(APB1_2, 20U)>;
 			interrupts = <12 0>;
 			status = "disabled";
 			#io-channel-cells = <1>;
@@ -430,7 +430,7 @@
 			#dma-cells = <3>;
 			reg = <0x40020000 0x400>;
 			interrupts = <9 0 10 0 10 0 11 0 11 0>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 0U)>;
 			dma-requests = <5>;
 			dma-offset = <0>;
 			status = "disabled";

dts/arm/st/g0/stm32g031.dtsi

@@ -14,7 +14,7 @@
 		lpuart1: serial@40008000 {
 			compatible = "st,stm32-lpuart", "st,stm32-uart";
 			reg = <0x40008000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
 			resets = <&rctl STM32_RESET(APB1L, 20U)>;
 			interrupts = <29 0>;
 			status = "disabled";
@@ -23,7 +23,7 @@
 		timers2: timers@40000000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40000000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
+			clocks = <&rcc STM32_CLOCK(APB1, 0U)>;
 			resets = <&rctl STM32_RESET(APB1L, 0U)>;
 			interrupts = <15 0>;
 			interrupt-names = "global";

dts/arm/st/g0/stm32g050.dtsi

@@ -13,7 +13,7 @@
 		timers6: timers@40001000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40001000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
+			clocks = <&rcc STM32_CLOCK(APB1, 4U)>;
 			resets = <&rctl STM32_RESET(APB1L, 4U)>;
 			interrupts = <17 0>;
 			interrupt-names = "global";
@@ -24,7 +24,7 @@
 		timers7: timers@40001400 {
 			compatible = "st,stm32-timers";
 			reg = <0x40001400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
+			clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
 			resets = <&rctl STM32_RESET(APB1L, 5U)>;
 			interrupts = <18 0>;
 			interrupt-names = "global";

dts/arm/st/g0/stm32g051.dtsi

@@ -13,7 +13,7 @@
 		timers6: timers@40001000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40001000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
+			clocks = <&rcc STM32_CLOCK(APB1, 4U)>;
 			resets = <&rctl STM32_RESET(APB1L, 4U)>;
 			interrupts = <17 0>;
 			interrupt-names = "global";
@@ -28,7 +28,7 @@
 		timers7: timers@40001400 {
 			compatible = "st,stm32-timers";
 			reg = <0x40001400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
+			clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
 			resets = <&rctl STM32_RESET(APB1L, 5U)>;
 			interrupts = <18 0>;
 			interrupt-names = "global";
@@ -44,7 +44,7 @@
 		timers15: timers@40014000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40014000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00010000>;
+			clocks = <&rcc STM32_CLOCK(APB1_2, 16U)>;
 			resets = <&rctl STM32_RESET(APB1H, 16U)>;
 			interrupts = <20 0>;
 			interrupt-names = "global";
@@ -66,7 +66,7 @@
 		dac1: dac@40007400 {
 			compatible = "st,stm32-dac";
 			reg = <0x40007400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 29U)>;
 			status = "disabled";
 			#io-channel-cells = <1>;
 		};

dts/arm/st/g0/stm32g070.dtsi

@@ -14,7 +14,7 @@
 		usart3: serial@40004800 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40004800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
 			resets = <&rctl STM32_RESET(APB1L, 18U)>;
 			interrupts = <29 0>;
 			status = "disabled";
@@ -23,7 +23,7 @@
 		usart4: serial@40004c00 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40004c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
 			resets = <&rctl STM32_RESET(APB1L, 19U)>;
 			interrupts = <29 0>;
 			status = "disabled";
@@ -32,7 +32,7 @@
 		timers15: timers@40014000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40014000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00010000>;
+			clocks = <&rcc STM32_CLOCK(APB1_2, 16U)>;
 			resets = <&rctl STM32_RESET(APB1H, 16U)>;
 			interrupts = <20 0>;
 			interrupt-names = "global";

dts/arm/st/g0/stm32g071.dtsi

@@ -15,7 +15,7 @@
 		usart3: serial@40004800 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40004800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
 			resets = <&rctl STM32_RESET(APB1L, 18U)>;
 			interrupts = <29 0>;
 			status = "disabled";
@@ -24,7 +24,7 @@
 		usart4: serial@40004c00 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40004c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
 			resets = <&rctl STM32_RESET(APB1L, 19U)>;
 			interrupts = <29 0>;
 			status = "disabled";
@@ -37,7 +37,7 @@
 		ucpd1: ucpd@4000a000 {
 			compatible = "st,stm32-ucpd";
 			reg = <0x4000a000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 25U)>;
 			interrupts = <8 0>;
 			status = "disabled";
 		};
@@ -45,7 +45,7 @@
 		ucpd2: ucpd@4000a400 {
 			compatible = "st,stm32-ucpd";
 			reg = <0x4000a400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x04000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 26U)>;
 			interrupts = <8 0>;
 			status = "disabled";
 		};

dts/arm/st/g0/stm32g0_crypt.dtsi

@@ -13,7 +13,7 @@
 		aes: aes@40026000 {
 			compatible = "st,stm32-aes";
 			reg = <0x40026000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00010000>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 16U)>;
 			resets = <&rctl STM32_RESET(AHB1, 16U)>;
 			interrupts = <31 0>;
 			status = "disabled";
@@ -23,7 +23,7 @@
 			compatible = "st,stm32-rng";
 			reg = <0x40025000 0x400>;
 			interrupts = <31 1>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00040000>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 18U)>;
 			status = "disabled";
 		};
 	};

dts/arm/st/g0/stm32g0b0.dtsi

@@ -16,14 +16,14 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x50001000 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000010>;
+				clocks = <&rcc STM32_CLOCK(IOP, 4U)>;
 			};
 		};
 
 		usart5: serial@40005000 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40005000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000100>;
+			clocks = <&rcc STM32_CLOCK(APB1, 8U)>;
 			resets = <&rctl STM32_RESET(APB1L, 8U)>;
 			interrupts = <29 0>;
 			status = "disabled";
@@ -32,7 +32,7 @@
 		usart6: serial@40013c00 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40013c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000200>;
+			clocks = <&rcc STM32_CLOCK(APB1, 9U)>;
 			resets = <&rctl STM32_RESET(APB1L, 9U)>;
 			interrupts = <29 0>;
 			status = "disabled";
@@ -41,7 +41,7 @@
 		timers4: timers@40000800 {
 			compatible = "st,stm32-timers";
 			reg = <0x40000800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
+			clocks = <&rcc STM32_CLOCK(APB1, 2U)>;
 			resets = <&rctl STM32_RESET(APB1L, 2U)>;
 			interrupts = <16 0>;
 			interrupt-names = "global";
@@ -61,7 +61,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40008800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 23U)>;
 			interrupts = <24 0>;
 			interrupt-names = "combined";
 			status = "disabled";
@@ -72,7 +72,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40003c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
 			interrupts = <26 3>;
 			status = "disabled";
 		};
@@ -82,7 +82,7 @@
 			#dma-cells = <3>;
 			reg = <0x40020400 0x400>;
 			interrupts = <11 0 11 0 11 0 11 0 11 0>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 1U)>;
 			dma-requests = <5>;
 			dma-offset = <7>;
 			status = "disabled";
@@ -100,7 +100,7 @@
 			num-bidir-endpoints = <8>;
 			ram-size = <2048>;
 			phys = <&usb_fs_phy>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00002000>,
+			clocks = <&rcc STM32_CLOCK(APB1, 13U)>,
 				 <&rcc STM32_SRC_HSI48 USB_SEL(0)>;
 			status = "disabled";
 		};

dts/arm/st/g0/stm32g0b1.dtsi

@@ -28,7 +28,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x50001000 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000010>;
+				clocks = <&rcc STM32_CLOCK(IOP, 4U)>;
 			};
 		};
 
@@ -38,7 +38,7 @@
 			reg-names = "m_can", "message_ram";
 			interrupts = <21 0>, <22 0>;
 			interrupt-names = "int0", "int1";
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00001000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 12U)>;
 			bosch,mram-cfg = <0x0 28 8 3 3 0 3 3>;
 			status = "disabled";
 		};
@@ -49,7 +49,7 @@
 			reg-names = "m_can", "message_ram";
 			interrupts = <21 0>, <22 0>;
 			interrupt-names = "int0", "int1";
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00001000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 12U)>;
 			bosch,mram-cfg = <0x0 28 8 3 3 0 3 3>;
 			status = "disabled";
 		};
@@ -57,7 +57,7 @@
 		usart5: serial@40005000 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40005000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000100>;
+			clocks = <&rcc STM32_CLOCK(APB1, 8U)>;
 			resets = <&rctl STM32_RESET(APB1L, 8U)>;
 			interrupts = <29 0>;
 			status = "disabled";
@@ -66,7 +66,7 @@
 		usart6: serial@40013c00 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40013c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000200>;
+			clocks = <&rcc STM32_CLOCK(APB1, 9U)>;
 			resets = <&rctl STM32_RESET(APB1L, 9U)>;
 			interrupts = <29 0>;
 			status = "disabled";
@@ -75,7 +75,7 @@
 		lpuart2: serial@40008400 {
 			compatible = "st,stm32-lpuart", "st,stm32-uart";
 			reg = <0x40008400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000080>;
+			clocks = <&rcc STM32_CLOCK(APB1, 7U)>;
 			resets = <&rctl STM32_RESET(APB1L, 7U)>;
 			interrupts = <28 0>;
 			status = "disabled";
@@ -84,7 +84,7 @@
 		timers4: timers@40000800 {
 			compatible = "st,stm32-timers";
 			reg = <0x40000800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
+			clocks = <&rcc STM32_CLOCK(APB1, 2U)>;
 			resets = <&rctl STM32_RESET(APB1L, 2U)>;
 			interrupts = <16 0>;
 			interrupt-names = "global";
@@ -104,7 +104,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40008800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 23U)>;
 			interrupts = <24 0>;
 			interrupt-names = "combined";
 			status = "disabled";
@@ -115,7 +115,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40003c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
 			interrupts = <26 3>;
 			status = "disabled";
 		};
@@ -125,7 +125,7 @@
 			#dma-cells = <3>;
 			reg = <0x40020400 0x400>;
 			interrupts = <11 0 11 0 11 0 11 0 11 0>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 1U)>;
 			dma-requests = <5>;
 			dma-offset = <7>;
 			status = "disabled";
@@ -144,7 +144,7 @@
 			num-bidir-endpoints = <8>;
 			ram-size = <2048>;
 			phys = <&usb_fs_phy>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00002000>,
+			clocks = <&rcc STM32_CLOCK(APB1, 13U)>,
 				 <&rcc STM32_SRC_HSI48 USB_SEL(0)>;
 			status = "disabled";
 		};

dts/arm/st/g4/stm32g4.dtsi

@@ -106,7 +106,7 @@
 		adc1: adc@50000000 {
 			compatible = "st,stm32-adc";
 			reg = <0x50000000 0x100>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00002000>;
+			clocks = <&rcc STM32_CLOCK(AHB2, 13U)>;
 			interrupts = <18 0>;
 			status = "disabled";
 			#io-channel-cells = <1>;
@@ -121,7 +121,7 @@
 		adc2: adc@50000100 {
 			compatible = "st,stm32-adc";
 			reg = <0x50000100 0x100>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00002000>;
+			clocks = <&rcc STM32_CLOCK(AHB2, 13U)>;
 			interrupts = <18 0>;
 			status = "disabled";
 			#io-channel-cells = <1>;
@@ -136,7 +136,7 @@
 		dac1: dac@50000800 {
 			compatible = "st,stm32-dac";
 			reg = <0x50000800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00010000>;
+			clocks = <&rcc STM32_CLOCK(AHB2, 16U)>;
 			status = "disabled";
 			#io-channel-cells = <1>;
 		};
@@ -144,7 +144,7 @@
 		dac3: dac@50001000 {
 			compatible = "st,stm32-dac";
 			reg = <0x50001000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00040000>;
+			clocks = <&rcc STM32_CLOCK(AHB2, 18U)>;
 			status = "disabled";
 			#io-channel-cells = <1>;
 		};
@@ -153,7 +153,7 @@
 			compatible = "st,stm32-flash-controller", "st,stm32g4-flash-controller";
 			reg = <0x40022000 0x400>;
 			interrupts = <3 0>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000100>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 8U)>;
 
 			#address-cells = <1>;
 			#size-cells = <1>;
@@ -206,7 +206,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x48000000 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000001>;
+				clocks = <&rcc STM32_CLOCK(AHB2, 0U)>;
 			};
 
 			gpiob: gpio@48000400 {
@@ -214,7 +214,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x48000400 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000002>;
+				clocks = <&rcc STM32_CLOCK(AHB2, 1U)>;
 			};
 
 			gpioc: gpio@48000800 {
@@ -222,7 +222,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x48000800 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000004>;
+				clocks = <&rcc STM32_CLOCK(AHB2, 2U)>;
 			};
 
 			gpiod: gpio@48000c00 {
@@ -230,7 +230,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x48000c00 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000008>;
+				clocks = <&rcc STM32_CLOCK(AHB2, 3U)>;
 			};
 
 			gpioe: gpio@48001000 {
@@ -238,7 +238,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x48001000 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
+				clocks = <&rcc STM32_CLOCK(AHB2, 4U)>;
 			};
 
 			gpiof: gpio@48001400 {
@@ -246,7 +246,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x48001400 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000020>;
+				clocks = <&rcc STM32_CLOCK(AHB2, 5U)>;
 			};
 
 			gpiog: gpio@48001800 {
@@ -254,14 +254,14 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x48001800 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000040>;
+				clocks = <&rcc STM32_CLOCK(AHB2, 6U)>;
 			};
 		};
 
 		usart1: serial@40013800 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40013800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 14U)>;
 			resets = <&rctl STM32_RESET(APB2, 14U)>;
 			interrupts = <37 0>;
 			status = "disabled";
@@ -270,7 +270,7 @@
 		usart2: serial@40004400 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40004400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 17U)>;
 			resets = <&rctl STM32_RESET(APB1L, 17U)>;
 			interrupts = <38 0>;
 			status = "disabled";
@@ -279,7 +279,7 @@
 		usart3: serial@40004800 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40004800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
 			resets = <&rctl STM32_RESET(APB1L, 18U)>;
 			interrupts = <39 0>;
 			status = "disabled";
@@ -288,7 +288,7 @@
 		uart4: serial@40004c00 {
 			compatible = "st,stm32-uart";
 			reg = <0x40004c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
 			resets = <&rctl STM32_RESET(APB1L, 19U)>;
 			interrupts = <52 0>;
 			status = "disabled";
@@ -297,7 +297,7 @@
 		lpuart1: serial@40008000 {
 			compatible = "st,stm32-lpuart", "st,stm32-uart";
 			reg = <0x40008000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000001>;
+			clocks = <&rcc STM32_CLOCK(APB1_2, 0U)>;
 			resets = <&rctl STM32_RESET(APB1H, 0U)>;
 			interrupts = <91 0>;
 			status = "disabled";
@@ -312,7 +312,7 @@
 		wwdg: watchdog@40002c00 {
 			compatible = "st,stm32-window-watchdog";
 			reg = <0x40002C00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
+			clocks = <&rcc STM32_CLOCK(APB1, 11U)>;
 			interrupts = <0 7>;
 			status = "disabled";
 		};
@@ -323,7 +323,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40005400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 21U)>;
 			interrupts = <31 0>, <32 0>;
 			interrupt-names = "event", "error";
 			status = "disabled";
@@ -335,7 +335,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40005800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
 			interrupts = <33 0>, <34 0>;
 			interrupt-names = "event", "error";
 			status = "disabled";
@@ -347,7 +347,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40007800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x40000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 30U)>;
 			interrupts = <92 0>, <93 0>;
 			interrupt-names = "event", "error";
 			status = "disabled";
@@ -359,7 +359,7 @@
 			#size-cells = <0>;
 			reg = <0x40013000 0x400>;
 			interrupts = <35 5>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 12U)>;
 			status = "disabled";
 		};
 
@@ -368,7 +368,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40003800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
 			interrupts = <36 5>;
 			status = "disabled";
 		};
@@ -378,7 +378,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40003c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
 			interrupts = <51 5>;
 			status = "disabled";
 		};
@@ -389,14 +389,14 @@
 			reg-names = "m_can", "message_ram";
 			interrupts = <21 0>, <22 0>;
 			interrupt-names = "int0", "int1";
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 25U)>;
 			bosch,mram-cfg = <0x0 28 8 3 3 0 3 3>;
 			status = "disabled";
 		};
 
 		lptim1: timers@40007c00 {
 			compatible = "st,stm32-lptim";
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 31U)>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40007c00 0x400>;
@@ -408,7 +408,7 @@
 		timers1: timers@40012c00 {
 			compatible = "st,stm32-timers";
 			reg = <0x40012c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>;
+			clocks = <&rcc STM32_CLOCK(APB2, 11U)>;
 			resets = <&rctl STM32_RESET(APB2, 11U)>;
 			interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
 			interrupt-names = "brk", "up", "trgcom", "cc";
@@ -425,7 +425,7 @@
 		timers2: timers@40000000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40000000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
+			clocks = <&rcc STM32_CLOCK(APB1, 0U)>;
 			resets = <&rctl STM32_RESET(APB1L, 0U)>;
 			interrupts = <28 0>;
 			interrupt-names = "global";
@@ -447,7 +447,7 @@
 		timers3: timers@40000400 {
 			compatible = "st,stm32-timers";
 			reg = <0x40000400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
+			clocks = <&rcc STM32_CLOCK(APB1, 1U)>;
 			resets = <&rctl STM32_RESET(APB1L, 1U)>;
 			interrupts = <29 0>;
 			interrupt-names = "global";
@@ -469,7 +469,7 @@
 		timers4: timers@40000800 {
 			compatible = "st,stm32-timers";
 			reg = <0x40000800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
+			clocks = <&rcc STM32_CLOCK(APB1, 2U)>;
 			resets = <&rctl STM32_RESET(APB1L, 2U)>;
 			interrupts = <30 0>;
 			interrupt-names = "global";
@@ -491,7 +491,7 @@
 		timers6: timers@40001000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40001000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
+			clocks = <&rcc STM32_CLOCK(APB1, 4U)>;
 			resets = <&rctl STM32_RESET(APB1L, 4U)>;
 			interrupts = <54 0>;
 			interrupt-names = "global";
@@ -502,7 +502,7 @@
 		timers7: timers@40001400 {
 			compatible = "st,stm32-timers";
 			reg = <0x40001400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
+			clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
 			resets = <&rctl STM32_RESET(APB1L, 5U)>;
 			interrupts = <55 0>;
 			interrupt-names = "global";
@@ -513,7 +513,7 @@
 		timers8: timers@40013400 {
 			compatible = "st,stm32-timers";
 			reg = <0x40013400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 13U)>;
 			resets = <&rctl STM32_RESET(APB2, 13U)>;
 			interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
 			interrupt-names = "brk", "up", "trgcom", "cc";
@@ -530,7 +530,7 @@
 		timers15: timers@40014000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40014000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00010000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 16U)>;
 			resets = <&rctl STM32_RESET(APB2, 16U)>;
 			interrupts = <24 0>;
 			interrupt-names = "global";
@@ -552,7 +552,7 @@
 		timers16: timers@40014400 {
 			compatible = "st,stm32-timers";
 			reg = <0x40014400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00020000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 17U)>;
 			resets = <&rctl STM32_RESET(APB2, 17U)>;
 			interrupts = <25 0>;
 			interrupt-names = "global";
@@ -574,7 +574,7 @@
 		timers17: timers@40014800 {
 			compatible = "st,stm32-timers";
 			reg = <0x40014800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00040000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 18U)>;
 			resets = <&rctl STM32_RESET(APB2, 18U)>;
 			interrupts = <26 0>;
 			interrupt-names = "global";
@@ -597,7 +597,7 @@
 			compatible = "st,stm32-rtc";
 			reg = <0x40002800 0x400>;
 			interrupts = <41 0>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000400>;
+			clocks = <&rcc STM32_CLOCK(APB1, 10U)>;
 			prescaler = <32768>;
 			alarms-count = <2>;
 			alrm-exti-line = <17>;
@@ -608,7 +608,7 @@
 			compatible = "st,stm32-rng";
 			reg = <0x50060800 0x400>;
 			interrupts = <90 0>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x04000000>;
+			clocks = <&rcc STM32_CLOCK(AHB2, 26U)>;
 			status = "disabled";
 		};
 
@@ -620,7 +620,7 @@
 			num-bidir-endpoints = <8>;
 			ram-size = <1024>;
 			phys = <&usb_fs_phy>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>,
+			clocks = <&rcc STM32_CLOCK(APB1, 23U)>,
 				 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
 			status = "disabled";
 		};
@@ -629,7 +629,7 @@
 			compatible = "st,stm32-dma-v2";
 			#dma-cells = <3>;
 			reg = <0x40020000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 0U)>;
 			dma-offset = <0>;
 			status = "disabled";
 		};
@@ -638,7 +638,7 @@
 			compatible = "st,stm32-dma-v2";
 			#dma-cells = <3>;
 			reg = <0x40020400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 1U)>;
 			status = "disabled";
 		};
 
@@ -647,7 +647,7 @@
 			#dma-cells = <3>;
 			reg = <0x40020800 0x400>;
 			interrupts = <94 0>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x4>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 2U)>;
 			dma-generators = <4>;
 			dma-requests= <111>;
 			status = "disabled";
@@ -656,7 +656,7 @@
 		ucpd1: ucpd@4000a000 {
 			compatible = "st,stm32-ucpd";
 			reg = <0x4000a000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
+			clocks = <&rcc STM32_CLOCK(APB1, 4U)>;
 			interrupts = <63 0>;
 			status = "disabled";
 		};

dts/arm/st/g4/stm32g473.dtsi

@@ -13,7 +13,7 @@
 		timers5: timers@40000c00 {
 			compatible = "st,stm32-timers";
 			reg = <0x40000c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
+			clocks = <&rcc STM32_CLOCK(APB1, 3U)>;
 			resets = <&rctl STM32_RESET(APB1L, 3U)>;
 			interrupts = <50 0>;
 			interrupt-names = "global";
@@ -30,7 +30,7 @@
 		adc4: adc@50000500 {
 			compatible = "st,stm32-adc";
 			reg = <0x50000500 0x100>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00004000>;
+			clocks = <&rcc STM32_CLOCK(AHB2, 14U)>;
 			interrupts = <61 0>;
 			status = "disabled";
 			#io-channel-cells = <1>;
@@ -45,7 +45,7 @@
 		adc5: adc@50000600 {
 			compatible = "st,stm32-adc";
 			reg = <0x50000600 0x100>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00004000>;
+			clocks = <&rcc STM32_CLOCK(AHB2, 14U)>;
 			interrupts = <62 0>;
 			status = "disabled";
 			#io-channel-cells = <1>;
@@ -62,7 +62,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40013c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00008000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 15U)>;
 			interrupts = <84 5>;
 			status = "disabled";
 		};
@@ -70,7 +70,7 @@
 		dac2: dac@50000c00 {
 			compatible = "st,stm32-dac";
 			reg = <0x50000c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00020000>;
+			clocks = <&rcc STM32_CLOCK(AHB2, 17U)>;
 			status = "disabled";
 			#io-channel-cells = <1>;
 		};
@@ -78,7 +78,7 @@
 		dac4: dac@50001400 {
 			compatible = "st,stm32-dac";
 			reg = <0x50001400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00080000>;
+			clocks = <&rcc STM32_CLOCK(AHB2, 19U)>;
 			status = "disabled";
 			#io-channel-cells = <1>;
 		};
@@ -89,7 +89,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40008400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000002>;
+			clocks = <&rcc STM32_CLOCK(APB1_2, 1U)>;
 			interrupts = <82 0>, <83 0>;
 			interrupt-names = "event", "error";
 			status = "disabled";
@@ -101,7 +101,7 @@
 			reg-names = "m_can", "message_ram";
 			interrupts = <88 0>, <89 0>;
 			interrupt-names = "int0", "int1";
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 25U)>;
 			bosch,mram-cfg = <0x6a0 28 8 3 3 0 3 3>;
 			status = "disabled";
 		};

dts/arm/st/g4/stm32g491.dtsi

@@ -16,7 +16,7 @@
 			reg-names = "m_can", "message_ram";
 			interrupts = <86 0>, <87 0>;
 			interrupt-names = "int0", "int1";
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 25U)>;
 			bosch,mram-cfg = <0x350 28 8 3 3 0 3 3>;
 			status = "disabled";
 		};
@@ -24,7 +24,7 @@
 		timers20: timers@40015000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40015000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 20U)>;
 			resets = <&rctl STM32_RESET(APB2, 20U)>;
 			interrupts = <77 0>, <78 0>, <79 0>, <80 0>;
 			interrupt-names = "brk", "up", "trgcom", "cc";
@@ -56,7 +56,7 @@
 		adc3: adc@50000400 {
 			compatible = "st,stm32-adc";
 			reg = <0x50000400 0x100>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00004000>;
+			clocks = <&rcc STM32_CLOCK(AHB2, 14U)>;
 			interrupts = <47 0>;
 			status = "disabled";
 			#io-channel-cells = <1>;
@@ -71,7 +71,7 @@
 		uart5: serial@40005000 {
 			compatible = "st,stm32-uart";
 			reg = <0x40005000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
 			resets = <&rctl STM32_RESET(APB1L, 20U)>;
 			interrupts = <53 0>;
 			status = "disabled";

dts/arm/st/h5/stm32h5.dtsi

@@ -132,7 +132,7 @@
 		backup_sram: memory@40036400 {
 			compatible = "zephyr,memory-region", "st,stm32-backup-sram";
 			reg = <0x40036400 DT_SIZE_K(2)>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x10000000>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 28U)>;
 			zephyr,memory-region = "BACKUP_SRAM";
 			status = "disabled";
 		};
@@ -190,7 +190,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x42020000 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000001>;
+				clocks = <&rcc STM32_CLOCK(AHB2, 0U)>;
 			};
 
 			gpiob: gpio@42020400 {
@@ -198,7 +198,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x42020400 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000002>;
+				clocks = <&rcc STM32_CLOCK(AHB2, 1U)>;
 			};
 
 			gpioc: gpio@42020800 {
@@ -206,7 +206,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x42020800 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000004>;
+				clocks = <&rcc STM32_CLOCK(AHB2, 2U)>;
 			};
 
 			gpiod: gpio@42020c00 {
@@ -214,7 +214,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x42020c00 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000008>;
+				clocks = <&rcc STM32_CLOCK(AHB2, 3U)>;
 			};
 
 			gpioh: gpio@42021c00 {
@@ -222,13 +222,13 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x42021c00 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000080>;
+				clocks = <&rcc STM32_CLOCK(AHB2, 7U)>;
 			};
 		};
 
 		lptim1: timers@44004400 {
 			compatible = "st,stm32-lptim";
-			clocks = <&rcc STM32_CLOCK_BUS_APB3 0x800>;
+			clocks = <&rcc STM32_CLOCK(APB3, 11U)>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x44004400 0x400>;
@@ -239,7 +239,7 @@
 
 		lptim2: timers@40009400 {
 			compatible = "st,stm32-lptim";
-			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x20>;
+			clocks = <&rcc STM32_CLOCK(APB1_2, 5U)>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40009400 0x400>;
@@ -251,7 +251,7 @@
 		usart1: serial@40013800 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40013800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 14U)>;
 			resets = <&rctl STM32_RESET(APB2, 14U)>;
 			interrupts = <58 0>;
 			status = "disabled";
@@ -260,7 +260,7 @@
 		usart2: serial@40004400 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40004400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 17U)>;
 			resets = <&rctl STM32_RESET(APB1L, 17U)>;
 			interrupts = <59 0>;
 			status = "disabled";
@@ -269,7 +269,7 @@
 		usart3: serial@40004800 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40004800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
 			resets = <&rctl STM32_RESET(APB1L, 18U)>;
 			interrupts = <60 0>;
 			status = "disabled";
@@ -278,7 +278,7 @@
 		lpuart1: serial@44002400 {
 			compatible = "st,stm32-lpuart", "st,stm32-uart";
 			reg = <0x44002400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000040>;
+			clocks = <&rcc STM32_CLOCK(APB3, 6U)>;
 			resets = <&rctl STM32_RESET(APB3, 6U)>;
 			interrupts = <63 0>;
 			status = "disabled";
@@ -293,7 +293,7 @@
 		wwdg: watchdog@40002c00 {
 			compatible = "st,stm32-window-watchdog";
 			reg = <0x40002c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
+			clocks = <&rcc STM32_CLOCK(APB1, 11U)>;
 			interrupts = <0 7>;
 			status = "disabled";
 		};
@@ -301,7 +301,7 @@
 		dac1: dac@42028400 {
 			compatible = "st,stm32-dac";
 			reg = <0x42028400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000800>;
+			clocks = <&rcc STM32_CLOCK(AHB2, 11U)>;
 			status = "disabled";
 			#io-channel-cells = <1>;
 		};
@@ -309,7 +309,7 @@
 		adc1: adc@42028000 {
 			compatible = "st,stm32-adc";
 			reg = <0x42028000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000400>;
+			clocks = <&rcc STM32_CLOCK(AHB2, 10U)>;
 			interrupts = <37 0>;
 			status = "disabled";
 			vref-mv = <3300>;
@@ -326,7 +326,7 @@
 			compatible = "st,stm32-rtc";
 			reg = <0x44007800 0x400>;
 			interrupts = <2 0>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00200000>;
+			clocks = <&rcc STM32_CLOCK(APB3, 21U)>;
 			prescaler = <32768>;
 			alarms-count = <2>;
 			alrm-exti-line = <17>;
@@ -336,7 +336,7 @@
 		timers1: timers@40012c00 {
 			compatible = "st,stm32-timers";
 			reg = <0x40012c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>;
+			clocks = <&rcc STM32_CLOCK(APB2, 11U)>;
 			resets = <&rctl STM32_RESET(APB2, 11U)>;
 			interrupts = <41 0>, <42 0>, <43 0>, <44 0>;
 			interrupt-names = "brk", "up", "trgcom", "cc";
@@ -352,7 +352,7 @@
 		timers2: timers@40000000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40000000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
+			clocks = <&rcc STM32_CLOCK(APB1, 0U)>;
 			resets = <&rctl STM32_RESET(APB1L, 0U)>;
 			interrupts = <45 0>;
 			interrupt-names = "global";
@@ -373,7 +373,7 @@
 		timers3: timers@40000400 {
 			compatible = "st,stm32-timers";
 			reg = <0x40000400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
+			clocks = <&rcc STM32_CLOCK(APB1, 1U)>;
 			resets = <&rctl STM32_RESET(APB1L, 1U)>;
 			interrupts = <46 0>;
 			interrupt-names = "global";
@@ -394,7 +394,7 @@
 		timers6: timers@40001000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40001000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
+			clocks = <&rcc STM32_CLOCK(APB1, 4U)>;
 			resets = <&rctl STM32_RESET(APB1L, 4U)>;
 			interrupts = <49 0>;
 			interrupt-names = "global";
@@ -415,7 +415,7 @@
 		timers7: timers@40001400 {
 			compatible = "st,stm32-timers";
 			reg = <0x40001400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
+			clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
 			resets = <&rctl STM32_RESET(APB1L, 5U)>;
 			interrupts = <50 0>;
 			interrupt-names = "global";
@@ -439,7 +439,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40005400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 21U)>;
 			interrupts = <51 0>, <52 0>;
 			interrupt-names = "event", "error";
 			status = "disabled";
@@ -451,7 +451,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40005800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
 			interrupts = <53 0>, <54 0>;
 			interrupt-names = "event", "error";
 			status = "disabled";
@@ -463,7 +463,7 @@
 			#size-cells = <0>;
 			reg = <0x40013000 0x400>;
 			interrupts = <55 5>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>,
+			clocks = <&rcc STM32_CLOCK(APB2, 12U)>,
 				 <&rcc STM32_SRC_PLL1_Q SPI1_SEL(0)>;
 			status = "disabled";
 		};
@@ -474,7 +474,7 @@
 			#size-cells = <0>;
 			reg = <0x40003800 0x400>;
 			interrupts = <56 5>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>,
+			clocks = <&rcc STM32_CLOCK(APB1, 14U)>,
 				 <&rcc STM32_SRC_PLL1_Q SPI2_SEL(0)>;
 			status = "disabled";
 		};
@@ -485,7 +485,7 @@
 			#size-cells = <0>;
 			reg = <0x40003c00 0x400>;
 			interrupts = <57 5>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>,
+			clocks = <&rcc STM32_CLOCK(APB1, 15U)>,
 				 <&rcc STM32_SRC_PLL1_Q SPI3_SEL(0)>;
 			status = "disabled";
 		};
@@ -496,7 +496,7 @@
 			reg-names = "m_can", "message_ram";
 			interrupts = <39 0>, <40 0>;
 			interrupt-names = "int0", "int1";
-			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000200>;
+			clocks = <&rcc STM32_CLOCK(APB1_2, 9U)>;
 			bosch,mram-cfg = <0x0 28 8 3 3 0 3 3>;
 			status = "disabled";
 		};
@@ -504,7 +504,7 @@
 		rng: rng@420c0800 {
 			compatible = "st,stm32-rng";
 			reg = <0x420c0800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00040000>;
+			clocks = <&rcc STM32_CLOCK(AHB2, 18U)>;
 			interrupts = <114 0>;
 			nist-config = <0xf00d00>;
 			health-test-config = <0xaac7>;
@@ -516,9 +516,9 @@
 			reg = <0x40028000 0x8000>;
 			interrupts = <106 0>;
 			clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00080000>,
-				 <&rcc STM32_CLOCK_BUS_AHB1 0x00100000>,
-				 <&rcc STM32_CLOCK_BUS_AHB1 0x00200000>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 19U)>,
+				 <&rcc STM32_CLOCK(AHB1, 20U)>,
+				 <&rcc STM32_CLOCK(AHB1, 21U)>;
 			status = "disabled";
 
 			mdio: mdio {
@@ -534,7 +534,7 @@
 			#dma-cells = <3>;
 			reg = <0x40020000 0x1000>;
 			interrupts = <27 0 28 0 29 0 30 0 31 0 32 0 33 0 34 0>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 0U)>;
 			dma-channels = <8>;
 			dma-requests = <140>;
 			dma-offset = <0>;
@@ -546,7 +546,7 @@
 			#dma-cells = <3>;
 			reg = <0x40021000 0x1000>;
 			interrupts = <90 0 91 0 92 0 93 0 94 0 95 0 96 0 97 0>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 1U)>;
 			dma-channels = <8>;
 			dma-requests = <140>;
 			dma-offset = <8>;
@@ -558,7 +558,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40013000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>,
+			clocks = <&rcc STM32_CLOCK(APB2, 12U)>,
 				<&rcc STM32_SRC_PLL1_Q SPI1_SEL(0)>;
 			dmas = <&gpdma1 0 7 (STM32_DMA_PERIPH_TX |STM32_DMA_16BITS | \
 					STM32_DMA_PRIORITY_HIGH)
@@ -574,7 +574,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40003800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>,
+			clocks = <&rcc STM32_CLOCK(APB1, 14U)>,
 				<&rcc STM32_SRC_PLL1_Q SPI2_SEL(0)>;
 			dmas = <&gpdma1 2 9 (STM32_DMA_PERIPH_TX | STM32_DMA_16BITS | \
 					STM32_DMA_PRIORITY_HIGH)
@@ -590,7 +590,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40003c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>,
+			clocks = <&rcc STM32_CLOCK(APB1, 15U)>,
 				<&rcc STM32_SRC_PLL1_Q SPI3_SEL(0)>;
 			dmas = <&gpdma1 4 11 (STM32_DMA_PERIPH_TX  | STM32_DMA_16BITS | \
 					STM32_DMA_PRIORITY_HIGH)
@@ -609,7 +609,7 @@
 			num-bidir-endpoints = <8>;
 			ram-size = <2048>;
 			phys = <&usb_fs_phy>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x01000000>,
+			clocks = <&rcc STM32_CLOCK(APB2, 24U)>,
 				 <&rcc STM32_SRC_HSI48 USB_SEL(3)>;
 			status = "disabled";
 		};
@@ -619,7 +619,7 @@
 			reg = <0x40008c00 0x400>;
 			interrupts = <113 0>;
 			interrupt-names = "digi_temp";
-			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000008>;
+			clocks = <&rcc STM32_CLOCK(APB1_2, 3U)>;
 			status = "disabled";
 		};
 	};

dts/arm/st/h5/stm32h533.dtsi

@@ -14,13 +14,13 @@
 			gpio-controller;
 			#gpio-cells = <2>;
 			reg = <0x42021400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000080>;
+			clocks = <&rcc STM32_CLOCK(AHB2, 7U)>;
 		};
 
 		fmc: memory-controller@47000400 {
 			compatible = "st,stm32-fmc";
 			reg = <0x47000400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00010000>;
+			clocks = <&rcc STM32_CLOCK(AHB4, 16U)>;
 			status = "disabled";
 		};
 	};

dts/arm/st/h5/stm32h562.dtsi

@@ -28,7 +28,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x42021000 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
+				clocks = <&rcc STM32_CLOCK(AHB2, 4U)>;
 			};
 
 			gpiof: gpio@42021400 {
@@ -36,7 +36,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x42021400 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000020>;
+				clocks = <&rcc STM32_CLOCK(AHB2, 5U)>;
 			};
 
 			gpiog: gpio@42021800 {
@@ -44,7 +44,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x42021800 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000040>;
+				clocks = <&rcc STM32_CLOCK(AHB2, 6U)>;
 			};
 
 			gpioi: gpio@42022000 {
@@ -52,7 +52,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x42022000 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000100>;
+				clocks = <&rcc STM32_CLOCK(AHB2, 8U)>;
 			};
 		};
 
@@ -62,7 +62,7 @@
 
 		lptim3: timers@44004800 {
 			compatible = "st,stm32-lptim";
-			clocks = <&rcc STM32_CLOCK_BUS_APB3 0x1000>;
+			clocks = <&rcc STM32_CLOCK(APB3, 12U)>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x44004800 0x400>;
@@ -73,7 +73,7 @@
 
 		lptim4: timers@44004c00 {
 			compatible = "st,stm32-lptim";
-			clocks = <&rcc STM32_CLOCK_BUS_APB3 0x2000>;
+			clocks = <&rcc STM32_CLOCK(APB3, 13U)>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x44004c00 0x400>;
@@ -84,7 +84,7 @@
 
 		lptim5: timers@44005000 {
 			compatible = "st,stm32-lptim";
-			clocks = <&rcc STM32_CLOCK_BUS_APB3 0x4000>;
+			clocks = <&rcc STM32_CLOCK(APB3, 14U)>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x44005000 0x400>;
@@ -95,7 +95,7 @@
 
 		lptim6: timers@44005400 {
 			compatible = "st,stm32-lptim";
-			clocks = <&rcc STM32_CLOCK_BUS_APB3 0x8000>;
+			clocks = <&rcc STM32_CLOCK(APB3, 15U)>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x44005400 0x400>;
@@ -107,7 +107,7 @@
 		uart4: serial@40004c00 {
 			compatible = "st,stm32-uart";
 			reg = <0x40004c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
 			resets = <&rctl STM32_RESET(APB1L, 19U)>;
 			interrupts = <61 0>;
 			status = "disabled";
@@ -116,7 +116,7 @@
 		uart5: serial@40005000 {
 			compatible = "st,stm32-uart";
 			reg = <0x40005000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
 			resets = <&rctl STM32_RESET(APB1L, 20U)>;
 			interrupts = <62 0>;
 			status = "disabled";
@@ -125,7 +125,7 @@
 		uart7: serial@40007800 {
 			compatible = "st,stm32-uart";
 			reg = <0x40007800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x40000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 30U)>;
 			resets = <&rctl STM32_RESET(APB1L, 30U)>;
 			interrupts = <98 0>;
 			status = "disabled";
@@ -134,7 +134,7 @@
 		uart8: serial@40007c00 {
 			compatible = "st,stm32-uart";
 			reg = <0x40007c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 31U)>;
 			resets = <&rctl STM32_RESET(APB1L, 31U)>;
 			interrupts = <99 0>;
 			status = "disabled";
@@ -143,7 +143,7 @@
 		uart9: serial@40008000 {
 			compatible = "st,stm32-uart";
 			reg = <0x40008000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000001>;
+			clocks = <&rcc STM32_CLOCK(APB1_2, 0U)>;
 			resets = <&rctl STM32_RESET(APB1H, 0U)>;
 			interrupts = <100 0>;
 			status = "disabled";
@@ -152,7 +152,7 @@
 		usart6: serial@40006400 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40006400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 25U)>;
 			resets = <&rctl STM32_RESET(APB1L, 25U)>;
 			interrupts = <85 0>;
 			status = "disabled";
@@ -161,7 +161,7 @@
 		usart10: serial@40006800 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40006800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x04000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 26U)>;
 			resets = <&rctl STM32_RESET(APB1L, 26U)>;
 			interrupts = <86 0>;
 			status = "disabled";
@@ -170,7 +170,7 @@
 		usart11: serial@40006c00 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40006c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x08000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 27U)>;
 			resets = <&rctl STM32_RESET(APB1L, 27U)>;
 			interrupts = <87 0>;
 			status = "disabled";
@@ -179,7 +179,7 @@
 		uart12: serial@40008400 {
 			compatible = "st,stm32-uart";
 			reg = <0x40008400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000002>;
+			clocks = <&rcc STM32_CLOCK(APB1_2, 1U)>;
 			resets = <&rctl STM32_RESET(APB1H, 1U)>;
 			interrupts = <101 0>;
 			status = "disabled";
@@ -191,7 +191,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x44002800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000080>;
+			clocks = <&rcc STM32_CLOCK(APB3, 7U)>;
 			interrupts = <80 0>, <81 0>;
 			interrupt-names = "event", "error";
 			status = "disabled";
@@ -203,7 +203,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x44002c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000100>;
+			clocks = <&rcc STM32_CLOCK(APB3, 8U)>;
 			interrupts = <125 0>, <126 0>;
 			interrupt-names = "event", "error";
 			status = "disabled";
@@ -215,7 +215,7 @@
 			#size-cells = <0>;
 			reg = <0x40014c00 0x400>;
 			interrupts = <82 5>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00080000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 19U)>;
 			status = "disabled";
 		};
 
@@ -225,7 +225,7 @@
 			#size-cells = <0>;
 			reg = <0x44002000 0x400>;
 			interrupts = <83 5>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000020>;
+			clocks = <&rcc STM32_CLOCK(APB3, 5U)>;
 			status = "disabled";
 		};
 
@@ -235,7 +235,7 @@
 			#size-cells = <0>;
 			reg = <0x40015000 0x400>;
 			interrupts = <84 5>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 20U)>;
 			status = "disabled";
 		};
 
@@ -244,7 +244,7 @@
 			reg = <0x47001400 0x400>;
 			interrupts = <78 0>;
 			clock-names = "xspix", "xspi-ker";
-			clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00100000>,
+			clocks = <&rcc STM32_CLOCK(AHB4, 20U)>,
 				<&rcc STM32_SRC_PLL1_Q OCTOSPI1_SEL(1)>;
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -254,7 +254,7 @@
 		adc2: adc@42028100 {
 			compatible = "st,stm32-adc";
 			reg = <0x42028100 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000400>;
+			clocks = <&rcc STM32_CLOCK(AHB2, 10U)>;
 			interrupts = <69 0>;
 			status = "disabled";
 			vref-mv = <3300>;
@@ -270,7 +270,7 @@
 		timers4: timers@40000800 {
 			compatible = "st,stm32-timers";
 			reg = <0x40000800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
+			clocks = <&rcc STM32_CLOCK(APB1, 2U)>;
 			resets = <&rctl STM32_RESET(APB1L, 2U)>;
 			interrupts = <47 0>;
 			interrupt-names = "global";
@@ -291,7 +291,7 @@
 		timers5: timers@40000c00 {
 			compatible = "st,stm32-timers";
 			reg = <0x40000c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
+			clocks = <&rcc STM32_CLOCK(APB1, 3U)>;
 			resets = <&rctl STM32_RESET(APB1L, 3U)>;
 			interrupts = <48 0>;
 			interrupt-names = "global";
@@ -312,7 +312,7 @@
 		timers12: timers@40001800 {
 			compatible = "st,stm32-timers";
 			reg = <0x40001800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000040>;
+			clocks = <&rcc STM32_CLOCK(APB1, 6U)>;
 			resets = <&rctl STM32_RESET(APB1L, 6U)>;
 			interrupts = <120 0>;
 			interrupt-names = "global";
@@ -333,7 +333,7 @@
 		timers13: timers@40001c00 {
 			compatible = "st,stm32-timers";
 			reg = <0x40001c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000080>;
+			clocks = <&rcc STM32_CLOCK(APB1, 7U)>;
 			resets = <&rctl STM32_RESET(APB1L, 7U)>;
 			interrupts = <121 0>;
 			interrupt-names = "global";
@@ -354,7 +354,7 @@
 		timers14: timers@40002000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40002000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000100>;
+			clocks = <&rcc STM32_CLOCK(APB1, 8U)>;
 			resets = <&rctl STM32_RESET(APB1L, 8U)>;
 			interrupts = <122 0>;
 			interrupt-names = "global";
@@ -375,7 +375,7 @@
 		timers15: timers@40014000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40014000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00010000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 16U)>;
 			resets = <&rctl STM32_RESET(APB2, 16U)>;
 			interrupts = <71 0>;
 			interrupt-names = "global";
@@ -396,7 +396,7 @@
 		timers16: timers@40014400 {
 			compatible = "st,stm32-timers";
 			reg = <0x40014400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00020000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 17U)>;
 			resets = <&rctl STM32_RESET(APB2, 17U)>;
 			interrupts = <72 0>;
 			interrupt-names = "global";
@@ -417,7 +417,7 @@
 		timers17: timers@40014800 {
 			compatible = "st,stm32-timers";
 			reg = <0x40014800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00040000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 18U)>;
 			resets = <&rctl STM32_RESET(APB2, 18U)>;
 			interrupts = <73 0>;
 			interrupt-names = "global";
@@ -438,7 +438,7 @@
 		aes: aes@420c0000 {
 			compatible = "st,stm32-aes";
 			reg = <0x420c0000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00010000>;
+			clocks = <&rcc STM32_CLOCK(AHB2, 16U)>;
 			resets = <&rctl STM32_RESET(AHB2, 16U)>;
 			interrupts = <116 0>;
 			status = "disabled";
@@ -451,7 +451,7 @@
 			interrupts = <109 0>, <110 0>;
 			interrupt-names = "int0", "int1";
 			/* common clock FDCAN 1 & 2 */
-			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000200>;
+			clocks = <&rcc STM32_CLOCK(APB1_2, 9U)>;
 			bosch,mram-cfg = <0x350 28 8 3 3 0 3 3>;
 			status = "disabled";
 		};
@@ -459,7 +459,7 @@
 		sdmmc1: sdmmc@46008000 {
 			compatible = "st,stm32-sdmmc";
 			reg = <0x46008000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000800>,
+			clocks = <&rcc STM32_CLOCK(AHB4, 11U)>,
 				 <&rcc STM32_SRC_PLL1_Q SDMMC1_SEL(0)>;
 			resets = <&rctl STM32_RESET(AHB4, 11U)>;
 			interrupts = <79 0>;
@@ -469,7 +469,7 @@
 		fmc: memory-controller@47000400 {
 			compatible = "st,stm32-fmc";
 			reg = <0x47000400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00010000>;
+			clocks = <&rcc STM32_CLOCK(AHB4, 16U)>;
 			status = "disabled";
 		};
 	};

dts/arm/st/h5/stm32h563.dtsi

@@ -13,7 +13,7 @@
 		sdmmc2: sdmmc@46008c00 {
 			compatible = "st,stm32-sdmmc";
 			reg = <0x46008c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00001000>,
+			clocks = <&rcc STM32_CLOCK(AHB4, 12U)>,
 				 <&rcc STM32_SRC_PLL1_Q SDMMC2_SEL(0)>;
 			resets = <&rctl STM32_RESET(AHB4, 12U)>;
 			interrupts = <102 0>;

dts/arm/st/h7/stm32h7.dtsi

@@ -144,7 +144,7 @@
 			compatible = "st,stm32-flash-controller", "st,stm32h7-flash-controller";
 			reg = <0x52002000 0x400>;
 			interrupts = <4 0>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00000100>;
+			clocks = <&rcc STM32_CLOCK(AHB3, 8U)>;
 
 			#address-cells = <1>;
 			#size-cells = <1>;
@@ -187,7 +187,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x58020000 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000001>;
+				clocks = <&rcc STM32_CLOCK(AHB4, 0U)>;
 			};
 
 			gpiob: gpio@58020400 {
@@ -195,7 +195,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x58020400 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000002>;
+				clocks = <&rcc STM32_CLOCK(AHB4, 1U)>;
 			};
 
 			gpioc: gpio@58020800 {
@@ -203,7 +203,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x58020800 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000004>;
+				clocks = <&rcc STM32_CLOCK(AHB4, 2U)>;
 			};
 
 			gpiod: gpio@58020C00 {
@@ -211,7 +211,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x58020C00 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000008>;
+				clocks = <&rcc STM32_CLOCK(AHB4, 3U)>;
 			};
 
 			gpioe: gpio@58021000 {
@@ -219,7 +219,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x58021000 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000010>;
+				clocks = <&rcc STM32_CLOCK(AHB4, 4U)>;
 			};
 
 			gpiof: gpio@58021400 {
@@ -227,7 +227,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x58021400 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000020>;
+				clocks = <&rcc STM32_CLOCK(AHB4, 5U)>;
 			};
 
 			gpiog: gpio@58021800 {
@@ -235,7 +235,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x58021800 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000040>;
+				clocks = <&rcc STM32_CLOCK(AHB4, 6U)>;
 			};
 
 			gpioh: gpio@58021C00 {
@@ -243,7 +243,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x58021C00 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000080>;
+				clocks = <&rcc STM32_CLOCK(AHB4, 7U)>;
 			};
 
 			gpioi: gpio@58022000 {
@@ -251,7 +251,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x58022000 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000100>;
+				clocks = <&rcc STM32_CLOCK(AHB4, 8U)>;
 			};
 
 			gpioj: gpio@58022400 {
@@ -259,7 +259,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x58022400 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000200>;
+				clocks = <&rcc STM32_CLOCK(AHB4, 9U)>;
 			};
 
 			gpiok: gpio@58022800 {
@@ -267,7 +267,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x58022800 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000400>;
+				clocks = <&rcc STM32_CLOCK(AHB4, 10U)>;
 			};
 		};
 
@@ -280,7 +280,7 @@
 		wwdg: wwdg1: watchdog@50003000 {
 			compatible = "st,stm32-window-watchdog";
 			reg = <0x50003000 0x1000>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000040>;
+			clocks = <&rcc STM32_CLOCK(APB3, 6U)>;
 			interrupts = <0 7>;
 			status = "disabled";
 		};
@@ -288,7 +288,7 @@
 		usart1: serial@40011000 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40011000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000010>;
+			clocks = <&rcc STM32_CLOCK(APB2, 4U)>;
 			resets = <&rctl STM32_RESET(APB2, 4U)>;
 			interrupts = <37 0>;
 			status = "disabled";
@@ -296,7 +296,7 @@
 		usart2: serial@40004400 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40004400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 17U)>;
 			resets = <&rctl STM32_RESET(APB1L, 17U)>;
 			interrupts = <38 0>;
 			status = "disabled";
@@ -304,7 +304,7 @@
 		usart3: serial@40004800 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40004800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
 			resets = <&rctl STM32_RESET(APB1L, 18U)>;
 			interrupts = <39 0>;
 			status = "disabled";
@@ -312,7 +312,7 @@
 		uart4: serial@40004c00 {
 			compatible ="st,stm32-uart";
 			reg = <0x40004c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
 			resets = <&rctl STM32_RESET(APB1L, 19U)>;
 			interrupts = <52 0>;
 			status = "disabled";
@@ -320,7 +320,7 @@
 		uart5: serial@40005000 {
 			compatible = "st,stm32-uart";
 			reg = <0x40005000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
 			resets = <&rctl STM32_RESET(APB1L, 20U)>;
 			interrupts = <53 0>;
 			status = "disabled";
@@ -328,7 +328,7 @@
 		usart6: serial@40011400 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40011400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
+			clocks = <&rcc STM32_CLOCK(APB2, 5U)>;
 			resets = <&rctl STM32_RESET(APB2, 5U)>;
 			interrupts = <71 0>;
 			status = "disabled";
@@ -336,7 +336,7 @@
 		uart7: serial@40007800 {
 			compatible = "st,stm32-uart";
 			reg = <0x40007800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x40000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 30U)>;
 			resets = <&rctl STM32_RESET(APB1L, 30U)>;
 			interrupts = <82 0>;
 			status = "disabled";
@@ -344,7 +344,7 @@
 		uart8: serial@40007c00 {
 			compatible = "st,stm32-uart";
 			reg = <0x40007c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 31U)>;
 			resets = <&rctl STM32_RESET(APB1L, 31U)>;
 			interrupts = <83 0>;
 			status = "disabled";
@@ -353,7 +353,7 @@
 		lpuart1: serial@58000c00 {
 			compatible = "st,stm32-lpuart", "st,stm32-uart";
 			reg = <0x58000c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB4 0x00000008>;
+			clocks = <&rcc STM32_CLOCK(APB4, 3U)>;
 			resets = <&rctl STM32_RESET(APB4, 3U)>;
 			interrupts = <142 0>;
 			status = "disabled";
@@ -363,7 +363,7 @@
 			compatible = "st,stm32-rtc";
 			reg = <0x58004000 0x400>;
 			interrupts = <41 0>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB4 0x00010000>;
+			clocks = <&rcc STM32_CLOCK(APB4, 16U)>;
 			prescaler = <32768>;
 			alarms-count = <2>;
 			alrm-exti-line = <17>;
@@ -376,7 +376,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40005400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 21U)>;
 			interrupts = <31 0>, <32 0>;
 			interrupt-names = "event", "error";
 			status = "disabled";
@@ -388,7 +388,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40005800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
 			interrupts = <33 0>, <34 0>;
 			interrupt-names = "event", "error";
 			status = "disabled";
@@ -400,7 +400,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40005c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 23U)>;
 			interrupts = <72 0>, <73 0>;
 			interrupt-names = "event", "error";
 			status = "disabled";
@@ -412,7 +412,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x58001c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB4 0x00000080>;
+			clocks = <&rcc STM32_CLOCK(APB4, 7U)>;
 			interrupts = <95 0>, <96 0>;
 			interrupt-names = "event", "error";
 			status = "disabled";
@@ -423,7 +423,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40013000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>,
+			clocks = <&rcc STM32_CLOCK(APB2, 12U)>,
 				<&rcc STM32_SRC_PLL1_Q SPI123_SEL(0)>;
 			interrupts = <35 0>;
 			status = "disabled";
@@ -434,7 +434,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40003800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>,
+			clocks = <&rcc STM32_CLOCK(APB1, 14U)>,
 				<&rcc STM32_SRC_PLL1_Q SPI123_SEL(0)>;
 			interrupts = <36 0>;
 			status = "disabled";
@@ -445,7 +445,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40003c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>,
+			clocks = <&rcc STM32_CLOCK(APB1, 15U)>,
 				<&rcc STM32_SRC_PLL1_Q SPI123_SEL(0)>;
 			interrupts = <51 0>;
 			status = "disabled";
@@ -456,7 +456,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40013400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 13U)>;
 			interrupts = <84 0>;
 			status = "disabled";
 		};
@@ -466,7 +466,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40015000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 20U)>;
 			interrupts = <85 0>;
 			status = "disabled";
 		};
@@ -476,7 +476,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x58001400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB4 0x00000020>;
+			clocks = <&rcc STM32_CLOCK(APB4, 5U)>;
 			interrupts = <86 0>;
 			status = "disabled";
 		};
@@ -486,7 +486,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40013000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>,
+			clocks = <&rcc STM32_CLOCK(APB2, 12U)>,
 				 <&rcc STM32_SRC_PLL1_Q SPI123_SEL(0)>;
 			dmas = <&dmamux1 0 38 (STM32_DMA_PERIPH_TX | STM32_DMA_PRIORITY_HIGH)
 				&dmamux1 1 37 (STM32_DMA_PERIPH_RX | STM32_DMA_PRIORITY_HIGH)>;
@@ -500,7 +500,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40003800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>,
+			clocks = <&rcc STM32_CLOCK(APB1, 14U)>,
 				 <&rcc STM32_SRC_PLL1_Q SPI123_SEL(0)>;
 			dmas = <&dmamux1 0 40 (STM32_DMA_PERIPH_TX | STM32_DMA_PRIORITY_HIGH)
 				&dmamux1 1 39 (STM32_DMA_PERIPH_RX | STM32_DMA_PRIORITY_HIGH)>;
@@ -514,7 +514,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40003c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>,
+			clocks = <&rcc STM32_CLOCK(APB1, 15U)>,
 				 <&rcc STM32_SRC_PLL1_Q SPI123_SEL(0)>;
 			dmas = <&dmamux1 0 62 (STM32_DMA_PERIPH_TX | STM32_DMA_PRIORITY_HIGH)
 				&dmamux1 1 61 (STM32_DMA_PERIPH_RX | STM32_DMA_PRIORITY_HIGH)>;
@@ -527,7 +527,7 @@
 			compatible = "st,stm32h7-fdcan";
 			reg = <0x4000a000 0x400>, <0x4000ac00 0x350>;
 			reg-names = "m_can", "message_ram";
-			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000100>;
+			clocks = <&rcc STM32_CLOCK(APB1_2, 8U)>;
 			interrupts = <19 0>, <21 0>, <63 0>;
 			interrupt-names = "int0", "int1", "calib";
 			bosch,mram-cfg = <0x0 28 8 3 3 0 3 3>;
@@ -538,7 +538,7 @@
 			compatible = "st,stm32h7-fdcan";
 			reg = <0x4000a400 0x400>, <0x4000ac00 0x6a0>;
 			reg-names = "m_can", "message_ram";
-			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000100>;
+			clocks = <&rcc STM32_CLOCK(APB1_2, 8U)>;
 			interrupts = <20 0>, <22 0>, <63 0>;
 			interrupt-names = "int0", "int1", "calib";
 			bosch,mram-cfg = <0x350 28 8 3 3 0 3 3>;
@@ -548,7 +548,7 @@
 		timers1: timers@40010000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40010000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000001>;
+			clocks = <&rcc STM32_CLOCK(APB2, 0U)>;
 			resets = <&rctl STM32_RESET(APB2, 0U)>;
 			interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
 			interrupt-names = "brk", "up", "trgcom", "cc";
@@ -565,7 +565,7 @@
 		timers2: timers@40000000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40000000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
+			clocks = <&rcc STM32_CLOCK(APB1, 0U)>;
 			resets = <&rctl STM32_RESET(APB1L, 0U)>;
 			interrupts = <28 0>;
 			interrupt-names = "global";
@@ -587,7 +587,7 @@
 		timers3: timers@40000400 {
 			compatible = "st,stm32-timers";
 			reg = <0x40000400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
+			clocks = <&rcc STM32_CLOCK(APB1, 1U)>;
 			resets = <&rctl STM32_RESET(APB1L, 1U)>;
 			interrupts = <29 0>;
 			interrupt-names = "global";
@@ -609,7 +609,7 @@
 		timers4: timers@40000800 {
 			compatible = "st,stm32-timers";
 			reg = <0x40000800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
+			clocks = <&rcc STM32_CLOCK(APB1, 2U)>;
 			resets = <&rctl STM32_RESET(APB1L, 2U)>;
 			interrupts = <30 0>;
 			interrupt-names = "global";
@@ -631,7 +631,7 @@
 		timers5: timers@40000c00 {
 			compatible = "st,stm32-timers";
 			reg = <0x40000c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
+			clocks = <&rcc STM32_CLOCK(APB1, 3U)>;
 			resets = <&rctl STM32_RESET(APB1L, 3U)>;
 			interrupts = <50 0>;
 			interrupt-names = "global";
@@ -653,7 +653,7 @@
 		timers6: timers@40001000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40001000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
+			clocks = <&rcc STM32_CLOCK(APB1, 4U)>;
 			resets = <&rctl STM32_RESET(APB1L, 4U)>;
 			interrupts = <54 0>;
 			interrupt-names = "global";
@@ -669,7 +669,7 @@
 		timers7: timers@40001400 {
 			compatible = "st,stm32-timers";
 			reg = <0x40001400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
+			clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
 			resets = <&rctl STM32_RESET(APB1L, 5U)>;
 			interrupts = <55 0>;
 			interrupt-names = "global";
@@ -685,7 +685,7 @@
 		timers8: timers@40010400 {
 			compatible = "st,stm32-timers";
 			reg = <0x40010400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000002>;
+			clocks = <&rcc STM32_CLOCK(APB2, 1U)>;
 			resets = <&rctl STM32_RESET(APB2, 1U)>;
 			interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
 			interrupt-names = "brk", "up", "trgcom", "cc";
@@ -702,7 +702,7 @@
 		timers12: timers@40001800 {
 			compatible = "st,stm32-timers";
 			reg = <0x40001800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000040>;
+			clocks = <&rcc STM32_CLOCK(APB1, 6U)>;
 			resets = <&rctl STM32_RESET(APB1L, 6U)>;
 			interrupts = <43 0>;
 			interrupt-names = "global";
@@ -724,7 +724,7 @@
 		timers13: timers@40001c00 {
 			compatible = "st,stm32-timers";
 			reg = <0x40001c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000080>;
+			clocks = <&rcc STM32_CLOCK(APB1, 7U)>;
 			resets = <&rctl STM32_RESET(APB1L, 7U)>;
 			interrupts = <44 0>;
 			interrupt-names = "global";
@@ -746,7 +746,7 @@
 		timers14: timers@40002000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40002000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000100>;
+			clocks = <&rcc STM32_CLOCK(APB1, 8U)>;
 			resets = <&rctl STM32_RESET(APB1L, 8U)>;
 			interrupts = <45 0>;
 			interrupt-names = "global";
@@ -768,7 +768,7 @@
 		timers15: timers@40014000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40014000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00010000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 16U)>;
 			resets = <&rctl STM32_RESET(APB2, 16U)>;
 			interrupts = <116 0>;
 			interrupt-names = "global";
@@ -790,7 +790,7 @@
 		timers16: timers@40014400 {
 			compatible = "st,stm32-timers";
 			reg = <0x40014400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00020000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 17U)>;
 			resets = <&rctl STM32_RESET(APB2, 17U)>;
 			interrupts = <117 0>;
 			interrupt-names = "global";
@@ -812,7 +812,7 @@
 		timers17: timers@40014800 {
 			compatible = "st,stm32-timers";
 			reg = <0x40014800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00040000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 18U)>;
 			resets = <&rctl STM32_RESET(APB2, 18U)>;
 			interrupts = <118 0>;
 			interrupt-names = "global";
@@ -833,7 +833,7 @@
 
 		lptim1: timers@40002400 {
 			compatible = "st,stm32-lptim";
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000200>;
+			clocks = <&rcc STM32_CLOCK(APB1, 9U)>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40002400 0x400>;
@@ -852,7 +852,7 @@
 		adc1: adc@40022000 {
 			compatible = "st,stm32-adc";
 			reg = <0x40022000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000020>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 5U)>;
 			interrupts = <18 0>;
 			status = "disabled";
 			#io-channel-cells = <1>;
@@ -868,7 +868,7 @@
 		adc2: adc@40022100 {
 			compatible = "st,stm32-adc";
 			reg = <0x40022100 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000020>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 5U)>;
 			interrupts = <18 0>;
 			status = "disabled";
 			#io-channel-cells = <1>;
@@ -885,7 +885,7 @@
 		adc1_2: adc@40022300 {
 			compatible = "st,stm32-adc";
 			reg = <0x40022300 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000020>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 5U)>;
 			interrupts = <18 0>;
 			status = "disabled";
 			#io-channel-cells = <1>;
@@ -901,7 +901,7 @@
 		adc3: adc@58026000 {
 			compatible = "st,stm32-adc";
 			reg = <0x58026000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x01000000>;
+			clocks = <&rcc STM32_CLOCK(AHB4, 24U)>;
 			interrupts = <127 0>;
 			status = "disabled";
 			#io-channel-cells = <1>;
@@ -917,7 +917,7 @@
 		dac1: dac@40007400 {
 			compatible = "st,stm32-dac";
 			reg = <0x40007400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 29U)>;
 			status = "disabled";
 			#io-channel-cells = <1>;
 		};
@@ -928,7 +928,7 @@
 			reg = <0x40020000 0x400>;
 			interrupts = <11 0>, <12 0>, <13 0>, <14 0>, <15 0>, <16 0>,
 						 <17 0>, <47 0>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000001>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 0U)>;
 			st,mem2mem;
 			dma-offset = <0>;
 			dma-requests = <8>;
@@ -941,7 +941,7 @@
 			reg = <0x40020400 0x400>;
 			interrupts = <56 0>, <57 0>, <58 0>, <59 0>, <60 0>, <68 0>,
 						<69 0>, <70 0>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000002>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 1U)>;
 			st,mem2mem;
 			dma-offset = <8>;
 			dma-requests = <8>;
@@ -954,7 +954,7 @@
 			reg = <0x58025400 0x400>;
 			interrupts = <129 0>, <130 0>, <131 0>, <132 0>, <133 0>, <134 0>,
 						 <135 0>, <136 0>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00200000>;
+			clocks = <&rcc STM32_CLOCK(AHB4, 21U)>;
 			st,mem2mem;
 			dma-offset = <0>;
 			dma-requests = <8>;
@@ -967,7 +967,7 @@
 			reg = <0x40020800 0x400>;
 			interrupts = <102 0>;
 			/* dmamux1 has no dedicated clock, so we enable dma1 clock */
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000001>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 0U)>;
 			dma-channels = <16>;
 			dma-generators = <8>;
 			status = "disabled";
@@ -983,7 +983,7 @@
 			reg = <0x58025800 0x400>;
 			interrupts = <128 0>;
 			/* dmamux2 has no dedicated clock, so we enable bdma clock */
-			clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00200000>;
+			clocks = <&rcc STM32_CLOCK(AHB4, 21U)>;
 			dma-channels = <8>;
 			dma-generators = <8>;
 			status = "disabled";
@@ -996,7 +996,7 @@
 		rng: rng@48021800 {
 			compatible = "st,stm32-rng";
 			reg = <0x48021800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000040>;
+			clocks = <&rcc STM32_CLOCK(AHB2, 6U)>;
 			interrupts = <80 0>;
 			status = "disabled";
 		};
@@ -1004,7 +1004,7 @@
 		sdmmc1: sdmmc@52007000 {
 			compatible = "st,stm32-sdmmc";
 			reg = <0x52007000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00010000>,
+			clocks = <&rcc STM32_CLOCK(AHB3, 16U)>,
 				 <&rcc STM32_SRC_PLL1_Q SDMMC_SEL(0)>;
 			resets = <&rctl STM32_RESET(AHB3, 16U)>;
 			interrupts = <49 0>;
@@ -1014,7 +1014,7 @@
 		sdmmc2: sdmmc@48022400 {
 			compatible = "st,stm32-sdmmc";
 			reg = <0x48022400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000200>,
+			clocks = <&rcc STM32_CLOCK(AHB2, 9U)>,
 				 <&rcc STM32_SRC_PLL1_Q SDMMC_SEL(0)>;
 			resets = <&rctl STM32_RESET(AHB2, 9U)>;
 			interrupts = <124 0>;
@@ -1026,9 +1026,9 @@
 			reg = <0x40028000 0x8000>;
 			interrupts = <61 0>;
 			clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00008000>,
-				 <&rcc STM32_CLOCK_BUS_AHB1 0x00010000>,
-				 <&rcc STM32_CLOCK_BUS_AHB1 0x00020000>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 15U)>,
+				 <&rcc STM32_CLOCK(AHB1, 16U)>,
+				 <&rcc STM32_CLOCK(AHB1, 17U)>;
 			status = "disabled";
 
 			mdio: mdio {
@@ -1042,7 +1042,7 @@
 		fmc: memory-controller@52004000 {
 			compatible = "st,stm32h7-fmc";
 			reg = <0x52004000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00001000>;
+			clocks = <&rcc STM32_CLOCK(AHB3, 12U)>;
 			status = "disabled";
 
 			sdram: sdram {
@@ -1056,7 +1056,7 @@
 		backup_sram: memory@38800000 {
 			compatible = "zephyr,memory-region", "st,stm32-backup-sram";
 			reg = <0x38800000 DT_SIZE_K(4)>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x10000000>;
+			clocks = <&rcc STM32_CLOCK(AHB4, 28U)>;
 			zephyr,memory-region = "BACKUP_SRAM";
 			status = "disabled";
 		};
@@ -1067,7 +1067,7 @@
 			#size-cells = <0x0>;
 			reg = <0x52005000 0x34>;
 			interrupts = <92 0>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00004000>;
+			clocks = <&rcc STM32_CLOCK(AHB3, 14U)>;
 			status = "disabled";
 		};
 
@@ -1076,7 +1076,7 @@
 			reg = <0x48020000 0x400>;
 			interrupts = <78 0>;
 			interrupt-names = "dcmi";
-			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000001>;
+			clocks = <&rcc STM32_CLOCK(AHB2, 0U)>;
 			status = "disabled";
 		};
 	};

dts/arm/st/h7/stm32h723.dtsi

@@ -27,7 +27,7 @@
 		uart9: serial@40011800 {
 			compatible = "st,stm32-uart";
 			reg = <0x40011800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000040>;
+			clocks = <&rcc STM32_CLOCK(APB2, 6U)>;
 			resets = <&rctl STM32_RESET(APB2, 6U)>;
 			interrupts = <155 0>;
 			status = "disabled";
@@ -36,7 +36,7 @@
 		usart10: serial@40011c00 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40011c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000080>;
+			clocks = <&rcc STM32_CLOCK(APB2, 7U)>;
 			resets = <&rctl STM32_RESET(APB2, 7U)>;
 			interrupts = <156 0>;
 			status = "disabled";
@@ -76,7 +76,7 @@
 			num-bidir-endpoints = <9>;
 			ram-size = <DT_SIZE_K(4)>;
 			maximum-speed = "full-speed";
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x02000000>,
+			clocks = <&rcc STM32_CLOCK(AHB1, 25U)>,
 				 <&rcc STM32_SRC_HSI48 USB_SEL(3)>;
 			phys = <&otghs_fs_phy>;
 			status = "disabled";
@@ -87,7 +87,7 @@
 			reg = <0x50001000 0x200>;
 			interrupts = <88 0>, <89 0>;
 			interrupt-names = "ltdc", "ltdc_er";
-			clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000008>;
+			clocks = <&rcc STM32_CLOCK(APB3, 3U)>;
 			resets = <&rctl STM32_RESET(APB3, 4U)>;
 			status = "disabled";
 		};
@@ -97,7 +97,7 @@
 			reg = <0x52005000 0x1000>;
 			interrupts = <92 0>;
 			clock-names = "ospix", "ospi-ker";
-			clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00004000>,
+			clocks = <&rcc STM32_CLOCK(AHB3, 14U)>,
 				<&rcc STM32_SRC_PLL1_Q OSPI_SEL(1)>;
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -109,7 +109,7 @@
 			reg = <0x5200a000 0x1000>;
 			interrupts = <150 0>;
 			clock-names = "ospix", "ospi-ker";
-			clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x000080000>,
+			clocks = <&rcc STM32_CLOCK(AHB3, 19U)>,
 				<&rcc STM32_SRC_PLL1_Q OSPI_SEL(1)>;
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -120,7 +120,7 @@
 			compatible = "st,stm32h7-fdcan";
 			reg = <0x4000d400 0x400>, <0x4000ac00 0x9f0>;
 			reg-names = "m_can", "message_ram";
-			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000100>;
+			clocks = <&rcc STM32_CLOCK(APB1_2, 8U)>;
 			interrupts = <159 0>, <160 0>, <63 0>;
 			interrupt-names = "int0", "int1", "calib";
 			bosch,mram-cfg = <0x6a0 28 8 3 3 0 3 3>;
@@ -138,7 +138,7 @@
 		timers23: timers@4000e000 {
 			compatible = "st,stm32-timers";
 			reg = <0x4000e000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x01000000>;
+			clocks = <&rcc STM32_CLOCK(APB1_2, 24U)>;
 			resets = <&rctl STM32_RESET(APB1H, 24U)>;
 			interrupts = <161 0>;
 			interrupt-names = "global";
@@ -160,7 +160,7 @@
 		timers24: timers@4000e400 {
 			compatible = "st,stm32-timers";
 			reg = <0x4000e400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x02000000>;
+			clocks = <&rcc STM32_CLOCK(APB1_2, 25U)>;
 			resets = <&rctl STM32_RESET(APB1H, 25U)>;
 			interrupts = <162 0>;
 			interrupt-names = "global";
@@ -184,7 +184,7 @@
 			reg = <0x58006800 0x400>;
 			interrupts = <147 0>;
 			interrupt-names = "digi_temp";
-			clocks = <&rcc STM32_CLOCK_BUS_APB4 0x04000000>;
+			clocks = <&rcc STM32_CLOCK(APB4, 26U)>;
 			status = "disabled";
 		};
 	};

dts/arm/st/h7/stm32h730.dtsi

@@ -13,7 +13,7 @@
 		cryp: cryp@48021000 {
 			compatible = "st,stm32-cryp";
 			reg = <0x48021000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
+			clocks = <&rcc STM32_CLOCK(AHB2, 4U)>;
 			resets = <&rctl STM32_RESET(AHB2, 4U)>;
 			interrupts = <79 0>;
 			status = "disabled";

dts/arm/st/h7/stm32h743.dtsi

@@ -37,7 +37,7 @@
 			num-bidir-endpoints = <9>;
 			ram-size = <4096>;
 			maximum-speed = "full-speed";
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x08000000>,
+			clocks = <&rcc STM32_CLOCK(AHB1, 27U)>,
 				 <&rcc STM32_SRC_HSI48 USB_SEL(3)>;
 			phys = <&otghs_fs_phy>;
 			status = "disabled";
@@ -48,7 +48,7 @@
 			reg = <0x50001000 0x200>;
 			interrupts = <88 0>, <89 0>;
 			interrupt-names = "ltdc", "ltdc_er";
-			clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000008>;
+			clocks = <&rcc STM32_CLOCK(APB3, 3U)>;
 			resets = <&rctl STM32_RESET(APB3, 4U)>;
 			status = "disabled";
 		};

dts/arm/st/h7/stm32h745.dtsi

@@ -41,7 +41,7 @@
 			reg = <0x50001000 0x200>;
 			interrupts = <88 0>, <89 0>;
 			interrupt-names = "ltdc", "ltdc_er";
-			clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000008>;
+			clocks = <&rcc STM32_CLOCK(APB3, 3U)>;
 			resets = <&rctl STM32_RESET(APB3, 4U)>;
 			status = "disabled";
 		};
@@ -54,7 +54,7 @@
 			num-bidir-endpoints = <9>;
 			ram-size = <4096>;
 			maximum-speed = "full-speed";
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x02000000>,
+			clocks = <&rcc STM32_CLOCK(AHB1, 25U)>,
 				 <&rcc STM32_SRC_HSI48 USB_SEL(3)>;
 			phys = <&otghs_fs_phy>;
 			status = "disabled";
@@ -68,7 +68,7 @@
 			num-bidir-endpoints = <9>;
 			ram-size = <4096>;
 			maximum-speed = "full-speed";
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x08000000>,
+			clocks = <&rcc STM32_CLOCK(AHB1, 27U)>,
 				 <&rcc STM32_SRC_HSI48 USB_SEL(3)>;
 			phys = <&otghs_fs_phy>;
 			status = "disabled";

dts/arm/st/h7/stm32h747.dtsi

@@ -17,7 +17,7 @@
 			#size-cells = <0>;
 			reg = <0x50000000 0x1000>;
 			clock-names = "dsiclk", "refclk", "pixelclk";
-			clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000010>,
+			clocks = <&rcc STM32_CLOCK(APB3, 4U)>,
 				 <&rcc STM32_SRC_HSE NO_SEL>,
 				 <&rcc STM32_SRC_PLL3_R NO_SEL>;
 			resets = <&rctl STM32_RESET(APB3, 4U)>;

dts/arm/st/h7/stm32h755.dtsi

@@ -14,7 +14,7 @@
 		cryp: cryp@48021000 {
 			compatible = "st,stm32-cryp";
 			reg = <0x48021000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
+			clocks = <&rcc STM32_CLOCK(AHB2, 4U)>;
 			interrupts = <79 0>;
 			status = "disabled";
 		};
@@ -22,7 +22,7 @@
 		hash: cryp@48021400 {
 			compatible = "st,stm32-cryp";
 			reg = <0x48021400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000020>;
+			clocks = <&rcc STM32_CLOCK(AHB2, 5U)>;
 			interrupts = <80 0>;
 			status = "disabled";
 		};

dts/arm/st/h7/stm32h7_dualcore.dtsi

@@ -19,7 +19,7 @@
 		mailbox: mailbox@58026400 {
 			compatible = "st,stm32-hsem-mailbox", "st,mbox-stm32-hsem";
 			reg = <0x58026400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x02000000>;
+			clocks = <&rcc STM32_CLOCK(AHB4, 25U)>;
 			#mbox-cells = <1>;
 			status = "disabled";
 		};

dts/arm/st/h7/stm32h7a3.dtsi

@@ -40,7 +40,7 @@
 			num-bidir-endpoints = <9>;
 			ram-size = <4096>;
 			maximum-speed = "full-speed";
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x02000000>,
+			clocks = <&rcc STM32_CLOCK(AHB1, 25U)>,
 				 <&rcc STM32_SRC_HSI48 USB_SEL(3)>;
 			phys = <&otghs_fs_phy>;
 			status = "disabled";
@@ -51,7 +51,7 @@
 			reg = <0x50001000 0x200>;
 			interrupts = <88 0>, <89 0>;
 			interrupt-names = "ltdc", "ltdc_er";
-			clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000008>;
+			clocks = <&rcc STM32_CLOCK(APB3, 3U)>;
 			resets = <&rctl STM32_RESET(APB3, 4U)>;
 			status = "disabled";
 		};
@@ -61,7 +61,7 @@
 			reg = <0x52005000 0x1000>;
 			interrupts = <92 0>;
 			clock-names = "ospix", "ospi-ker";
-			clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00004000>,
+			clocks = <&rcc STM32_CLOCK(AHB3, 14U)>,
 				<&rcc STM32_SRC_PLL1_Q OSPI_SEL(1)>;
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -73,7 +73,7 @@
 			reg = <0x5200a000 0x1000>;
 			interrupts = <150 0>;
 			clock-names = "ospix", "ospi-ker";
-			clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x000080000>,
+			clocks = <&rcc STM32_CLOCK(AHB3, 19U)>,
 				<&rcc STM32_SRC_PLL1_Q OSPI_SEL(1)>;
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -85,7 +85,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x58001400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB4 0x00000020>,
+			clocks = <&rcc STM32_CLOCK(APB4, 5U)>,
 				 <&rcc STM32_SRC_PLL1_Q SPI6_SEL(0)>;
 			dmas = <&dmamux2 0 12 0x20440 &dmamux2 1 11 0x20480>;
 			dma-names = "tx", "rx";
@@ -104,7 +104,7 @@
 			reg = <0x58006800 0x400>;
 			interrupts = <147 0>;
 			interrupt-names = "digi_temp";
-			clocks = <&rcc STM32_CLOCK_BUS_APB4 0x04000000>;
+			clocks = <&rcc STM32_CLOCK(APB4, 26U)>;
 			status = "disabled";
 		};
 	};

dts/arm/st/h7/stm32h7b0.dtsi

@@ -18,7 +18,7 @@
 		cryp: cryp@48021000 {
 			compatible = "st,stm32-cryp";
 			reg = <0x48021000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
+			clocks = <&rcc STM32_CLOCK(AHB2, 4U)>;
 			resets = <&rctl STM32_RESET(AHB2, 4U)>;
 			interrupts = <79 0>;
 			interrupt-names = "cryp";

dts/arm/st/h7rs/stm32h7rs.dtsi

@@ -175,7 +175,7 @@
 			compatible = "st,stm32-flash-controller", "st,stm32h7-flash-controller";
 			reg = <0x52002000 0x400>;
 			interrupts = <8 0>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00000100>;
+			clocks = <&rcc STM32_CLOCK(AHB3, 8U)>;
 
 			#address-cells = <1>;
 			#size-cells = <1>;
@@ -233,7 +233,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x58020000 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000001>;
+				clocks = <&rcc STM32_CLOCK(AHB4, 0U)>;
 			};
 
 			gpiob: gpio@58020400 {
@@ -241,7 +241,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x58020400 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000002>;
+				clocks = <&rcc STM32_CLOCK(AHB4, 1U)>;
 			};
 
 			gpioc: gpio@58020800 {
@@ -249,7 +249,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x58020800 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000004>;
+				clocks = <&rcc STM32_CLOCK(AHB4, 2U)>;
 			};
 
 			gpiod: gpio@58020C00 {
@@ -257,7 +257,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x58020C00 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000008>;
+				clocks = <&rcc STM32_CLOCK(AHB4, 3U)>;
 			};
 
 			gpioe: gpio@58021000 {
@@ -265,7 +265,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x58021000 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000010>;
+				clocks = <&rcc STM32_CLOCK(AHB4, 4U)>;
 			};
 
 			gpiof: gpio@58021400 {
@@ -273,7 +273,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x58021400 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000020>;
+				clocks = <&rcc STM32_CLOCK(AHB4, 5U)>;
 			};
 
 			gpiog: gpio@58021800 {
@@ -281,7 +281,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x58021800 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000040>;
+				clocks = <&rcc STM32_CLOCK(AHB4, 6U)>;
 			};
 
 			gpioh: gpio@58021c00 {
@@ -289,7 +289,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x58021c00 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000080>;
+				clocks = <&rcc STM32_CLOCK(AHB4, 7U)>;
 			};
 
 			gpiom: gpio@58023000 {
@@ -297,7 +297,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x58023000 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00001000>;
+				clocks = <&rcc STM32_CLOCK(AHB4, 12U)>;
 			};
 
 			gpion: gpio@58023400 {
@@ -305,7 +305,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x58023400 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00002000>;
+				clocks = <&rcc STM32_CLOCK(AHB4, 13U)>;
 			};
 
 			gpioo: gpio@58023800 {
@@ -313,7 +313,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x58023800 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00004000>;
+				clocks = <&rcc STM32_CLOCK(AHB4, 14U)>;
 			};
 
 			gpiop: gpio@58023c00 {
@@ -321,14 +321,14 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x58023c00 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00008000>;
+				clocks = <&rcc STM32_CLOCK(AHB4, 15U)>;
 			};
 		};
 
 		usart1: serial@42001000 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x42001000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000010>;
+			clocks = <&rcc STM32_CLOCK(APB2, 4U)>;
 			resets = <&rctl STM32_RESET(APB2, 4U)>;
 			interrupts = <82 0>;
 			status = "disabled";
@@ -336,7 +336,7 @@
 		usart2: serial@40004400 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40004400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 17U)>;
 			resets = <&rctl STM32_RESET(APB1L, 17U)>;
 			interrupts = <83 0>;
 			status = "disabled";
@@ -344,7 +344,7 @@
 		usart3: serial@40004800 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40004800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
 			resets = <&rctl STM32_RESET(APB1L, 18U)>;
 			interrupts = <84 0>;
 			status = "disabled";
@@ -352,7 +352,7 @@
 		uart4: serial@40004c00 {
 			compatible ="st,stm32-uart";
 			reg = <0x40004c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
 			resets = <&rctl STM32_RESET(APB1L, 19U)>;
 			interrupts = <85 0>;
 			status = "disabled";
@@ -360,7 +360,7 @@
 		uart5: serial@40005000 {
 			compatible = "st,stm32-uart";
 			reg = <0x40005000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
 			resets = <&rctl STM32_RESET(APB1L, 20U)>;
 			interrupts = <86 0>;
 			status = "disabled";
@@ -368,7 +368,7 @@
 		uart7: serial@40007800 {
 			compatible = "st,stm32-uart";
 			reg = <0x40007800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x40000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 30U)>;
 			resets = <&rctl STM32_RESET(APB1L, 30U)>;
 			interrupts = <87 0>;
 			status = "disabled";
@@ -376,7 +376,7 @@
 		uart8: serial@40007c00 {
 			compatible = "st,stm32-uart";
 			reg = <0x40007c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 31U)>;
 			resets = <&rctl STM32_RESET(APB1L, 31U)>;
 			interrupts = <88 0>;
 			status = "disabled";
@@ -385,7 +385,7 @@
 		lpuart1: serial@58000c00 {
 			compatible = "st,stm32-lpuart", "st,stm32-uart";
 			reg = <0x58000c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB4 0x00000008>;
+			clocks = <&rcc STM32_CLOCK(APB4, 3U)>;
 			resets = <&rctl STM32_RESET(APB4, 3U)>;
 			interrupts = <131 0>;
 			status = "disabled";
@@ -397,7 +397,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40005400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 21U)>;
 			interrupts = <76 0>, <77 0>;
 			interrupt-names = "event", "error";
 			status = "disabled";
@@ -409,7 +409,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40005800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
 			interrupts = <78 0>, <79 0>;
 			interrupt-names = "event", "error";
 			status = "disabled";
@@ -421,7 +421,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40005c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 23U)>;
 			interrupts = <80 0>, <81 0>;
 			interrupt-names = "event", "error";
 			status = "disabled";
@@ -432,7 +432,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x42003000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>,
+			clocks = <&rcc STM32_CLOCK(APB2, 12U)>,
 				<&rcc STM32_SRC_PLL1_Q SPI1_SEL(0)>;
 			interrupts = <58 0>;
 			status = "disabled";
@@ -443,7 +443,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40003800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>,
+			clocks = <&rcc STM32_CLOCK(APB1, 14U)>,
 				<&rcc STM32_SRC_PLL1_Q SPI23_SEL(0)>;
 			interrupts = <59 0>;
 			status = "disabled";
@@ -454,7 +454,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40003c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>,
+			clocks = <&rcc STM32_CLOCK(APB1, 15U)>,
 				<&rcc STM32_SRC_PLL1_Q SPI23_SEL(0)>;
 			interrupts = <60 0>;
 			status = "disabled";
@@ -465,7 +465,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x42003400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 13U)>;
 			interrupts = <61 0>;
 			status = "disabled";
 		};
@@ -475,7 +475,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x42005000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 20U)>;
 			interrupts = <62 0>;
 			status = "disabled";
 		};
@@ -485,7 +485,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40013000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>,
+			clocks = <&rcc STM32_CLOCK(APB2, 12U)>,
 				 <&rcc STM32_SRC_PLL1_Q SPI1_SEL(0)>;
 			interrupts = <35 3>;
 			status = "disabled";
@@ -501,7 +501,7 @@
 		wwdg: wwdg1: watchdog@40002c00 {
 			compatible = "st,stm32-window-watchdog";
 			reg = <0x40002c00 0x1000>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
+			clocks = <&rcc STM32_CLOCK(APB1, 11U)>;
 			interrupts = <4 7>;
 			status = "disabled";
 		};
@@ -509,7 +509,7 @@
 		timers1: timers@42000000 {
 			compatible = "st,stm32-timers";
 			reg = <0x42000000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000001>;
+			clocks = <&rcc STM32_CLOCK(APB2, 0U)>;
 			resets = <&rctl STM32_RESET(APB2, 0U)>;
 			interrupts = <47 0>, <48 0>, <49 0>, <50 0>;
 			interrupt-names = "brk", "up", "trgcom", "cc";
@@ -526,7 +526,7 @@
 		timers2: timers@40000000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40000000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
+			clocks = <&rcc STM32_CLOCK(APB1, 0U)>;
 			resets = <&rctl STM32_RESET(APB1L, 0U)>;
 			interrupts = <51 0>;
 			interrupt-names = "global";
@@ -548,7 +548,7 @@
 		timers3: timers@40000400 {
 			compatible = "st,stm32-timers";
 			reg = <0x40000400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
+			clocks = <&rcc STM32_CLOCK(APB1, 1U)>;
 			resets = <&rctl STM32_RESET(APB1L, 1U)>;
 			interrupts = <52 0>;
 			interrupt-names = "global";
@@ -570,7 +570,7 @@
 		timers4: timers@40000800 {
 			compatible = "st,stm32-timers";
 			reg = <0x40000800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
+			clocks = <&rcc STM32_CLOCK(APB1, 2U)>;
 			resets = <&rctl STM32_RESET(APB1L, 2U)>;
 			interrupts = <53 0>;
 			interrupt-names = "global";
@@ -592,7 +592,7 @@
 		timers5: timers@40000c00 {
 			compatible = "st,stm32-timers";
 			reg = <0x40000c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
+			clocks = <&rcc STM32_CLOCK(APB1, 3U)>;
 			resets = <&rctl STM32_RESET(APB1L, 3U)>;
 			interrupts = <54 0>;
 			interrupt-names = "global";
@@ -614,7 +614,7 @@
 		timers6: timers@40001000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40001000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
+			clocks = <&rcc STM32_CLOCK(APB1, 4U)>;
 			resets = <&rctl STM32_RESET(APB1L, 4U)>;
 			interrupts = <55 0>;
 			interrupt-names = "global";
@@ -630,7 +630,7 @@
 		timers7: timers@40001400 {
 			compatible = "st,stm32-timers";
 			reg = <0x40001400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
+			clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
 			resets = <&rctl STM32_RESET(APB1L, 5U)>;
 			interrupts = <56 0>;
 			interrupt-names = "global";
@@ -646,7 +646,7 @@
 		timers9: timers@42004c00 {
 			compatible = "st,stm32-timers";
 			reg = <0x42004c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00080000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 19U)>;
 			resets = <&rctl STM32_RESET(APB2, 19U)>;
 			interrupts = <57 0>;
 			interrupt-names = "global";
@@ -662,7 +662,7 @@
 		timers15: timers@42004000 {
 			compatible = "st,stm32-timers";
 			reg = <0x42004000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00010000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 16U)>;
 			resets = <&rctl STM32_RESET(APB2, 16U)>;
 			interrupts = <116 0>;
 			interrupt-names = "global";
@@ -684,7 +684,7 @@
 		timers16: timers@42004400 {
 			compatible = "st,stm32-timers";
 			reg = <0x42004400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 17U)>;
 			resets = <&rctl STM32_RESET(APB2, 17U)>;
 			interrupts = <117 0>;
 			interrupt-names = "global";
@@ -706,7 +706,7 @@
 		timers17: timers@42004800 {
 			compatible = "st,stm32-timers";
 			reg = <0x42004800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
 			resets = <&rctl STM32_RESET(APB2, 18U)>;
 			interrupts = <118 0>;
 			interrupt-names = "global";
@@ -727,7 +727,7 @@
 
 		lptim1: timers@40002400 {
 			compatible = "st,stm32-lptim";
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000200>;
+			clocks = <&rcc STM32_CLOCK(APB1, 9U)>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40002400 0x400>;
@@ -739,7 +739,7 @@
 		adc1: adc@40022000 {
 			compatible = "st,stm32-adc";
 			reg = <0x40022000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000020>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 5U)>;
 			interrupts = <38 0>;
 			status = "disabled";
 			#io-channel-cells = <1>;
@@ -754,7 +754,7 @@
 		adc2: adc@40022100 {
 			compatible = "st,stm32-adc";
 			reg = <0x40022100 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000020>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 5U)>;
 			interrupts = <38 0>;
 			status = "disabled";
 			#io-channel-cells = <1>;
@@ -769,7 +769,7 @@
 		rng: rng@48020000 {
 			compatible = "st,stm32-rng";
 			reg = <0x48020000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00000001>;
+			clocks = <&rcc STM32_CLOCK(AHB3, 0U)>;
 			interrupts = <37 0>;
 			status = "disabled";
 		};

dts/arm/st/l0/stm32l0.dtsi

@@ -95,7 +95,7 @@
 			compatible = "st,stm32-rtc";
 			reg = <0x40002800 0x400>;
 			interrupts = <2 0>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 28U)>;
 			prescaler = <32768>;
 			alarms-count = <2>;
 			alrm-exti-line = <17>;
@@ -160,7 +160,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x50000000 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000001>;
+				clocks = <&rcc STM32_CLOCK(IOP, 0U)>;
 			};
 
 			gpiob: gpio@50000400 {
@@ -168,7 +168,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x50000400 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000002>;
+				clocks = <&rcc STM32_CLOCK(IOP, 1U)>;
 			};
 
 			gpioc: gpio@50000800 {
@@ -176,7 +176,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x50000800 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000004>;
+				clocks = <&rcc STM32_CLOCK(IOP, 2U)>;
 			};
 
 			gpiod: gpio@50000c00 {
@@ -184,7 +184,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x50000c00 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000008>;
+				clocks = <&rcc STM32_CLOCK(IOP, 3U)>;
 			};
 
 			gpioh: gpio@50001c00 {
@@ -192,7 +192,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x50001c00 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000080>;
+				clocks = <&rcc STM32_CLOCK(IOP, 7U)>;
 			};
 		};
 
@@ -205,7 +205,7 @@
 		wwdg: watchdog@40002c00 {
 			compatible = "st,stm32-window-watchdog";
 			reg = <0x40002C00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
+			clocks = <&rcc STM32_CLOCK(APB1, 11U)>;
 			interrupts = <0 2>;
 			status = "disabled";
 		};
@@ -213,7 +213,7 @@
 		usart2: serial@40004400 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40004400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 17U)>;
 			resets = <&rctl STM32_RESET(APB1, 17U)>;
 			interrupts = <28 0>;
 			status = "disabled";
@@ -222,7 +222,7 @@
 		lpuart1: serial@40004800 {
 			compatible = "st,stm32-lpuart", "st,stm32-uart";
 			reg = <0x40004800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
 			resets = <&rctl STM32_RESET(APB1, 18U)>;
 			interrupts = <29 0>;
 			status = "disabled";
@@ -234,7 +234,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40005400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 21U)>;
 			interrupts = <23 0>;
 			interrupt-names = "combined";
 			status = "disabled";
@@ -245,7 +245,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40013000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 12U)>;
 			interrupts = <25 3>;
 			status = "disabled";
 		};
@@ -253,7 +253,7 @@
 		timers2: timers@40000000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40000000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
+			clocks = <&rcc STM32_CLOCK(APB1, 0U)>;
 			resets = <&rctl STM32_RESET(APB1, 0U)>;
 			interrupts = <15 0>;
 			interrupt-names = "global";
@@ -275,7 +275,7 @@
 		timers21: timers@40010800 {
 			compatible = "st,stm32-timers";
 			reg = <0x40010800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000004>;
+			clocks = <&rcc STM32_CLOCK(APB2, 2U)>;
 			resets = <&rctl STM32_RESET(APB2, 2U)>;
 			interrupts = <20 0>;
 			interrupt-names = "global";
@@ -296,7 +296,7 @@
 
 		lptim1: timers@40007c00 {
 			compatible = "st,stm32-lptim";
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 31U)>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40007c00 0x400>;
@@ -308,7 +308,7 @@
 		adc1: adc@40012400 {
 			compatible = "st,stm32-adc";
 			reg = <0x40012400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000200>;
+			clocks = <&rcc STM32_CLOCK(APB2, 9U)>;
 			interrupts = <12 0>;
 			status = "disabled";
 			#io-channel-cells = <1>;
@@ -326,7 +326,7 @@
 			#dma-cells = <3>;
 			reg = <0x40020000 0x400>;
 			interrupts = <9 0 10 0 10 0 11 0 11 0 11 0 11 0>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 0U)>;
 			status = "disabled";
 		};
 

dts/arm/st/l0/stm32l010Xb.dtsi

@@ -26,7 +26,7 @@
 		timers22: timers@40011400 {
 			compatible = "st,stm32-timers";
 			reg = <0x40011400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
+			clocks = <&rcc STM32_CLOCK(APB2, 5U)>;
 			resets = <&rctl STM32_RESET(APB2, 5U)>;
 			interrupts = <22 0>;
 			interrupt-names = "global";

dts/arm/st/l0/stm32l031.dtsi

@@ -13,7 +13,7 @@
 		timers22: timers@40011400 {
 			compatible = "st,stm32-timers";
 			reg = <0x40011400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
+			clocks = <&rcc STM32_CLOCK(APB2, 5U)>;
 			resets = <&rctl STM32_RESET(APB2, 5U)>;
 			interrupts = <22 0>;
 			interrupt-names = "global";

dts/arm/st/l0/stm32l051.dtsi

@@ -16,7 +16,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40005800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
 			interrupts = <24 0>;
 			interrupt-names = "combined";
 			status = "disabled";
@@ -27,7 +27,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40003800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
 			interrupts = <26 3>;
 			status = "disabled";
 		};
@@ -35,7 +35,7 @@
 		usart1: serial@40013800 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40013800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 14U)>;
 			resets = <&rctl STM32_RESET(APB2, 14U)>;
 			interrupts = <27 0>;
 			status = "disabled";
@@ -44,7 +44,7 @@
 		timers22: timers@40011400 {
 			compatible = "st,stm32-timers";
 			reg = <0x40011400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
+			clocks = <&rcc STM32_CLOCK(APB2, 5U)>;
 			resets = <&rctl STM32_RESET(APB2, 5U)>;
 			interrupts = <22 0>;
 			interrupt-names = "global";
@@ -61,7 +61,7 @@
 		timers6: timers@40001000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40001000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
+			clocks = <&rcc STM32_CLOCK(APB1, 4U)>;
 			resets = <&rctl STM32_RESET(APB1, 4U)>;
 			interrupts = <17 0>;
 			interrupt-names = "global";

dts/arm/st/l0/stm32l053.dtsi

@@ -29,7 +29,7 @@
 			ram-size = <1024>;
 			maximum-speed = "full-speed";
 			phys = <&otgfs_phy>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>,
+			clocks = <&rcc STM32_CLOCK(APB1, 23U)>,
 				 <&rcc STM32_SRC_HSI48 HSI48_SEL(1)>;
 			status = "disabled";
 		};
@@ -37,7 +37,7 @@
 		dac1: dac@40007400 {
 			compatible = "st,stm32-dac";
 			reg = <0x40007400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 29U)>;
 			status = "disabled";
 			#io-channel-cells = <1>;
 		};

dts/arm/st/l0/stm32l071.dtsi

@@ -16,7 +16,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x50001000 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000010>;
+				clocks = <&rcc STM32_CLOCK(IOP, 4U)>;
 			};
 		};
 
@@ -26,7 +26,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40005800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
 			interrupts = <24 0>;
 			interrupt-names = "combined";
 			status = "disabled";
@@ -38,7 +38,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40007800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x40000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 30U)>;
 			interrupts = <21 0>;
 			interrupt-names = "combined";
 			status = "disabled";
@@ -49,7 +49,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40003800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
 			interrupts = <26 3>;
 			status = "disabled";
 		};
@@ -57,7 +57,7 @@
 		timers3: timers@40000400 {
 			compatible = "st,stm32-timers";
 			reg = <0x40000400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
+			clocks = <&rcc STM32_CLOCK(APB1, 1U)>;
 			resets = <&rctl STM32_RESET(APB1, 1U)>;
 			interrupts = <16 0>;
 			interrupt-names = "global";
@@ -79,7 +79,7 @@
 		timers6: timers@40001000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40001000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
+			clocks = <&rcc STM32_CLOCK(APB1, 4U)>;
 			resets = <&rctl STM32_RESET(APB1, 4U)>;
 			interrupts = <17 0>;
 			interrupt-names = "global";
@@ -95,7 +95,7 @@
 		timers7: timers@40001400 {
 			compatible = "st,stm32-timers";
 			reg = <0x40001400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
+			clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
 			resets = <&rctl STM32_RESET(APB1, 5U)>;
 			interrupts = <18 0>;
 			interrupt-names = "global";
@@ -111,7 +111,7 @@
 		timers22: timers@40011400 {
 			compatible = "st,stm32-timers";
 			reg = <0x40011400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
+			clocks = <&rcc STM32_CLOCK(APB2, 5U)>;
 			resets = <&rctl STM32_RESET(APB2, 5U)>;
 			interrupts = <22 0>;
 			interrupt-names = "global";
@@ -133,7 +133,7 @@
 		usart1: serial@40013800 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40013800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 14U)>;
 			resets = <&rctl STM32_RESET(APB2, 14U)>;
 			interrupts = <27 0>;
 			status = "disabled";
@@ -142,7 +142,7 @@
 		usart4: serial@40004c00 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40004c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
 			resets = <&rctl STM32_RESET(APB1, 19U)>;
 			interrupts = <14 0>;
 			status = "disabled";
@@ -151,7 +151,7 @@
 		usart5: serial@40005000 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40005000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
 			resets = <&rctl STM32_RESET(APB1, 20U)>;
 			interrupts = <14 0>;
 			status = "disabled";

dts/arm/st/l0/stm32l072.dtsi

@@ -32,7 +32,7 @@
 			ram-size = <1024>;
 			maximum-speed = "full-speed";
 			phys = <&otgfs_phy>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>,
+			clocks = <&rcc STM32_CLOCK(APB1, 23U)>,
 				 <&rcc STM32_SRC_HSI48 HSI48_SEL(1)>;
 			status = "disabled";
 		};
@@ -41,7 +41,7 @@
 			compatible = "st,stm32-rng";
 			reg = <0x40025000 0x400>;
 			interrupts = <29 0>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00100000>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 20U)>;
 			status = "disabled";
 		};
 	};
@@ -54,7 +54,7 @@
 	dac1: dac@40007400 {
 		compatible = "st,stm32-dac";
 		reg = <0x40007400 0x400>;
-		clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
+		clocks = <&rcc STM32_CLOCK(APB1, 29U)>;
 		status = "disabled";
 		#io-channel-cells = <1>;
 	};

dts/arm/st/l1/stm32l1.dtsi

@@ -86,7 +86,7 @@
 			compatible = "st,stm32-flash-controller", "st,stm32f1-flash-controller";
 			reg = <0x40023c00 0x400>;
 			interrupts = <4 0>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00008000>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 15U)>;
 
 			#address-cells = <1>;
 			#size-cells = <1>;
@@ -117,7 +117,7 @@
 			compatible = "st,stm32-rtc";
 			reg = <0x40002800 0x400>;
 			interrupts = <41 0>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 28U)>;
 			prescaler = <32768>;
 			alarms-count = <2>;
 			alrm-exti-line = <17>;
@@ -127,7 +127,7 @@
 		usart2: serial@40004400 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40004400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 17U)>;
 			resets = <&rctl STM32_RESET(APB1, 17U)>;
 			interrupts = <38 0>;
 			status = "disabled";
@@ -136,7 +136,7 @@
 		usart3: serial@40004800 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40004800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
 			resets = <&rctl STM32_RESET(APB1, 18U)>;
 			interrupts = <39 0>;
 			status = "disabled";
@@ -145,7 +145,7 @@
 		uart4: serial@40004c00 {
 			compatible = "st,stm32-uart";
 			reg = <0x40004c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
 			resets = <&rctl STM32_RESET(APB1, 19U)>;
 			interrupts = <48 0>;
 			status = "disabled";
@@ -154,7 +154,7 @@
 		uart5: serial@40005000 {
 			compatible = "st,stm32-uart";
 			reg = <0x40005000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 20U)>;
 			resets = <&rctl STM32_RESET(APB1, 20U)>;
 			interrupts = <49 0>;
 			status = "disabled";
@@ -166,7 +166,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40005400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 21U)>;
 			interrupts = <31 0>, <32 0>;
 			interrupt-names = "event", "error";
 			status = "disabled";
@@ -178,7 +178,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40005800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
 			interrupts = <33 0>, <34 0>;
 			interrupt-names = "event", "error";
 			status = "disabled";
@@ -189,7 +189,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40013000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 12U)>;
 			interrupts = <35 0>;
 			status = "disabled";
 		};
@@ -199,7 +199,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40003800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
 			interrupts = <36 0>;
 			status = "disabled";
 		};
@@ -207,7 +207,7 @@
 		usart1: serial@40013800 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40013800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 14U)>;
 			resets = <&rctl STM32_RESET(APB2, 14U)>;
 			interrupts = <37 0>;
 			status = "disabled";
@@ -216,7 +216,7 @@
 		adc1: adc@40012400 {
 			compatible = "st,stm32f4-adc", "st,stm32-adc";
 			reg = <0x40012400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000200>,
+			clocks = <&rcc STM32_CLOCK(APB2, 9U)>,
 				 <&rcc STM32_SRC_HSI NO_SEL>;
 			interrupts = <18 0>;
 			status = "disabled";
@@ -233,7 +233,7 @@
 		dac1: dac@40007400 {
 			compatible = "st,stm32-dac";
 			reg = <0x40007400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 29U)>;
 			status = "disabled";
 			#io-channel-cells = <1>;
 		};
@@ -256,7 +256,7 @@
 		timers2: timers@40000000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40000000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
+			clocks = <&rcc STM32_CLOCK(APB1, 0U)>;
 			resets = <&rctl STM32_RESET(APB1, 0U)>;
 			interrupts = <28 0>;
 			interrupt-names = "global";
@@ -278,7 +278,7 @@
 		timers3: timers@40000400 {
 			compatible = "st,stm32-timers";
 			reg = <0x40000400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
+			clocks = <&rcc STM32_CLOCK(APB1, 1U)>;
 			resets = <&rctl STM32_RESET(APB1, 1U)>;
 			interrupts = <29 0>;
 			interrupt-names = "global";
@@ -300,7 +300,7 @@
 		timers4: timers@40000800 {
 			compatible = "st,stm32-timers";
 			reg = <0x40000800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
+			clocks = <&rcc STM32_CLOCK(APB1, 2U)>;
 			resets = <&rctl STM32_RESET(APB1, 2U)>;
 			interrupts = <30 0>;
 			interrupt-names = "global";
@@ -322,7 +322,7 @@
 		timers9: timers@40010800 {
 			compatible = "st,stm32-timers";
 			reg = <0x40010800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000004>;
+			clocks = <&rcc STM32_CLOCK(APB2, 2U)>;
 			resets = <&rctl STM32_RESET(APB2, 2U)>;
 			interrupts = <25 0>;
 			interrupt-names = "global";
@@ -344,7 +344,7 @@
 		timers10: timers@40010c00 {
 			compatible = "st,stm32-timers";
 			reg = <0x40010c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000008>;
+			clocks = <&rcc STM32_CLOCK(APB2, 3U)>;
 			resets = <&rctl STM32_RESET(APB2, 3U)>;
 			interrupts = <26 0>;
 			interrupt-names = "global";
@@ -366,7 +366,7 @@
 		timers11: timers@40011000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40011000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000010>;
+			clocks = <&rcc STM32_CLOCK(APB2, 4U)>;
 			resets = <&rctl STM32_RESET(APB2, 4U)>;
 			interrupts = <27 0>;
 			interrupt-names = "global";
@@ -396,7 +396,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x40020000 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000001>;
+				clocks = <&rcc STM32_CLOCK(AHB1, 0U)>;
 			};
 
 			gpiob: gpio@40020400 {
@@ -404,7 +404,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x40020400 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000002>;
+				clocks = <&rcc STM32_CLOCK(AHB1, 1U)>;
 			};
 
 			gpioc: gpio@40020800 {
@@ -412,7 +412,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x40020800 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000004>;
+				clocks = <&rcc STM32_CLOCK(AHB1, 2U)>;
 			};
 
 			gpiod: gpio@40020c00 {
@@ -420,7 +420,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x40020c00 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000008>;
+				clocks = <&rcc STM32_CLOCK(AHB1, 3U)>;
 			};
 
 			gpioe: gpio@40021000 {
@@ -428,7 +428,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x40021000 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000010>;
+				clocks = <&rcc STM32_CLOCK(AHB1, 4U)>;
 			};
 
 			gpioh: gpio@40021400 {
@@ -436,7 +436,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x40021400 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000020>;
+				clocks = <&rcc STM32_CLOCK(AHB1, 5U)>;
 			};
 		};
 
@@ -449,7 +449,7 @@
 		wwdg: watchdog@40002c00 {
 			compatible = "st,stm32-window-watchdog";
 			reg = <0x40002C00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
+			clocks = <&rcc STM32_CLOCK(APB1, 11U)>;
 			interrupts = <0 7>;
 			status = "disabled";
 		};
@@ -463,7 +463,7 @@
 			compatible = "st,stm32-dma-v2bis";
 			#dma-cells = <2>;
 			reg = <0x40026000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1000000>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 24U)>;
 			interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0>;
 			status = "disabled";
 		};

dts/arm/st/l1/stm32l151Xc.dtsi

@@ -22,7 +22,7 @@
 		timers5: timers@40000c00 {
 			compatible = "st,stm32-timers";
 			reg = <0x40000c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
+			clocks = <&rcc STM32_CLOCK(APB1, 3U)>;
 			resets = <&rctl STM32_RESET(APB1, 3U)>;
 			interrupts = <45 0>;
 			interrupt-names = "global";
@@ -41,7 +41,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40003c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
 			interrupts = <47 0>;
 			status = "disabled";
 		};

dts/arm/st/l1/stm32l152Xc.dtsi

@@ -22,7 +22,7 @@
 		timers5: timers@40000c00 {
 			compatible = "st,stm32-timers";
 			reg = <0x40000c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
+			clocks = <&rcc STM32_CLOCK(APB1, 3U)>;
 			resets = <&rctl STM32_RESET(APB1, 3U)>;
 			interrupts = <45 0>;
 			interrupt-names = "global";
@@ -41,7 +41,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40003c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
 			interrupts = <47 0>;
 			status = "disabled";
 		};

dts/arm/st/l1/stm32l152Xe.dtsi

@@ -22,7 +22,7 @@
 		timers5: timers@40000c00 {
 			compatible = "st,stm32-timers";
 			reg = <0x40000c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
+			clocks = <&rcc STM32_CLOCK(APB1, 3U)>;
 			resets = <&rctl STM32_RESET(APB1, 3U)>;
 			interrupts = <45 0>;
 			interrupt-names = "global";
@@ -41,7 +41,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40003c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
 			interrupts = <47 0>;
 			status = "disabled";
 		};

dts/arm/st/l4/stm32l4.dtsi

@@ -118,7 +118,7 @@
 			compatible = "st,stm32-flash-controller", "st,stm32l4-flash-controller";
 			reg = <0x40022000 0x400>;
 			interrupts = <4 0>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000100>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 8U)>;
 
 			#address-cells = <1>;
 			#size-cells = <1>;
@@ -170,7 +170,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x48000000 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000001>;
+				clocks = <&rcc STM32_CLOCK(AHB2, 0U)>;
 			};
 
 			gpiob: gpio@48000400 {
@@ -178,7 +178,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x48000400 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000002>;
+				clocks = <&rcc STM32_CLOCK(AHB2, 1U)>;
 			};
 
 			gpioc: gpio@48000800 {
@@ -186,7 +186,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x48000800 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000004>;
+				clocks = <&rcc STM32_CLOCK(AHB2, 2U)>;
 			};
 
 			gpioh: gpio@48001c00 {
@@ -194,7 +194,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x48001c00 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000080>;
+				clocks = <&rcc STM32_CLOCK(AHB2, 7U)>;
 			};
 		};
 
@@ -207,7 +207,7 @@
 		wwdg: watchdog@40002c00 {
 			compatible = "st,stm32-window-watchdog";
 			reg = <0x40002C00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
+			clocks = <&rcc STM32_CLOCK(APB1, 11U)>;
 			interrupts = <0 7>;
 			status = "disabled";
 		};
@@ -215,7 +215,7 @@
 		usart1: serial@40013800 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40013800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 14U)>;
 			resets = <&rctl STM32_RESET(APB2, 14U)>;
 			interrupts = <37 0>;
 			status = "disabled";
@@ -224,7 +224,7 @@
 		usart2: serial@40004400 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40004400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 17U)>;
 			resets = <&rctl STM32_RESET(APB1L, 17U)>;
 			interrupts = <38 0>;
 			status = "disabled";
@@ -233,7 +233,7 @@
 		lpuart1: serial@40008000 {
 			compatible = "st,stm32-lpuart", "st,stm32-uart";
 			reg = <0x40008000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000001>;
+			clocks = <&rcc STM32_CLOCK(APB1_2, 0U)>;
 			resets = <&rctl STM32_RESET(APB1H, 0U)>;
 			interrupts = <70 0>;
 			status = "disabled";
@@ -245,7 +245,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40005400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 21U)>;
 			interrupts = <31 0>, <32 0>;
 			interrupt-names = "event", "error";
 			status = "disabled";
@@ -257,7 +257,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40005c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 23U)>;
 			interrupts = <72 0>, <73 0>;
 			interrupt-names = "event", "error";
 			status = "disabled";
@@ -269,7 +269,7 @@
 			#size-cells = <0>;
 			reg = <0xa0001000 0x400>;
 			interrupts = <71 0>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00000100>;
+			clocks = <&rcc STM32_CLOCK(AHB3, 8U)>;
 			status = "disabled";
 		};
 
@@ -279,7 +279,7 @@
 			#size-cells = <0>;
 			reg = <0x40013000 0x400>;
 			interrupts = <35 5>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 12U)>;
 			status = "disabled";
 		};
 
@@ -287,7 +287,7 @@
 		timers1: timers@40012c00 {
 			compatible = "st,stm32-timers";
 			reg = <0x40012c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>;
+			clocks = <&rcc STM32_CLOCK(APB2, 11U)>;
 			resets = <&rctl STM32_RESET(APB2, 11U)>;
 			interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
 			interrupt-names = "brk", "up", "trgcom", "cc";
@@ -304,7 +304,7 @@
 		timers2: timers@40000000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40000000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
+			clocks = <&rcc STM32_CLOCK(APB1, 0U)>;
 			resets = <&rctl STM32_RESET(APB1L, 0U)>;
 			interrupts = <28 0>;
 			interrupt-names = "global";
@@ -326,7 +326,7 @@
 		timers6: timers@40001000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40001000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
+			clocks = <&rcc STM32_CLOCK(APB1, 4U)>;
 			resets = <&rctl STM32_RESET(APB1L, 4U)>;
 			interrupts = <54 0>;
 			interrupt-names = "global";
@@ -342,7 +342,7 @@
 		timers15: timers@40014000 {
 			compatible = "st,stm32-timers";
 			reg = <0x40014000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00010000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 16U)>;
 			resets = <&rctl STM32_RESET(APB2, 16U)>;
 			interrupts = <24 0>;
 			interrupt-names = "global";
@@ -364,7 +364,7 @@
 		timers16: timers@40014400 {
 			compatible = "st,stm32-timers";
 			reg = <0x40014400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00020000>;
+			clocks = <&rcc STM32_CLOCK(APB2, 17U)>;
 			resets = <&rctl STM32_RESET(APB2, 17U)>;
 			interrupts = <25 0>;
 			interrupt-names = "global";
@@ -387,7 +387,7 @@
 			compatible = "st,stm32-rtc";
 			reg = <0x40002800 0x400>;
 			interrupts = <41 0>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 28U)>;
 			prescaler = <32768>;
 			alarms-count = <2>;
 			alrm-exti-line = <18>;
@@ -397,7 +397,7 @@
 		adc1: adc@50040000 {
 			compatible = "st,stm32-adc";
 			reg = <0x50040000 0x100>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00002000>;
+			clocks = <&rcc STM32_CLOCK(AHB2, 13U)>;
 			interrupts = <18 0>;
 			status = "disabled";
 			#io-channel-cells = <1>;
@@ -412,7 +412,7 @@
 		adc2: adc@50040100 {
 			compatible = "st,stm32-adc";
 			reg = <0x50040100 0x100>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00002000>;
+			clocks = <&rcc STM32_CLOCK(AHB2, 13U)>;
 			interrupts = <18 0>;
 			status = "disabled";
 			#io-channel-cells = <1>;
@@ -429,7 +429,7 @@
 			#dma-cells = <3>;
 			reg = <0x40020000 0x400>;
 			interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 0U)>;
 			dma-requests = <7>;
 			status = "disabled";
 		};
@@ -439,14 +439,14 @@
 			#dma-cells = <3>;
 			reg = <0x40020400 0x400>;
 			interrupts = <56 0 57 0 58 0 59 0 60 0 68 0 69 0>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 1U)>;
 			dma-requests = <7>;
 			status = "disabled";
 		};
 
 		lptim1: timers@40007c00 {
 			compatible = "st,stm32-lptim";
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 31U)>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40007c00 0x400>;
@@ -460,7 +460,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40009400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000020>;
+			clocks = <&rcc STM32_CLOCK(APB1_2, 5U)>;
 			interrupts = <66 1>;
 			interrupt-names = "wakeup";
 			status = "disabled";
@@ -470,7 +470,7 @@
 			compatible = "st,stm32-rng";
 			reg = <0x50060800 0x400>;
 			interrupts = <80 0>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00040000>,
+			clocks = <&rcc STM32_CLOCK(AHB2, 18U)>,
 				/* Following domain clock setting requires MSI
 				 * clock to be enabled with msi-range = <11>;
 				 */

dts/arm/st/l4/stm32l412.dtsi

@@ -22,7 +22,7 @@
 
 
 		rng: rng@50060800 {
-			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00040000>,
+			clocks = <&rcc STM32_CLOCK(AHB2, 18U)>,
 				 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
 		};
 
@@ -35,7 +35,7 @@
 			ram-size = <1024>;
 			maximum-speed = "full-speed";
 			phys = <&usb_fs_phy>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x04000000>,
+			clocks = <&rcc STM32_CLOCK(APB1, 26U)>,
 				 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
 			status = "disabled";
 		};
@@ -45,7 +45,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40005800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
 			clock-frequency = <I2C_BITRATE_STANDARD>;
 			interrupts = <33 0>, <34 0>;
 			interrupt-names = "event", "error";
@@ -58,14 +58,14 @@
 			#size-cells = <0>;
 			reg = <0x40003800 0x400>;
 			interrupts = <36 5>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
 			status = "disabled";
 		};
 
 		usart3: serial@40004800 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40004800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
 			resets = <&rctl STM32_RESET(APB1L, 18U)>;
 			interrupts = <39 0>;
 			status = "disabled";

dts/arm/st/l4/stm32l422.dtsi

@@ -13,7 +13,7 @@
 		aes: aes@50060000 {
 			compatible = "st,stm32l4-aes", "st,stm32-aes";
 			reg = <0x50060000 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00010000>;
+			clocks = <&rcc STM32_CLOCK(AHB2, 16U)>;
 			resets = <&rctl STM32_RESET(AHB2, 16U)>;
 			interrupts = <79 0>;
 			interrupt-names = "aes";

dts/arm/st/l4/stm32l431.dtsi

@@ -25,7 +25,7 @@
 			gpiod: gpio@48000c00 {
 				compatible = "st,stm32-gpio";
 				reg = <0x48000c00 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000008>;
+				clocks = <&rcc STM32_CLOCK(AHB2, 3U)>;
 				gpio-controller;
 				#gpio-cells = <2>;
 			};
@@ -33,7 +33,7 @@
 			gpioe: gpio@48001000 {
 				compatible = "st,stm32-gpio";
 				reg = <0x48001000 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
+				clocks = <&rcc STM32_CLOCK(AHB2, 4U)>;
 				gpio-controller;
 				#gpio-cells = <2>;
 			};
@@ -41,7 +41,7 @@
 		};
 
 		rng: rng@50060800 {
-			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00040000>,
+			clocks = <&rcc STM32_CLOCK(AHB2, 18U)>,
 				 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
 		};
 
@@ -50,7 +50,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40005800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
 			clock-frequency = <I2C_BITRATE_STANDARD>;
 			interrupts = <33 0>, <34 0>;
 			interrupt-names = "event", "error";
@@ -62,7 +62,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40003800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
 			interrupts = <36 5>;
 			status = "disabled";
 		};
@@ -72,7 +72,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40003c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
 			interrupts = <51 5>;
 			status = "disabled";
 		};
@@ -80,7 +80,7 @@
 		usart3: serial@40004800 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40004800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
 			resets = <&rctl STM32_RESET(APB1L, 18U)>;
 			interrupts = <39 0>;
 			status = "disabled";
@@ -89,7 +89,7 @@
 		timers7: timers@40001400 {
 			compatible = "st,stm32-timers";
 			reg = <0x40001400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
+			clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
 			resets = <&rctl STM32_RESET(APB1L, 5U)>;
 			interrupts = <55 0>;
 			interrupt-names = "global";
@@ -105,7 +105,7 @@
 		can1: can@40006400 {
 			compatible = "st,stm32-bxcan";
 			reg = <0x40006400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 25U)>;
 			interrupts = <19 0>, <20 0>, <21 0>, <22 0>;
 			interrupt-names = "TX", "RX0", "RX1", "SCE";
 			status = "disabled";
@@ -114,7 +114,7 @@
 		sdmmc1: sdmmc@40012800 {
 			compatible = "st,stm32-sdmmc";
 			reg = <0x40012800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000400>,
+			clocks = <&rcc STM32_CLOCK(APB2, 10U)>,
 				 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
 			resets = <&rctl STM32_RESET(APB2, 10U)>;
 			interrupts = <49 0>;
@@ -124,7 +124,7 @@
 		dac1: dac@40007400 {
 			compatible = "st,stm32-dac";
 			reg = <0x40007400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 29U)>;
 			#io-channel-cells = <1>;
 			status = "disabled";
 		};

dts/arm/st/l4/stm32l432.dtsi

@@ -21,7 +21,7 @@
 		compatible = "st,stm32l432", "st,stm32l4", "simple-bus";
 
 		rng: rng@50060800 {
-			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00040000>,
+			clocks = <&rcc STM32_CLOCK(AHB2, 18U)>,
 				 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
 		};
 
@@ -30,7 +30,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40003c00 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
 			interrupts = <51 5>;
 			status = "disabled";
 		};
@@ -38,7 +38,7 @@
 		timers7: timers@40001400 {
 			compatible = "st,stm32-timers";
 			reg = <0x40001400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
+			clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
 			resets = <&rctl STM32_RESET(APB1L, 5U)>;
 			interrupts = <55 0>;
 			interrupt-names = "global";
@@ -56,7 +56,7 @@
 			reg = <0x40006400 0x400>;
 			interrupts = <19 0>, <20 0>, <21 0>, <22 0>;
 			interrupt-names = "TX", "RX0", "RX1", "SCE";
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>; //RCC_APB1ENR1_CAN1EN
+			clocks = <&rcc STM32_CLOCK(APB1, 25U)>; //RCC_APB1ENR1_CAN1EN
 			status = "disabled";
 		};
 
@@ -69,7 +69,7 @@
 			ram-size = <1024>;
 			maximum-speed = "full-speed";
 			phys = <&usb_fs_phy>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x04000000>,
+			clocks = <&rcc STM32_CLOCK(APB1, 26U)>,
 				 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
 			status = "disabled";
 		};
@@ -77,7 +77,7 @@
 		dac1: dac@40007400 {
 			compatible = "st,stm32-dac";
 			reg = <0x40007400 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 29U)>;
 			status = "disabled";
 			#io-channel-cells = <1>;
 		};

dts/arm/st/l4/stm32l433.dtsi

@@ -16,7 +16,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x48000c00 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000008>;
+				clocks = <&rcc STM32_CLOCK(AHB2, 3U)>;
 			};
 
 			gpioe: gpio@48001000 {
@@ -24,7 +24,7 @@
 				gpio-controller;
 				#gpio-cells = <2>;
 				reg = <0x48001000 0x400>;
-				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
+				clocks = <&rcc STM32_CLOCK(AHB2, 4U)>;
 			};
 		};
 
@@ -34,7 +34,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40005800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
 			interrupts = <33 0>, <34 0>;
 			interrupt-names = "event", "error";
 			status = "disabled";
@@ -45,7 +45,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x40003800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
 			interrupts = <36 5>;
 			status = "disabled";
 		};
@@ -53,7 +53,7 @@
 		usart3: serial@40004800 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40004800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
+			clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
 			resets = <&rctl STM32_RESET(APB1L, 18U)>;
 			interrupts = <39 0>;
 			status = "disabled";
@@ -62,7 +62,7 @@
 		sdmmc1: sdmmc@40012800 {
 			compatible = "st,stm32-sdmmc";
 			reg = <0x40012800 0x400>;
-			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000400>,
+			clocks = <&rcc STM32_CLOCK(APB2, 10U)>,
 				 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
 			interrupts = <49 0>;
 			status = "disabled";