drivers: npcx: Add const modifier for hal instances and so on.

Add const modifier for hal instances, clock devices pointer, and module
base address in npcx drivers to prevent driver functions change them
unexpectedly.

Signed-off-by: Mulin Chao <MLChao@nuvoton.com>

drivers/clock_control/clock_control_npcx.c

@@ -37,7 +37,7 @@ static inline int npcx_clock_control_on(const struct device *dev,
 {
 	ARG_UNUSED(dev);
 	struct npcx_clk_cfg *clk_cfg = (struct npcx_clk_cfg *)(sub_system);
-	uint32_t pmc_base = DRV_CONFIG(dev)->base_pmc;
+	const uint32_t pmc_base = DRV_CONFIG(dev)->base_pmc;
 
 	/* Clear related PD (Power-Down) bit of module to turn on clock */
 	NPCX_PWDWN_CTL(pmc_base, clk_cfg->ctrl) &= ~(BIT(clk_cfg->bit));
@@ -49,7 +49,7 @@ static inline int npcx_clock_control_off(const struct device *dev,
 {
 	ARG_UNUSED(dev);
 	struct npcx_clk_cfg *clk_cfg = (struct npcx_clk_cfg *)(sub_system);
-	uint32_t pmc_base = DRV_CONFIG(dev)->base_pmc;
+	const uint32_t pmc_base = DRV_CONFIG(dev)->base_pmc;
 
 	/* Set related PD (Power-Down) bit of module to turn off clock */
 	NPCX_PWDWN_CTL(pmc_base, clk_cfg->ctrl) |= BIT(clk_cfg->bit);
@@ -103,8 +103,8 @@ static struct clock_control_driver_api npcx_clock_control_api = {
 
 static int npcx_clock_control_init(const struct device *dev)
 {
-	struct cdcg_reg *inst_cdcg = HAL_CDCG_INST(dev);
-	uint32_t pmc_base = DRV_CONFIG(dev)->base_pmc;
+	struct cdcg_reg *const inst_cdcg = HAL_CDCG_INST(dev);
+	const uint32_t pmc_base = DRV_CONFIG(dev)->base_pmc;
 
 	/*
 	 * Resetting the OSC_CLK (even to the same value) will make the clock

drivers/gpio/gpio_npcx.c

@@ -49,7 +49,6 @@ struct gpio_npcx_data {
 
 #define HAL_INSTANCE(dev) (struct gpio_reg *)(DRV_CONFIG(dev)->base)
 
-
 /* Soc specific GPIO functions */
 const struct device *soc_get_gpio_dev(int port)
 {
@@ -63,7 +62,7 @@ const struct device *soc_get_gpio_dev(int port)
 static int gpio_npcx_config(const struct device *dev,
 			     gpio_pin_t pin, gpio_flags_t flags)
 {
-	struct gpio_reg *inst = HAL_INSTANCE(dev);
+	struct gpio_reg *const inst = HAL_INSTANCE(dev);
 	uint32_t mask = BIT(pin);
 
 	/* Don't support simultaneous in/out mode */
@@ -119,7 +118,7 @@ static int gpio_npcx_config(const struct device *dev,
 static int gpio_npcx_port_get_raw(const struct device *dev,
 				  gpio_port_value_t *value)
 {
-	struct gpio_reg *inst = HAL_INSTANCE(dev);
+	struct gpio_reg *const inst = HAL_INSTANCE(dev);
 
 	/* Get raw bits of GPIO input registers */
 	*value = inst->PDIN;
@@ -131,7 +130,7 @@ static int gpio_npcx_port_set_masked_raw(const struct device *dev,
 					  gpio_port_pins_t mask,
 					  gpio_port_value_t value)
 {
-	struct gpio_reg *inst = HAL_INSTANCE(dev);
+	struct gpio_reg *const inst = HAL_INSTANCE(dev);
 	uint8_t out = inst->PDOUT;
 
 	inst->PDOUT = ((out & ~mask) | (value & mask));
@@ -142,7 +141,7 @@ static int gpio_npcx_port_set_masked_raw(const struct device *dev,
 static int gpio_npcx_port_set_bits_raw(const struct device *dev,
 					gpio_port_value_t mask)
 {
-	struct gpio_reg *inst = HAL_INSTANCE(dev);
+	struct gpio_reg *const inst = HAL_INSTANCE(dev);
 
 	/* Set raw bits of GPIO output registers */
 	inst->PDOUT |= mask;
@@ -153,7 +152,7 @@ static int gpio_npcx_port_set_bits_raw(const struct device *dev,
 static int gpio_npcx_port_clear_bits_raw(const struct device *dev,
 						gpio_port_value_t mask)
 {
-	struct gpio_reg *inst = HAL_INSTANCE(dev);
+	struct gpio_reg *const inst = HAL_INSTANCE(dev);
 
 	/* Clear raw bits of GPIO output registers */
 	inst->PDOUT &= ~mask;
@@ -164,7 +163,7 @@ static int gpio_npcx_port_clear_bits_raw(const struct device *dev,
 static int gpio_npcx_port_toggle_bits(const struct device *dev,
 						gpio_port_value_t mask)
 {
-	struct gpio_reg *inst = HAL_INSTANCE(dev);
+	struct gpio_reg *const inst = HAL_INSTANCE(dev);
 
 	/* Toggle raw bits of GPIO output registers */
 	inst->PDOUT ^= mask;
@@ -177,7 +176,7 @@ static int gpio_npcx_pin_interrupt_configure(const struct device *dev,
 					     enum gpio_int_mode mode,
 					     enum gpio_int_trig trig)
 {
-	const struct gpio_npcx_config *config = DRV_CONFIG(dev);
+	const struct gpio_npcx_config *const config = DRV_CONFIG(dev);
 	enum miwu_int_mode miwu_mode = NPCX_MIWU_MODE_DISABLED;
 	enum miwu_int_trig miwu_trig = NPCX_MIWU_TRIG_NONE;
 
@@ -222,7 +221,7 @@ static int gpio_npcx_pin_interrupt_configure(const struct device *dev,
 static int gpio_npcx_manage_callback(const struct device *dev,
 				      struct gpio_callback *callback, bool set)
 {
-	const struct gpio_npcx_config *config = DRV_CONFIG(dev);
+	const struct gpio_npcx_config *const config = DRV_CONFIG(dev);
 	struct miwu_io_callback *miwu_cb = (struct miwu_io_callback *)callback;
 	int pin = find_lsb_set(callback->pin_mask) - 1;
 

drivers/interrupt_controller/intc_miwu.c

@@ -135,7 +135,7 @@ static void intc_miwu_dispatch_generic_isr(uint8_t wui_table,
 static void intc_miwu_isr_pri(int wui_table, int wui_group)
 {
 	int wui_bit;
-	uint32_t base = DRV_CONFIG(miwu_devs[wui_table])->base;
+	const uint32_t base = DRV_CONFIG(miwu_devs[wui_table])->base;
 	uint8_t mask = NPCX_WKPND(base, wui_group) & NPCX_WKEN(base, wui_group);
 
 	/* Clear pending bits before dispatch ISR */
@@ -158,21 +158,21 @@ static void intc_miwu_isr_pri(int wui_table, int wui_group)
 /* Soc specific MIWU functions */
 void soc_miwu_irq_enable(const struct npcx_wui *wui)
 {
-	uint32_t base = DRV_CONFIG(miwu_devs[wui->table])->base;
+	const uint32_t base = DRV_CONFIG(miwu_devs[wui->table])->base;
 
 	NPCX_WKEN(base, wui->group) |= BIT(wui->bit);
 }
 
 void soc_miwu_irq_disable(const struct npcx_wui *wui)
 {
-	uint32_t base = DRV_CONFIG(miwu_devs[wui->table])->base;
+	const uint32_t base = DRV_CONFIG(miwu_devs[wui->table])->base;
 
 	NPCX_WKEN(base, wui->group) &= ~BIT(wui->bit);
 }
 
 unsigned int soc_miwu_irq_get_state(const struct npcx_wui *wui)
 {
-	uint32_t base = DRV_CONFIG(miwu_devs[wui->table])->base;
+	const uint32_t base = DRV_CONFIG(miwu_devs[wui->table])->base;
 
 	if (IS_BIT_SET(NPCX_WKEN(base, wui->group), wui->bit))
 		return 1;
@@ -183,7 +183,7 @@ unsigned int soc_miwu_irq_get_state(const struct npcx_wui *wui)
 int soc_miwu_interrupt_configure(const struct npcx_wui *wui,
 		enum miwu_int_mode mode, enum miwu_int_trig trig)
 {
-	uint32_t base = DRV_CONFIG(miwu_devs[wui->table])->base;
+	const uint32_t base = DRV_CONFIG(miwu_devs[wui->table])->base;
 	uint8_t pmask = BIT(wui->bit);
 
 	if (mode == NPCX_MIWU_MODE_DISABLED) {
@@ -329,7 +329,7 @@ int soc_miwu_manage_dev_callback(struct miwu_dev_callback *cb, bool set)
 	static int intc_miwu_init##inst(const struct device *dev)              \
 	{                                                                      \
 		int i;                                                         \
-		uint32_t base = DRV_CONFIG(dev)->base;                         \
+		const uint32_t base = DRV_CONFIG(dev)->base;                   \
 									       \
 		/* Clear all MIWUs' pending and enable bits of MIWU device */  \
 		for (i = 0; i < NPCX_MIWU_GROUP_COUNT; i++) {                  \

drivers/pinmux/pinmux_npcx.c

@@ -35,7 +35,7 @@ static const struct npcx_pinctrl_config npcx_pinctrl_cfg = {
 /* Pin-control local functions */
 static void npcx_pinctrl_alt_sel(const struct npcx_alt *alt, int alt_func)
 {
-	uint32_t scfg_base = npcx_pinctrl_cfg.base;
+	const uint32_t scfg_base = npcx_pinctrl_cfg.base;
 	uint8_t alt_mask = BIT(alt->bit);
 
 	/*
@@ -65,7 +65,7 @@ void soc_pinctrl_mux_configure(const struct npcx_alt *alts_list,
 /* Pin-control driver registration */
 static int npcx_pinctrl_init(const struct device *dev)
 {
-	struct scfg_reg *inst = HAL_INSTANCE(dev);
+	struct scfg_reg *const inst = HAL_INSTANCE(dev);
 
 #if defined(CONFIG_SOC_SERIES_NPCX7)
 	/*

drivers/serial/uart_npcx.c

@@ -53,7 +53,7 @@ struct uart_npcx_data {
 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
 static int uart_npcx_tx_fifo_ready(const struct device *dev)
 {
-	struct uart_reg *inst = HAL_INSTANCE(dev);
+	struct uart_reg *const inst = HAL_INSTANCE(dev);
 
 	/* True if the Tx FIFO is not completely full */
 	return !(GET_FIELD(inst->UFTSTS, NPCX_UFTSTS_TEMPTY_LVL) == 0);
@@ -61,7 +61,7 @@ static int uart_npcx_tx_fifo_ready(const struct device *dev)
 
 static int uart_npcx_rx_fifo_available(const struct device *dev)
 {
-	struct uart_reg *inst = HAL_INSTANCE(dev);
+	struct uart_reg *const inst = HAL_INSTANCE(dev);
 
 	/* True if at least one byte is in the Rx FIFO */
 	return IS_BIT_SET(inst->UFRSTS, NPCX_UFRSTS_RFIFO_NEMPTY_STS);
@@ -69,7 +69,7 @@ static int uart_npcx_rx_fifo_available(const struct device *dev)
 
 static void uart_npcx_dis_all_tx_interrupts(const struct device *dev)
 {
-	struct uart_reg *inst = HAL_INSTANCE(dev);
+	struct uart_reg *const inst = HAL_INSTANCE(dev);
 
 	/* Disable all Tx interrupts */
 	inst->UFTCTL &= ~(BIT(NPCX_UFTCTL_TEMPTY_LVL_EN) |
@@ -79,7 +79,7 @@ static void uart_npcx_dis_all_tx_interrupts(const struct device *dev)
 
 static void uart_npcx_clear_rx_fifo(const struct device *dev)
 {
-	struct uart_reg *inst = HAL_INSTANCE(dev);
+	struct uart_reg *const inst = HAL_INSTANCE(dev);
 	uint8_t scratch;
 
 	/* Read all dummy bytes out from Rx FIFO */
@@ -91,7 +91,7 @@ static void uart_npcx_clear_rx_fifo(const struct device *dev)
 /* UART api functions */
 static int uart_npcx_poll_in(const struct device *dev, unsigned char *c)
 {
-	struct uart_reg *inst = HAL_INSTANCE(dev);
+	struct uart_reg *const inst = HAL_INSTANCE(dev);
 
 	/* Rx single byte buffer is not full */
 	if (!IS_BIT_SET(inst->UICTRL, NPCX_UICTRL_RBF))
@@ -103,7 +103,7 @@ static int uart_npcx_poll_in(const struct device *dev, unsigned char *c)
 
 static void uart_npcx_poll_out(const struct device *dev, unsigned char c)
 {
-	struct uart_reg *inst = HAL_INSTANCE(dev);
+	struct uart_reg *const inst = HAL_INSTANCE(dev);
 
 	/* Wait while Tx single byte buffer is ready to send */
 	while (!IS_BIT_SET(inst->UICTRL, NPCX_UICTRL_TBE))
@@ -114,7 +114,7 @@ static void uart_npcx_poll_out(const struct device *dev, unsigned char c)
 
 static int uart_npcx_err_check(const struct device *dev)
 {
-	struct uart_reg *inst = HAL_INSTANCE(dev);
+	struct uart_reg *const inst = HAL_INSTANCE(dev);
 	uint32_t err = 0U;
 	uint8_t stat = inst->USTAT;
 
@@ -135,7 +135,7 @@ static int uart_npcx_fifo_fill(const struct device *dev,
 				  const uint8_t *tx_data,
 				  int size)
 {
-	struct uart_reg *inst = HAL_INSTANCE(dev);
+	struct uart_reg *const inst = HAL_INSTANCE(dev);
 	uint8_t tx_bytes = 0U;
 
 	/* If Tx FIFO is still ready to send */
@@ -150,7 +150,7 @@ static int uart_npcx_fifo_fill(const struct device *dev,
 static int uart_npcx_fifo_read(const struct device *dev, uint8_t *rx_data,
 				  const int size)
 {
-	struct uart_reg *inst = HAL_INSTANCE(dev);
+	struct uart_reg *const inst = HAL_INSTANCE(dev);
 	unsigned int rx_bytes = 0U;
 
 	/* If least one byte is in the Rx FIFO */
@@ -164,21 +164,21 @@ static int uart_npcx_fifo_read(const struct device *dev, uint8_t *rx_data,
 
 static void uart_npcx_irq_tx_enable(const struct device *dev)
 {
-	struct uart_reg *inst = HAL_INSTANCE(dev);
+	struct uart_reg *const inst = HAL_INSTANCE(dev);
 
 	inst->UFTCTL |= BIT(NPCX_UFTCTL_TEMPTY_EN);
 }
 
 static void uart_npcx_irq_tx_disable(const struct device *dev)
 {
-	struct uart_reg *inst = HAL_INSTANCE(dev);
+	struct uart_reg *const inst = HAL_INSTANCE(dev);
 
 	inst->UFTCTL &= ~(BIT(NPCX_UFTCTL_TEMPTY_EN));
 }
 
 static int uart_npcx_irq_tx_ready(const struct device *dev)
 {
-	struct uart_reg *inst = HAL_INSTANCE(dev);
+	struct uart_reg *const inst = HAL_INSTANCE(dev);
 
 	/* Tx interrupt is enable and its FIFO is ready to send (not full) */
 	return (IS_BIT_SET(inst->UFTCTL, NPCX_UFTCTL_TEMPTY_EN) &&
@@ -187,7 +187,7 @@ static int uart_npcx_irq_tx_ready(const struct device *dev)
 
 static int uart_npcx_irq_tx_complete(const struct device *dev)
 {
-	struct uart_reg *inst = HAL_INSTANCE(dev);
+	struct uart_reg *const inst = HAL_INSTANCE(dev);
 
 	/* Tx FIFO is empty or last byte is sending */
 	return IS_BIT_SET(inst->UFTSTS, NPCX_UFTSTS_NXMIP);
@@ -195,21 +195,21 @@ static int uart_npcx_irq_tx_complete(const struct device *dev)
 
 static void uart_npcx_irq_rx_enable(const struct device *dev)
 {
-	struct uart_reg *inst = HAL_INSTANCE(dev);
+	struct uart_reg *const inst = HAL_INSTANCE(dev);
 
 	inst->UFRCTL |= BIT(NPCX_UFRCTL_RNEMPTY_EN);
 }
 
 static void uart_npcx_irq_rx_disable(const struct device *dev)
 {
-	struct uart_reg *inst = HAL_INSTANCE(dev);
+	struct uart_reg *const inst = HAL_INSTANCE(dev);
 
 	inst->UFRCTL &= ~(BIT(NPCX_UFRCTL_RNEMPTY_EN));
 }
 
 static int uart_npcx_irq_rx_ready(const struct device *dev)
 {
-	struct uart_reg *inst = HAL_INSTANCE(dev);
+	struct uart_reg *const inst = HAL_INSTANCE(dev);
 
 	/* Rx interrupt is enable and at least one byte is in its FIFO */
 	return (IS_BIT_SET(inst->UFRCTL, NPCX_UFRCTL_RNEMPTY_EN) &&
@@ -218,14 +218,14 @@ static int uart_npcx_irq_rx_ready(const struct device *dev)
 
 static void uart_npcx_irq_err_enable(const struct device *dev)
 {
-	struct uart_reg *inst = HAL_INSTANCE(dev);
+	struct uart_reg *const inst = HAL_INSTANCE(dev);
 
 	inst->UICTRL |= BIT(NPCX_UICTRL_EEI);
 }
 
 static void uart_npcx_irq_err_disable(const struct device *dev)
 {
-	struct uart_reg *inst = HAL_INSTANCE(dev);
+	struct uart_reg *const inst = HAL_INSTANCE(dev);
 
 	inst->UICTRL &= ~(BIT(NPCX_UICTRL_EEI));
 }
@@ -288,10 +288,11 @@ static const struct uart_driver_api uart_npcx_driver_api = {
 
 static int uart_npcx_init(const struct device *dev)
 {
-	const struct uart_npcx_config *config = DRV_CONFIG(dev);
-	const struct uart_npcx_data *data = DRV_DATA(dev);
-	struct uart_reg *inst = HAL_INSTANCE(dev);
-	const struct device *clk_dev = device_get_binding(NPCX_CLK_CTRL_NAME);
+	const struct uart_npcx_config *const config = DRV_CONFIG(dev);
+	const struct uart_npcx_data *const data = DRV_DATA(dev);
+	struct uart_reg *const inst = HAL_INSTANCE(dev);
+	const struct device *const clk_dev =
+					device_get_binding(NPCX_CLK_CTRL_NAME);
 	uint32_t uart_rate;
 
 	/* Turn on device clock first */