From 4a9412b5d45ff4e659bde8f197b4b0e54c9238fb Mon Sep 17 00:00:00 2001 From: Hao Luo Date: Fri, 23 May 2025 09:45:09 +0800 Subject: [PATCH] drivers: adc: add dma support for ambiq adc driver This commit adds dma support for ambiq adc driver Signed-off-by: Hao Luo --- .../apollo510_evb/apollo510_evb-pinctrl.dtsi | 2 +- boards/rakwireless/rak11720/rak11720.dts | 4 - drivers/adc/Kconfig.ambiq | 12 + drivers/adc/adc_ambiq.c | 260 ++++++++++++++---- dts/arm/ambiq/ambiq_apollo3_blue.dtsi | 9 - dts/arm/ambiq/ambiq_apollo3p_blue.dtsi | 9 - dts/bindings/adc/ambiq,adc.yaml | 14 + .../adc/adc_dt/boards/apollo3_evb.overlay | 1 + .../adc/adc_dt/boards/apollo510_evb.overlay | 13 +- 9 files changed, 242 insertions(+), 82 deletions(-) diff --git a/boards/ambiq/apollo510_evb/apollo510_evb-pinctrl.dtsi b/boards/ambiq/apollo510_evb/apollo510_evb-pinctrl.dtsi index a57fcdd95fb..797ce0b96d1 100644 --- a/boards/ambiq/apollo510_evb/apollo510_evb-pinctrl.dtsi +++ b/boards/ambiq/apollo510_evb/apollo510_evb-pinctrl.dtsi @@ -32,7 +32,7 @@ adc0_default: adc0_default{ group1 { - pinmux = , ; + pinmux = , ; drive-strength = "0.1"; }; }; diff --git a/boards/rakwireless/rak11720/rak11720.dts b/boards/rakwireless/rak11720/rak11720.dts index 6596d689962..12fc1d7966b 100644 --- a/boards/rakwireless/rak11720/rak11720.dts +++ b/boards/rakwireless/rak11720/rak11720.dts @@ -162,10 +162,6 @@ status = "okay"; }; -&counter3 { - status = "okay"; -}; - &counter4 { status = "okay"; }; diff --git a/drivers/adc/Kconfig.ambiq b/drivers/adc/Kconfig.ambiq index 8b0e59a062d..be9ab0fcf9f 100644 --- a/drivers/adc/Kconfig.ambiq +++ b/drivers/adc/Kconfig.ambiq @@ -8,5 +8,17 @@ config ADC_AMBIQ depends on DT_HAS_AMBIQ_ADC_ENABLED select AMBIQ_HAL select AMBIQ_HAL_USE_ADC + select AMBIQ_HAL_USE_TIMER if SOC_SERIES_APOLLO3X help Enables the Adc driver for Ambiq devices. + +if ADC_AMBIQ + +config ADC_AMBIQ_HANDLE_CACHE + bool "Turn on cache handling in adc driver" + default y + depends on CACHE_MANAGEMENT && DCACHE + help + Disable this if cache has been handled in upper layers. + +endif # ADC_AMBIQ diff --git a/drivers/adc/adc_ambiq.c b/drivers/adc/adc_ambiq.c index ac8f7793f07..cfeac9b590f 100644 --- a/drivers/adc/adc_ambiq.c +++ b/drivers/adc/adc_ambiq.c @@ -11,6 +11,7 @@ #include #include #include +#include #define ADC_CONTEXT_USES_KERNEL_TIMER #include "adc_context.h" @@ -22,7 +23,14 @@ LOG_MODULE_REGISTER(adc_ambiq, CONFIG_ADC_LOG_LEVEL); /* Number of slots available. */ -#define AMBIQ_ADC_SLOT_NUMBER AM_HAL_ADC_MAX_SLOTS +#define AMBIQ_ADC_SLOT_NUMBER AM_HAL_ADC_MAX_SLOTS +#define ADC_TRANSFER_TIMEOUT_MSEC 500 + +#if defined(CONFIG_SOC_SERIES_APOLLO3X) +#define AMBIQ_ADC_DMA_INT (AM_HAL_ADC_INT_DERR | AM_HAL_ADC_INT_DCMP) +#else +#define AMBIQ_ADC_DMA_INT (AM_HAL_ADC_INT_DERR | AM_HAL_ADC_INT_DCMP | AM_HAL_ADC_INT_FIFOOVR1) +#endif struct adc_ambiq_config { uint32_t base; @@ -35,9 +43,13 @@ struct adc_ambiq_config { struct adc_ambiq_data { struct adc_context ctx; void *adcHandle; - uint16_t *buffer; - uint16_t *repeat_buffer; + uint32_t *buffer; + uint32_t *repeat_buffer; uint8_t active_channels; + struct k_sem dma_done_sem; + am_hal_adc_dma_config_t dma_cfg; + am_hal_adc_sample_t *sample_buf; + bool dma_mode; }; static int adc_ambiq_set_resolution(am_hal_adc_slot_prec_e *prec, uint8_t adc_resolution) @@ -64,6 +76,39 @@ static int adc_ambiq_set_resolution(am_hal_adc_slot_prec_e *prec, uint8_t adc_re return 0; } +static int adc_ambiq_config(const struct device *dev) +{ + struct adc_ambiq_data *data = dev->data; + am_hal_adc_config_t ADCConfig; + + /* Set up the ADC configuration parameters. These settings are reasonable + * for accurate measurements at a low sample rate. + */ +#if defined(CONFIG_SOC_SERIES_APOLLO3X) + ADCConfig.eClock = AM_HAL_ADC_CLKSEL_HFRC; + ADCConfig.eReference = AM_HAL_ADC_REFSEL_INT_1P5; +#else + ADCConfig.eClock = AM_HAL_ADC_CLKSEL_HFRC_24MHZ; + ADCConfig.eRepeatTrigger = AM_HAL_ADC_RPTTRIGSEL_INT; +#endif + ADCConfig.ePolarity = AM_HAL_ADC_TRIGPOL_RISING; + ADCConfig.eTrigger = AM_HAL_ADC_TRIGSEL_SOFTWARE; + ADCConfig.eClockMode = AM_HAL_ADC_CLKMODE_LOW_LATENCY; + ADCConfig.ePowerMode = AM_HAL_ADC_LPMODE0; + if (data->dma_mode) { + ADCConfig.eRepeat = AM_HAL_ADC_REPEATING_SCAN; + } else { + ADCConfig.eRepeat = AM_HAL_ADC_SINGLE_SCAN; + } + + if (AM_HAL_STATUS_SUCCESS != am_hal_adc_configure(data->adcHandle, &ADCConfig)) { + LOG_ERR("configuring ADC failed.\n"); + return -ENODEV; + } + + return 0; +} + static int adc_ambiq_slot_config(const struct device *dev, const struct adc_sequence *sequence, am_hal_adc_slot_chan_e channel, uint32_t ui32SlotNumber) { @@ -92,6 +137,22 @@ static int adc_ambiq_slot_config(const struct device *dev, const struct adc_sequ return 0; } +static void adc_ambiq_disable(const struct device *dev) +{ + struct adc_ambiq_data *data = dev->data; + am_hal_adc_slot_config_t ADCSlotConfig; + + am_hal_adc_interrupt_disable(data->adcHandle, 0xFF); + ADCSlotConfig.bEnabled = false; + for (uint8_t slotNum = 0; slotNum < AM_HAL_ADC_MAX_SLOTS; slotNum++) { + am_hal_adc_configure_slot(data->adcHandle, slotNum, &ADCSlotConfig); + } + if (data->dma_mode) { + ADCn(0)->DMACFG_b.DMAEN = 0; + } + am_hal_adc_disable(data->adcHandle); +} + static void adc_ambiq_isr(const struct device *dev) { struct adc_ambiq_data *data = dev->data; @@ -114,9 +175,21 @@ static void adc_ambiq_isr(const struct device *dev) &Sample); *data->buffer++ = Sample.ui32Sample; } - am_hal_adc_disable(data->adcHandle); + adc_ambiq_disable(dev); adc_context_on_sampling_done(&data->ctx, dev); } + + if (data->dma_mode) { +#if defined(CONFIG_SOC_SERIES_APOLLO3X) + if (ui32IntMask & AM_HAL_ADC_INT_DCMP) { +#else + if (((ui32IntMask & AM_HAL_ADC_INT_FIFOOVR1) && (ADCn(0)->DMASTAT_b.DMACPL)) || + (ui32IntMask & AM_HAL_ADC_INT_DCMP)) { +#endif + k_sem_give(&data->dma_done_sem); + } + } + /* Clear the ADC interrupt.*/ am_hal_adc_interrupt_clear(data->adcHandle, ui32IntMask); } @@ -172,6 +245,11 @@ static int adc_ambiq_start_read(const struct device *dev, const struct adc_seque return -ENOTSUP; } + error = adc_ambiq_config(dev); + if (error < 0) { + return error; + } + channels = sequence->channels; for (slot_index = 0; slot_index < active_channels; slot_index++) { channel_id = find_lsb_set(channels) - 1; @@ -183,11 +261,79 @@ static int adc_ambiq_start_read(const struct device *dev, const struct adc_seque } __ASSERT_NO_MSG(channels == 0); + if (data->dma_mode) { + am_hal_adc_dma_config_t ADCDmaConfig = data->dma_cfg; + + if (data->dma_cfg.ui32SampleCount < active_channels) { + LOG_ERR("Not enough DMA buffer.\n"); + return -EOVERFLOW; + } + ADCDmaConfig.ui32SampleCount = active_channels; +#if defined(CONFIG_SOC_SERIES_APOLLO3X) + /* Start a timer to trigger the ADC periodically. */ + am_hal_ctimer_config_single(3, AM_HAL_CTIMER_TIMERA, + AM_HAL_CTIMER_HFRC_3MHZ | AM_HAL_CTIMER_FN_REPEAT); + am_hal_ctimer_int_enable(AM_HAL_CTIMER_INT_TIMERA3); + am_hal_ctimer_period_set(3, AM_HAL_CTIMER_TIMERA, 10, 5); + /* Enable the timer A3 to trigger the ADC directly */ + am_hal_ctimer_adc_trigger_enable(); +#else + am_hal_adc_irtt_config_t ADCIrttConfig; + + /* Set up internal repeat trigger timer */ + ADCIrttConfig.bIrttEnable = true; + ADCIrttConfig.eClkDiv = AM_HAL_ADC_RPTT_CLK_DIV16; /* 24MHz / 16 = 1.5MHz */ + ADCIrttConfig.ui32IrttCountMax = 750; /* 1.5MHz / 750 = 2kHz */ + am_hal_adc_configure_irtt(data->adcHandle, &ADCIrttConfig); +#endif + /* Configure DMA.*/ + if (AM_HAL_STATUS_SUCCESS != + am_hal_adc_configure_dma(data->adcHandle, &ADCDmaConfig)) { + LOG_ERR("Error - configuring DMA failed.\n"); + return -EINVAL; + } + + am_hal_adc_interrupt_clear(data->adcHandle, AMBIQ_ADC_DMA_INT); + am_hal_adc_interrupt_enable(data->adcHandle, AMBIQ_ADC_DMA_INT); + } else { + am_hal_adc_interrupt_enable(data->adcHandle, AM_HAL_ADC_INT_CNVCMP); + } + data->active_channels = active_channels; data->buffer = sequence->buffer; /* Start ADC conversion */ adc_context_start_read(&data->ctx, sequence); - error = adc_context_wait_for_completion(&data->ctx); + + if (data->dma_mode) { + if (k_sem_take(&data->dma_done_sem, K_MSEC(ADC_TRANSFER_TIMEOUT_MSEC))) { + LOG_ERR("Timeout waiting for transfer complete"); + /* cancel timed out transaction */ + adc_ambiq_disable(dev); + /* clean up for next xfer */ + k_sem_reset(&data->dma_done_sem); + return -ETIMEDOUT; + } +#if CONFIG_ADC_AMBIQ_HANDLE_CACHE + if (!buf_in_nocache((uintptr_t)data->dma_cfg.ui32TargetAddress, + data->active_channels * sizeof(uint32_t))) { + /* Invalidate Dcache after DMA read */ + sys_cache_data_invd_range((void *)data->dma_cfg.ui32TargetAddress, + data->active_channels * sizeof(uint32_t)); + } +#endif /* CONFIG_ADC_AMBIQ_HANDLE_CACHE */ + /* Read the value from the FIFO. */ + am_hal_adc_samples_read(data->adcHandle, false, + (uint32_t *)data->dma_cfg.ui32TargetAddress, + (uint32_t *)&data->active_channels, data->sample_buf); + for (uint32_t i = 0; i < data->active_channels; i++) { + *data->buffer++ = data->sample_buf[i].ui32Sample; + } + adc_ambiq_disable(dev); + adc_context_on_sampling_done(&data->ctx, dev); + } else { + error = adc_context_wait_for_completion(&data->ctx); + } + pm_device_runtime_put(dev); return error; } @@ -197,23 +343,18 @@ static int adc_ambiq_read(const struct device *dev, const struct adc_sequence *s struct adc_ambiq_data *data = dev->data; int error = 0; + adc_context_lock(&data->ctx, false, NULL); + error = pm_device_runtime_get(dev); if (error < 0) { - LOG_ERR("pm_device_runtime_get failed: %d", error); + LOG_ERR("Failed to get device runtime PM state"); + adc_context_release(&data->ctx, error); + return error; } - adc_context_lock(&data->ctx, false, NULL); error = adc_ambiq_start_read(dev, sequence); - adc_context_release(&data->ctx, error); - - int ret = error; - error = pm_device_runtime_put(dev); - if (error < 0) { - LOG_ERR("pm_device_runtime_put failed: %d", error); - } - - error = ret; + adc_context_release(&data->ctx, error); return error; } @@ -266,6 +407,15 @@ static void adc_context_start_sampling(struct adc_context *ctx) data->repeat_buffer = data->buffer; /* Enable the ADC. */ am_hal_adc_enable(data->adcHandle); + if (data->dma_mode) { +#if defined(CONFIG_SOC_SERIES_APOLLO3X) + /* Start the ADC repetitive sample timer A3 */ + am_hal_ctimer_start(3, AM_HAL_CTIMER_TIMERA); +#else + /* Enable internal repeat trigger timer */ + am_hal_adc_irtt_enable(data->adcHandle); +#endif + } /*Trigger the ADC*/ am_hal_adc_sw_trigger(data->adcHandle); } @@ -274,13 +424,11 @@ static int adc_ambiq_init(const struct device *dev) { struct adc_ambiq_data *data = dev->data; const struct adc_ambiq_config *cfg = dev->config; - am_hal_adc_config_t ADCConfig; int ret; /* Initialize the ADC and get the handle*/ - if (AM_HAL_STATUS_SUCCESS != - am_hal_adc_initialize(0, &data->adcHandle)) { + if (AM_HAL_STATUS_SUCCESS != am_hal_adc_initialize(0, &data->adcHandle)) { ret = -ENODEV; LOG_ERR("Failed to initialize ADC, code:%d", ret); return ret; @@ -289,27 +437,6 @@ static int adc_ambiq_init(const struct device *dev) /* power on ADC*/ ret = am_hal_adc_power_control(data->adcHandle, AM_HAL_SYSCTRL_WAKE, false); - /* Set up the ADC configuration parameters. These settings are reasonable - * for accurate measurements at a low sample rate. - */ -#if defined(CONFIG_SOC_SERIES_APOLLO3X) - ADCConfig.eClock = AM_HAL_ADC_CLKSEL_HFRC; - ADCConfig.eReference = AM_HAL_ADC_REFSEL_INT_1P5; -#else - ADCConfig.eClock = AM_HAL_ADC_CLKSEL_HFRC_24MHZ; - ADCConfig.eRepeatTrigger = AM_HAL_ADC_RPTTRIGSEL_TMR, -#endif - ADCConfig.ePolarity = AM_HAL_ADC_TRIGPOL_RISING; - ADCConfig.eTrigger = AM_HAL_ADC_TRIGSEL_SOFTWARE; - ADCConfig.eClockMode = AM_HAL_ADC_CLKMODE_LOW_POWER; - ADCConfig.ePowerMode = AM_HAL_ADC_LPMODE0; - ADCConfig.eRepeat = AM_HAL_ADC_SINGLE_SCAN; - if (AM_HAL_STATUS_SUCCESS != am_hal_adc_configure(data->adcHandle, &ADCConfig)) { - ret = -ENODEV; - LOG_ERR("Configuring ADC failed, code:%d", ret); - return ret; - } - ret = pinctrl_apply_state(cfg->pin_cfg, PINCTRL_STATE_DEFAULT); if (ret < 0) { return ret; @@ -317,8 +444,6 @@ static int adc_ambiq_init(const struct device *dev) /* Enable the ADC interrupts in the ADC. */ cfg->irq_config_func(); - am_hal_adc_interrupt_enable(data->adcHandle, AM_HAL_ADC_INT_CNVCMP); - adc_context_unlock_unconditionally(&data->ctx); return 0; @@ -331,23 +456,17 @@ static int adc_ambiq_read_async(const struct device *dev, const struct adc_seque struct adc_ambiq_data *data = dev->data; int error = 0; + adc_context_lock(&data->ctx, true, async); + error = pm_device_runtime_get(dev); if (error < 0) { - LOG_ERR("pm_device_runtime_get failed: %d", error); + adc_context_release(&data->ctx, error); + return error; } - adc_context_lock(&data->ctx, true, async); error = adc_ambiq_start_read(dev, sequence); - adc_context_release(&data->ctx, error); - - int ret = error; - - error = pm_device_runtime_put(dev); - if (error < 0) { - LOG_ERR("pm_device_runtime_put failed: %d", error); - } - error = ret; + adc_context_release(&data->ctx, error); return error; } @@ -398,6 +517,22 @@ static int adc_ambiq_pm_action(const struct device *dev, enum pm_device_action a }; #endif +#define ADC_DMA_CFG(n, buf, size) \ + { \ + .bDynamicPriority = true, \ + .ePriority = AM_HAL_ADC_PRIOR_SERVICE_IMMED, \ + .bDMAEnable = true, \ + .ui32SampleCount = size, \ + .ui32TargetAddress = (uint32_t)buf, \ + } + +#if CONFIG_ADC_AMBIQ_HANDLE_CACHE +#define __ADC_NOCACHE(n) \ + __attribute__((section(DT_INST_PROP_OR(n, dma_buffer_location, ".nocache")))) +#else +#define __ADC_NOCACHE(n) +#endif /* CONFIG_ADC_AMBIQ_HANDLE_CACHE */ + #define ADC_AMBIQ_INIT(n) \ PINCTRL_DT_INST_DEFINE(n); \ ADC_AMBIQ_DRIVER_API(n); \ @@ -407,15 +542,32 @@ static int adc_ambiq_pm_action(const struct device *dev, enum pm_device_action a DEVICE_DT_INST_GET(n), 0); \ irq_enable(DT_INST_IRQN(n)); \ }; \ + IF_ENABLED(DT_INST_PROP(n, dma_mode), \ + (static uint32_t adc_ambiq_dma_buf##n[DT_INST_PROP_OR(n, dma_buffer_size, 128)] \ + __ADC_NOCACHE(n);) \ + ) \ + IF_ENABLED(DT_INST_PROP(n, dma_mode), \ + (static am_hal_adc_sample_t adc_sample_buf##n[DT_INST_PROP_OR(n, dma_buffer_size, 128)];)) \ static struct adc_ambiq_data adc_ambiq_data_##n = { \ ADC_CONTEXT_INIT_TIMER(adc_ambiq_data_##n, ctx), \ ADC_CONTEXT_INIT_LOCK(adc_ambiq_data_##n, ctx), \ ADC_CONTEXT_INIT_SYNC(adc_ambiq_data_##n, ctx), \ + .dma_cfg = ADC_DMA_CFG( \ + n, COND_CODE_1(DT_INST_PROP(n, dma_mode), (adc_ambiq_dma_buf##n), \ + (NULL)), \ + COND_CODE_1(DT_INST_PROP(n, dma_mode), \ + (DT_INST_PROP_OR(n, dma_buffer_size, 128)), (0))), \ + .dma_mode = DT_INST_PROP(n, dma_mode), \ + .dma_done_sem = Z_SEM_INITIALIZER( \ + adc_ambiq_data_##n.dma_done_sem, 0, 1), \ + .sample_buf = COND_CODE_1( \ + DT_INST_PROP(n, dma_mode), \ + (adc_sample_buf##n), (NULL)), \ }; \ const static struct adc_ambiq_config adc_ambiq_config_##n = { \ .base = DT_INST_REG_ADDR(n), \ .size = DT_INST_REG_SIZE(n), \ - .num_channels = DT_PROP(DT_DRV_INST(n), channel_count), \ + .num_channels = DT_INST_PROP(n, channel_count), \ .irq_config_func = adc_irq_config_func_##n, \ .pin_cfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \ }; \ diff --git a/dts/arm/ambiq/ambiq_apollo3_blue.dtsi b/dts/arm/ambiq/ambiq_apollo3_blue.dtsi index fa53a63b654..ba88b498333 100644 --- a/dts/arm/ambiq/ambiq_apollo3_blue.dtsi +++ b/dts/arm/ambiq/ambiq_apollo3_blue.dtsi @@ -124,15 +124,6 @@ status = "disabled"; }; - counter3: counter@40008060 { - compatible = "ambiq,counter"; - reg = <0x40008060 0x20>; - interrupts = <14 0>; - clock-frequency = ; - clk-source = <2>; - status = "disabled"; - }; - counter4: counter@40008080 { compatible = "ambiq,counter"; reg = <0x40008080 0x20>; diff --git a/dts/arm/ambiq/ambiq_apollo3p_blue.dtsi b/dts/arm/ambiq/ambiq_apollo3p_blue.dtsi index a5d0f62f668..5d01e8171e5 100644 --- a/dts/arm/ambiq/ambiq_apollo3p_blue.dtsi +++ b/dts/arm/ambiq/ambiq_apollo3p_blue.dtsi @@ -142,15 +142,6 @@ status = "disabled"; }; - counter3: counter@40008060 { - compatible = "ambiq,counter"; - reg = <0x40008060 0x20>; - interrupts = <14 0>; - clock-frequency = ; - clk-source = <2>; - status = "disabled"; - }; - counter4: counter@40008080 { compatible = "ambiq,counter"; reg = <0x40008080 0x20>; diff --git a/dts/bindings/adc/ambiq,adc.yaml b/dts/bindings/adc/ambiq,adc.yaml index 73f138178e5..8ac8002a1dc 100644 --- a/dts/bindings/adc/ambiq,adc.yaml +++ b/dts/bindings/adc/ambiq,adc.yaml @@ -23,5 +23,19 @@ properties: required: true description: Indicates the reference voltage of the ADC in mV. + dma-mode: + description: Enables DMA over ADC. + type: boolean + + dma-buffer-location: + type: string + description: | + Define the DMA buffer location section + + dma-buffer-size: + type: int + description: | + Define the DMA buffer size in (4-byte) words + io-channel-cells: - input diff --git a/samples/drivers/adc/adc_dt/boards/apollo3_evb.overlay b/samples/drivers/adc/adc_dt/boards/apollo3_evb.overlay index 2b8732f1782..c24c9cf56cd 100644 --- a/samples/drivers/adc/adc_dt/boards/apollo3_evb.overlay +++ b/samples/drivers/adc/adc_dt/boards/apollo3_evb.overlay @@ -11,6 +11,7 @@ &adc0 { status = "okay"; + dma-mode; #address-cells = <1>; #size-cells = <0>; diff --git a/samples/drivers/adc/adc_dt/boards/apollo510_evb.overlay b/samples/drivers/adc/adc_dt/boards/apollo510_evb.overlay index d77bb43e078..9bc9997ba52 100644 --- a/samples/drivers/adc/adc_dt/boards/apollo510_evb.overlay +++ b/samples/drivers/adc/adc_dt/boards/apollo510_evb.overlay @@ -5,7 +5,7 @@ */ / { zephyr,user { - io-channels = <&adc0 4>, <&adc0 7>; + io-channels = <&adc0 5>, <&adc0 6>; }; }; @@ -13,19 +13,22 @@ status = "okay"; interrupt-parent = <&nvic>; interrupts = <19 0>; + dma-mode; + dma-buffer-location = "SRAM_NO_CACHE"; + dma-buffer-size = <128>; #address-cells = <1>; #size-cells = <0>; - channel@4 { - reg = <4>; + channel@5 { + reg = <5>; zephyr,gain = "ADC_GAIN_1"; zephyr,reference = "ADC_REF_INTERNAL"; zephyr,acquisition-time = ; zephyr,resolution = <12>; }; - channel@7 { - reg = <7>; + channel@6 { + reg = <6>; zephyr,gain = "ADC_GAIN_1"; zephyr,reference = "ADC_REF_INTERNAL"; zephyr,acquisition-time = ;