boards: arc: nsim: Convert to v2

Converts the board to hwmv2

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>

boards/boards_legacy/arc/nsim/Kconfig.board

@@ -1,13 +0,0 @@
-# DesignWare ARC nSIM simulated platform configuration
-
-# Copyright (c) 2016, 2019 Synopsys, Inc. All rights reserved.
-# SPDX-License-Identifier: Apache-2.0
-
-config BOARD_NSIM
-	bool "ARC nSIM simulator"
-	depends on SOC_NSIM
-	select HAS_COVERAGE_SUPPORT
-	help
-	  The DesignWare ARC nSIM board is a virtual board based on
-	  the ARC nSIM simulator. It demonstrates the ARC core features
-	  and a console based on the ns16550 UART model.

boards/boards_legacy/arc/nsim/Kconfig.defconfig

@@ -1,8 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-if BOARD_NSIM
-
-config BOARD
-	default "nsim"
-
-endif # BOARD_NSIM

boards/boards_legacy/arc/nsim/nsim_hs5x_smp_12cores_defconfig

@@ -1,17 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-CONFIG_ISA_ARCV3=y
-CONFIG_SOC_NSIM=y
-CONFIG_SOC_NSIM_HS5X_SMP=y
-CONFIG_BOARD_NSIM=y
-CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
-CONFIG_XIP=n
-CONFIG_BUILD_OUTPUT_BIN=n
-CONFIG_ARCV2_INTERRUPT_UNIT=y
-CONFIG_ARCV2_TIMER=y
-CONFIG_CONSOLE=y
-CONFIG_UART_CONSOLE=y
-CONFIG_SERIAL=y
-CONFIG_SMP=y
-CONFIG_MP_MAX_NUM_CPUS=12
-CONFIG_TICKET_SPINLOCKS=y

boards/boards_legacy/arc/nsim/nsim_hs5x_smp_defconfig

@@ -1,17 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-CONFIG_ISA_ARCV3=y
-CONFIG_SOC_NSIM=y
-CONFIG_SOC_NSIM_HS5X_SMP=y
-CONFIG_BOARD_NSIM=y
-CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
-CONFIG_XIP=n
-CONFIG_BUILD_OUTPUT_BIN=n
-CONFIG_ARCV2_INTERRUPT_UNIT=y
-CONFIG_ARCV2_TIMER=y
-CONFIG_CONSOLE=y
-CONFIG_UART_CONSOLE=y
-CONFIG_SERIAL=y
-CONFIG_SMP=y
-CONFIG_MP_MAX_NUM_CPUS=2
-CONFIG_TICKET_SPINLOCKS=y

boards/boards_legacy/arc/nsim/nsim_hs6x_smp_12cores_defconfig

@@ -1,17 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-CONFIG_ISA_ARCV3=y
-CONFIG_SOC_NSIM=y
-CONFIG_SOC_NSIM_HS6X_SMP=y
-CONFIG_BOARD_NSIM=y
-CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
-CONFIG_XIP=n
-CONFIG_BUILD_OUTPUT_BIN=n
-CONFIG_ARCV2_INTERRUPT_UNIT=y
-CONFIG_ARCV2_TIMER=y
-CONFIG_CONSOLE=y
-CONFIG_UART_CONSOLE=y
-CONFIG_SERIAL=y
-CONFIG_SMP=y
-CONFIG_MP_MAX_NUM_CPUS=12
-CONFIG_TICKET_SPINLOCKS=y

boards/boards_legacy/arc/nsim/nsim_hs6x_smp_defconfig

@@ -1,17 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-CONFIG_ISA_ARCV3=y
-CONFIG_SOC_NSIM=y
-CONFIG_SOC_NSIM_HS6X_SMP=y
-CONFIG_BOARD_NSIM=y
-CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
-CONFIG_XIP=n
-CONFIG_BUILD_OUTPUT_BIN=n
-CONFIG_ARCV2_INTERRUPT_UNIT=y
-CONFIG_ARCV2_TIMER=y
-CONFIG_CONSOLE=y
-CONFIG_UART_CONSOLE=y
-CONFIG_SERIAL=y
-CONFIG_SMP=y
-CONFIG_MP_MAX_NUM_CPUS=2
-CONFIG_TICKET_SPINLOCKS=y

boards/boards_legacy/arc/nsim/nsim_hs_defconfig

@@ -1,14 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-CONFIG_SOC_NSIM=y
-CONFIG_SOC_NSIM_HS=y
-CONFIG_BOARD_NSIM=y
-CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
-CONFIG_XIP=n
-CONFIG_BUILD_OUTPUT_BIN=n
-CONFIG_ARCV2_INTERRUPT_UNIT=y
-CONFIG_ARCV2_TIMER=y
-CONFIG_CONSOLE=y
-CONFIG_UART_CONSOLE=y
-CONFIG_SERIAL=y
-CONFIG_ARC_MPU_ENABLE=y

boards/boards_legacy/arc/nsim/nsim_hs_flash_xip_defconfig

@@ -1,15 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-CONFIG_SOC_NSIM=y
-CONFIG_SOC_NSIM_HS=y
-CONFIG_BOARD_NSIM=y
-CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
-CONFIG_XIP=y
-CONFIG_BUILD_OUTPUT_BIN=n
-CONFIG_ARCV2_INTERRUPT_UNIT=y
-CONFIG_ARCV2_TIMER=y
-CONFIG_CONSOLE=y
-CONFIG_UART_CONSOLE=y
-CONFIG_SERIAL=y
-CONFIG_HARVARD=n
-CONFIG_ARC_MPU_ENABLE=y

boards/boards_legacy/arc/nsim/nsim_hs_mpuv6_defconfig

@@ -1,14 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-CONFIG_SOC_NSIM=y
-CONFIG_SOC_NSIM_HS_MPUV6=y
-CONFIG_BOARD_NSIM=y
-CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
-CONFIG_XIP=n
-CONFIG_BUILD_OUTPUT_BIN=n
-CONFIG_ARCV2_INTERRUPT_UNIT=y
-CONFIG_ARCV2_TIMER=y
-CONFIG_ARC_MPU_ENABLE=y
-CONFIG_CONSOLE=y
-CONFIG_UART_CONSOLE=y
-CONFIG_SERIAL=y

boards/boards_legacy/arc/nsim/nsim_hs_smp_defconfig

@@ -1,16 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-CONFIG_SOC_NSIM=y
-CONFIG_SOC_NSIM_HS_SMP=y
-CONFIG_BOARD_NSIM=y
-CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
-CONFIG_XIP=n
-CONFIG_BUILD_OUTPUT_BIN=n
-CONFIG_ARCV2_INTERRUPT_UNIT=y
-CONFIG_ARCV2_TIMER=y
-CONFIG_CONSOLE=y
-CONFIG_UART_CONSOLE=y
-CONFIG_SERIAL=y
-CONFIG_SMP=y
-CONFIG_MP_MAX_NUM_CPUS=2
-CONFIG_TICKET_SPINLOCKS=y

boards/boards_legacy/arc/nsim/nsim_hs_sram_defconfig

@@ -1,15 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-CONFIG_SOC_NSIM=y
-CONFIG_SOC_NSIM_HS=y
-CONFIG_BOARD_NSIM=y
-CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
-CONFIG_XIP=n
-CONFIG_BUILD_OUTPUT_BIN=n
-CONFIG_ARCV2_INTERRUPT_UNIT=y
-CONFIG_ARCV2_TIMER=y
-CONFIG_CONSOLE=y
-CONFIG_UART_CONSOLE=y
-CONFIG_SERIAL=y
-CONFIG_HARVARD=n
-CONFIG_ARC_MPU_ENABLE=y

boards/boards_legacy/arc/nsim/nsim_sem_mpu_stack_guard_defconfig

@@ -1,16 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-CONFIG_SOC_NSIM=y
-CONFIG_SOC_NSIM_SEM=y
-CONFIG_BOARD_NSIM=y
-CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
-CONFIG_XIP=n
-CONFIG_BUILD_OUTPUT_BIN=n
-CONFIG_ARCV2_INTERRUPT_UNIT=y
-CONFIG_ARCV2_TIMER=y
-CONFIG_ARC_HAS_STACK_CHECKING=n
-CONFIG_ARC_MPU_ENABLE=y
-CONFIG_CONSOLE=y
-CONFIG_UART_CONSOLE=y
-CONFIG_SERIAL=y
-CONFIG_TRUSTED_EXECUTION_SECURE=y

boards/synopsys/nsim/Kconfig

@@ -0,0 +1,7 @@
+# DesignWare ARC nSIM simulated platform configuration
+
+# Copyright (c) 2016, 2019 Synopsys, Inc. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_NSIM
+	select HAS_COVERAGE_SUPPORT

boards/synopsys/nsim/Kconfig.nsim

@@ -0,0 +1,28 @@
+# DesignWare ARC nSIM simulated platform configuration
+
+# Copyright (c) 2016, 2019 Synopsys, Inc. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_NSIM
+	select SOC_NSIM_EM if BOARD_NSIM_NSIM_EM
+	select SOC_NSIM_EM7D_V22 if BOARD_NSIM_NSIM_EM7D_V22
+	select SOC_NSIM_EM11D if BOARD_NSIM_NSIM_EM11D
+	select SOC_NSIM_HS if BOARD_NSIM_NSIM_HS
+	select SOC_NSIM_HS if BOARD_NSIM_NSIM_HS_SRAM
+	select SOC_NSIM_HS_SMP if BOARD_NSIM_NSIM_HS_SMP
+	select SOC_NSIM_HS if BOARD_NSIM_NSIM_HS_FLASH_XIP
+	select SOC_NSIM_HS_MPUV6 if BOARD_NSIM_NSIM_HS_MPUV6
+	select SOC_NSIM_HS if BOARD_NSIM_NSIM_HS_HOSTLINK
+	select SOC_NSIM_HS5X if BOARD_NSIM_NSIM_HS5X
+	select SOC_NSIM_HS5X_SMP if BOARD_NSIM_NSIM_HS5X_SMP
+	select SOC_NSIM_HS5X_SMP if BOARD_NSIM_NSIM_HS5X_SMP_12CORES
+	select SOC_NSIM_HS6X if BOARD_NSIM_NSIM_HS6X
+	select SOC_NSIM_HS6X_SMP if BOARD_NSIM_NSIM_HS6X_SMP
+	select SOC_NSIM_HS6X_SMP if BOARD_NSIM_NSIM_HS6X_SMP_12CORES
+	select SOC_NSIM_SEM if BOARD_NSIM_NSIM_SEM
+	select SOC_NSIM_SEM if BOARD_NSIM_NSIM_SEM_MPU_STACK_GUARD
+	select SOC_NSIM_VPX5 if BOARD_NSIM_NSIM_VPX5
+	help
+	  The DesignWare ARC nSIM board is a virtual board based on
+	  the ARC nSIM simulator. It demonstrates the ARC core features
+	  and a console based on the ns16550 UART model.

boards/synopsys/nsim/board.yml

@@ -0,0 +1,28 @@
+board:
+  name: nsim
+  vendor: Synopsys
+  socs:
+  - name: nsim_em
+  - name: nsim_em7d_v22
+  - name: nsim_em11d
+  - name: nsim_hs
+    variants:
+    - name: sram
+    - name: smp
+    - name: flash_xip
+    - name: mpuv6
+    - name: hostlink
+  - name: nsim_hs5x
+    variants:
+    - name: smp
+      variants:
+      - name: 12cores
+  - name: nsim_hs6x
+    variants:
+    - name: smp
+      variants:
+      - name: 12cores
+  - name: nsim_sem
+    variants:
+    - name: mpu_stack_guard
+  - name: nsim_vpx5

boards/synopsys/nsim/doc/index.rst

@@ -22,24 +22,24 @@ are currently supported in the Zephyr RTOS for ARC, again please refer to
 There are multiple supported sub-configurations for that platform. Some but not all of currently
 available configurations are listed below:
 
-* ``nsim_em`` - ARC EM core v4.0 with two register banks, FastIRQ's, MPUv2, DSP options and
+* ``nsim/nsim_em`` - ARC EM core v4.0 with two register banks, FastIRQ's, MPUv2, DSP options and
   XY-memory
-* ``nsim_em_em7d_v22`` - ARC EM core v3.0 with one register bank and FastIRQ's
+* ``nsim/nsim_em7d_v22`` - ARC EM core v3.0 with one register bank and FastIRQ's
-* ``nsim_em_em11d`` - ARC EM core v4.0 with one register bank, no FastIRQ's, MPUv2, DSP options and
+* ``nsim/nsim_em11d`` - ARC EM core v4.0 with one register bank, no FastIRQ's, MPUv2, DSP options and
   XY-memory
-* ``nsim_sem`` - ARC EM core v4.0 with secure features (thus "SEM", i.e. Secure EM) and MPUv4
+* ``nsim/nsim_sem`` - ARC EM core v4.0 with secure features (thus "SEM", i.e. Secure EM) and MPUv4
-* ``nsim_hs`` - ARCv2 HS core v2.1 with two register banks, FastIRQ's and MPUv3
+* ``nsim/nsim_hs`` - ARCv2 HS core v2.1 with two register banks, FastIRQ's and MPUv3
-* ``nsim_hs_smp`` - Dual-core ARCv2 HS core v2.1 with two register banks, FastIRQ's and MPUv3
+* ``nsim/nsim_hs/smp`` - Dual-core ARCv2 HS core v2.1 with two register banks, FastIRQ's and MPUv3
-* ``nsim_vpx5`` - ARCv2 VPX5 core, close to vpx5_integer_full template
+* ``nsim/nsim_vpx5`` - ARCv2 VPX5 core, close to vpx5_integer_full template
-* ``nsim_hs5x`` - 32-bit ARCv3 HS core with rich set of options
+* ``nsim/nsim_hs5x`` - 32-bit ARCv3 HS core with rich set of options
-* ``nsim_hs6x`` - 64-bit ARCv3 HS core with rich set of options
+* ``nsim/nsim_hs6x`` - 64-bit ARCv3 HS core with rich set of options
-* ``nsim_hs5x_smp_12cores`` - SMP 12 cores 32-bit ARCv3 HS platform
+* ``nsim/nsim_hs5x/smp/12cores`` - SMP 12 cores 32-bit ARCv3 HS platform
-* ``nsim_hs6x_smp_12cores`` - SMP 12 cores 64-bit ARCv3 HS platform
+* ``nsim/nsim_hs6x/smp/12cores`` - SMP 12 cores 64-bit ARCv3 HS platform
 
 .. _board_arc_nsim_prop_args_files:
 
 It is recommended to look at precise description of a particular sub-configuration in either
-``.props`` or ``.args`` files in :zephyr_file:`boards/arc/nsim/support/` directory to understand
+``.props`` or ``.args`` files in :zephyr_file:`boards/synopsys/nsim/support/` directory to understand
 which options are configured and so will be used on invocation of the simulator.
 
 In case of single-core configurations it would be ``.props`` file which contains configuration
@@ -54,15 +54,15 @@ simulation anyway).
    defined in ``.props`` and ``.args`` are semantically identical (unfortunately options of
    nSIM & MDB don't exactly match, so care should be taken).
 
-I.e. for the single-core ``nsim_hs5x`` platform there are
+I.e. for the single-core ``nsim/nsim_hs5x`` platform there are
-:zephyr_file:`boards/arc/nsim/support/nsim_hs5x.props` and
+:zephyr_file:`boards/synopsys/nsim/support/nsim_hs5x.props` and
-:zephyr_file:`boards/arc/nsim/support/mdb_hs5x.args`.
+:zephyr_file:`boards/synopsys/nsim/support/mdb_hs5x.args`.
 
 For the multi-core configurations there is only ``.args`` file as the multi-core configuration
 can only be instantiated with help of MDB.
 
-I.e. for the multi-core ``nsim_hs5x_smp`` platform there is only
+I.e. for the multi-core ``nsim/nsim_hs5x/smp`` platform there is only
-:zephyr_file:`boards/arc/nsim/support/mdb_hs5x_smp.args`.
+:zephyr_file:`boards/synopsys/nsim/support/mdb_hs5x_smp.args`.
 
 .. warning::
    All nSIM/MDB configurations are used for demo and testing purposes. They are not meant to
@@ -90,7 +90,7 @@ Most board sub-configurations support building with both GNU and ARC MWDT toolch
 there might be exceptions from that, especially for newly added targets. You can check supported
 toolchains for the sub-configurations in the corresponding ``.yaml`` file.
 
-I.e. for the ``nsim_hs5x`` board we can check :zephyr_file:`boards/arc/nsim/nsim_hs5x.yaml`
+I.e. for the ``nsim/nsim_hs5x`` board we can check :zephyr_file:`boards/synopsys/nsim/nsim_hs5x.yaml`
 
 The supported toolchains are listed in ``toolchain:`` array in ``.yaml`` file, where we can find:
 
@@ -189,15 +189,15 @@ platform:
 
       west -v debug --runner mdb-nsim
 
-   it will produce the following output (the ``nsim_hs5x_smp`` configuration was used for that
+   it will produce the following output (the ``nsim/nsim_hs5x/smp`` configuration was used for that
    example):
 
    .. code-block:: console
 
        < *snip* >
       -- west debug: using runner mdb-nsim
-      runners.mdb-nsim: mdb -pset=1 -psetname=core0 -nooptions -nogoifmain -toggle=include_local_symbols=1 -nsim @/path/zephyr/boards/arc/nsim/support/mdb_hs5x_smp.args /path/zephyr/build/zephyr/zephyr.elf
+      runners.mdb-nsim: mdb -pset=1 -psetname=core0 -nooptions -nogoifmain -toggle=include_local_symbols=1 -nsim @/path/zephyr/boards/synopsys/nsim/support/mdb_hs5x_smp.args /path/zephyr/build/zephyr/zephyr.elf
-      runners.mdb-nsim: mdb -pset=2 -psetname=core1 -prop=download=2 -nooptions -nogoifmain -toggle=include_local_symbols=1 -nsim @/path/zephyr/boards/arc/nsim/support/mdb_hs5x_smp.args /path/zephyr/build/zephyr/zephyr.elf
+      runners.mdb-nsim: mdb -pset=2 -psetname=core1 -prop=download=2 -nooptions -nogoifmain -toggle=include_local_symbols=1 -nsim @/path/zephyr/boards/synopsys/nsim/support/mdb_hs5x_smp.args /path/zephyr/build/zephyr/zephyr.elf
       runners.mdb-nsim: mdb -multifiles=core1,core0 -OKN
 
    From that output it's possible to extract MDB commands used for setting-up the GUI debugging
@@ -205,8 +205,8 @@ platform:
 
    .. code-block:: console
 
-      mdb -pset=1 -psetname=core0 -nooptions -nogoifmain -toggle=include_local_symbols=1 -nsim @/path/zephyr/boards/arc/nsim/support/mdb_hs5x_smp.args /path/zephyr/build/zephyr/zephyr.elf
+      mdb -pset=1 -psetname=core0 -nooptions -nogoifmain -toggle=include_local_symbols=1 -nsim @/path/zephyr/boards/synopsys/nsim/support/mdb_hs5x_smp.args /path/zephyr/build/zephyr/zephyr.elf
-      mdb -pset=2 -psetname=core1 -prop=download=2 -nooptions -nogoifmain -toggle=include_local_symbols=1 -nsim @/path/zephyr/boards/arc/nsim/support/mdb_hs5x_smp.args /path/zephyr/build/zephyr/zephyr.elf
+      mdb -pset=2 -psetname=core1 -prop=download=2 -nooptions -nogoifmain -toggle=include_local_symbols=1 -nsim @/path/zephyr/boards/synopsys/nsim/support/mdb_hs5x_smp.args /path/zephyr/build/zephyr/zephyr.elf
       mdb -multifiles=core1,core0 -OKN
 
    Then it's possible to use them directly or in some machinery if required.
@@ -316,7 +316,7 @@ GNU & MWDT toolchain compiler options
 =====================================
 
 The hardware-specific compiler options are set in corresponding SoC cmake file. For ``nsim`` board
-it is :zephyr_file:`soc/arc/snps_nsim/CMakeLists.txt`.
+it is :zephyr_file:`soc/synopsys/nsim/CMakeLists.txt`.
 
 For the GNU toolchain the basic configuration is set via ``-mcpu`` which is defined in generic code
 and based on the selected CPU model via Kconfig. It still can be forcefully set to required value

boards/synopsys/nsim/nsim_nsim_em.yaml

@@ -1,4 +1,4 @@
-identifier: nsim_em
+identifier: nsim/nsim_em
 name: EM Nsim simulator
 type: sim
 simulation: nsim

boards/synopsys/nsim/nsim_nsim_em11d.yaml

@@ -1,4 +1,4 @@
-identifier: nsim_em11d
+identifier: nsim/nsim_em11d
 name: EM11D Nsim simulator
 type: sim
 simulation: nsim

boards/synopsys/nsim/nsim_nsim_em11d_defconfig

@@ -1,10 +1,6 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_SOC_NSIM=y
-CONFIG_SOC_NSIM_EM=y
-CONFIG_BOARD_NSIM=y
 CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
-CONFIG_XIP=n
 CONFIG_BUILD_OUTPUT_BIN=n
 CONFIG_ARCV2_INTERRUPT_UNIT=y
 CONFIG_ARCV2_TIMER=y

boards/synopsys/nsim/nsim_nsim_em7d_v22.yaml

@@ -1,4 +1,4 @@
-identifier: nsim_em7d_v22
+identifier: nsim/nsim_em7d_v22
 name: EM nSIM simulator (EM7D_v22)
 type: sim
 simulation: nsim

boards/synopsys/nsim/nsim_nsim_em7d_v22_defconfig

@@ -1,10 +1,6 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_SOC_NSIM=y
-CONFIG_SOC_NSIM_EM11D=y
-CONFIG_BOARD_NSIM=y
 CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
-CONFIG_XIP=n
 CONFIG_BUILD_OUTPUT_BIN=n
 CONFIG_ARCV2_INTERRUPT_UNIT=y
 CONFIG_ARCV2_TIMER=y

boards/synopsys/nsim/nsim_nsim_em_defconfig

@@ -1,10 +1,6 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_SOC_NSIM=y
-CONFIG_SOC_NSIM_EM7D_V22=y
-CONFIG_BOARD_NSIM=y
 CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
-CONFIG_XIP=n
 CONFIG_BUILD_OUTPUT_BIN=n
 CONFIG_ARCV2_INTERRUPT_UNIT=y
 CONFIG_ARCV2_TIMER=y

boards/synopsys/nsim/nsim_nsim_hs.yaml

@@ -1,4 +1,4 @@
-identifier: nsim_hs
+identifier: nsim/nsim_hs
 name: HS nSIM simulator
 type: sim
 simulation: nsim

boards/synopsys/nsim/nsim_nsim_hs5x.yaml

@@ -1,4 +1,4 @@
-identifier: nsim_hs5x
+identifier: nsim/nsim_hs5x
 name: HS5x nSIM simulator
 type: sim
 simulation: nsim

boards/synopsys/nsim/nsim_nsim_hs5x_defconfig

@@ -1,11 +1,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 CONFIG_ISA_ARCV3=y
-CONFIG_SOC_NSIM=y
-CONFIG_SOC_NSIM_HS5X=y
-CONFIG_BOARD_NSIM=y
 CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
-CONFIG_XIP=n
 CONFIG_BUILD_OUTPUT_BIN=n
 CONFIG_ARCV2_INTERRUPT_UNIT=y
 CONFIG_ARCV2_TIMER=y

boards/synopsys/nsim/nsim_nsim_hs5x_smp.yaml

@@ -1,4 +1,4 @@
-identifier: nsim_hs5x_smp
+identifier: nsim/nsim_hs5x/smp
 name: Multi-core HS5x nSIM simulator
 type: sim
 simulation: mdb-nsim

boards/synopsys/nsim/nsim_nsim_hs5x_smp_12cores.yaml

@@ -1,4 +1,4 @@
-identifier: nsim_hs5x_smp_12cores
+identifier: nsim/nsim_hs5x/smp/12cores
 name: Multi-core HS5x nSIM simulator (12 cores)
 type: sim
 simulation: mdb-nsim

boards/synopsys/nsim/nsim_nsim_hs5x_smp_12cores_defconfig

@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_MP_MAX_NUM_CPUS=12

boards/synopsys/nsim/nsim_nsim_hs5x_smp_defconfig

@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SMP=y
+CONFIG_MP_MAX_NUM_CPUS=2
+CONFIG_TICKET_SPINLOCKS=y

boards/synopsys/nsim/nsim_nsim_hs6x.yaml

@@ -1,4 +1,4 @@
-identifier: nsim_hs6x
+identifier: nsim/nsim_hs6x
 name: HS6x nSIM simulator
 type: sim
 simulation: nsim

boards/synopsys/nsim/nsim_nsim_hs6x_defconfig

@@ -1,11 +1,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 CONFIG_ISA_ARCV3=y
-CONFIG_SOC_NSIM=y
-CONFIG_SOC_NSIM_HS6X=y
-CONFIG_BOARD_NSIM=y
 CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
-CONFIG_XIP=n
 CONFIG_BUILD_OUTPUT_BIN=n
 CONFIG_ARCV2_INTERRUPT_UNIT=y
 CONFIG_ARCV2_TIMER=y

boards/synopsys/nsim/nsim_nsim_hs6x_smp.yaml

@@ -1,4 +1,4 @@
-identifier: nsim_hs6x_smp
+identifier: nsim/nsim_hs6x/smp
 name: Multi-core HS6x nSIM simulator
 type: sim
 simulation: mdb-nsim

boards/synopsys/nsim/nsim_nsim_hs6x_smp_12cores.yaml

@@ -1,4 +1,4 @@
-identifier: nsim_hs6x_smp_12cores
+identifier: nsim/nsim_hs6x/smp/12cores
 name: Multi-core HS6x nSIM simulator (12 cores)
 type: sim
 simulation: mdb-nsim

boards/synopsys/nsim/nsim_nsim_hs6x_smp_12cores_defconfig

@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_MP_MAX_NUM_CPUS=12

boards/synopsys/nsim/nsim_nsim_hs6x_smp_defconfig

@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SMP=y
+CONFIG_MP_MAX_NUM_CPUS=2
+CONFIG_TICKET_SPINLOCKS=y

boards/synopsys/nsim/nsim_nsim_hs_defconfig

@@ -1,10 +1,6 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_SOC_NSIM=y
-CONFIG_SOC_NSIM_HS=y
-CONFIG_BOARD_NSIM=y
 CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
-CONFIG_XIP=n
 CONFIG_BUILD_OUTPUT_BIN=n
 CONFIG_ARCV2_INTERRUPT_UNIT=y
 CONFIG_ARCV2_TIMER=y

boards/synopsys/nsim/nsim_nsim_hs_flash_xip.yaml

@@ -1,4 +1,4 @@
-identifier: nsim_hs_flash_xip
+identifier: nsim/nsim_hs/flash_xip
 name: HS nSIM simulator (FLASH XIP)
 type: sim
 simulation: nsim

boards/synopsys/nsim/nsim_nsim_hs_flash_xip_defconfig

@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_XIP=y
+CONFIG_HARVARD=n

boards/synopsys/nsim/nsim_nsim_hs_hostlink.yaml

@@ -1,4 +1,4 @@
-identifier: nsim_hs3x_hostlink
+identifier: nsim/nsim_hs/hostlink
 name: HS3x nSIM simulator
 type: sim
 simulation: nsim

boards/synopsys/nsim/nsim_nsim_hs_mpuv6.yaml

@@ -1,4 +1,4 @@
-identifier: nsim_hs_mpuv6
+identifier: nsim/nsim_hs/mpuv6
 name: HS (with MPU v6) nSIM simulator
 type: sim
 simulation: nsim

boards/synopsys/nsim/nsim_nsim_hs_smp.yaml

@@ -1,4 +1,4 @@
-identifier: nsim_hs_smp
+identifier: nsim/nsim_hs/smp
 name: Multi-core HS nSIM simulator
 type: sim
 simulation: mdb-nsim

boards/synopsys/nsim/nsim_nsim_hs_smp_defconfig

@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_ARC_MPU_ENABLE=n
+CONFIG_SMP=y
+CONFIG_MP_MAX_NUM_CPUS=2
+CONFIG_TICKET_SPINLOCKS=y

boards/synopsys/nsim/nsim_nsim_hs_sram.yaml

@@ -1,4 +1,4 @@
-identifier: nsim_hs_sram
+identifier: nsim/nsim_hs/sram
 name: HS nSIM simulator (SRAM)
 type: sim
 simulation: nsim

boards/synopsys/nsim/nsim_nsim_hs_sram_defconfig

@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_HARVARD=n

boards/synopsys/nsim/nsim_nsim_sem.yaml

@@ -1,4 +1,4 @@
-identifier: nsim_sem
+identifier: nsim/nsim_sem
 name: SEM Nsim simulator
 type: sim
 arch: arc

boards/synopsys/nsim/nsim_nsim_sem_defconfig

@@ -1,10 +1,6 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_SOC_NSIM=y
-CONFIG_SOC_NSIM_SEM=y
-CONFIG_BOARD_NSIM=y
 CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
-CONFIG_XIP=n
 CONFIG_BUILD_OUTPUT_BIN=n
 CONFIG_ARCV2_INTERRUPT_UNIT=y
 CONFIG_ARCV2_TIMER=y

boards/synopsys/nsim/nsim_nsim_sem_mpu_stack_guard.yaml

@@ -1,4 +1,4 @@
-identifier: nsim_sem_mpu_stack_guard
+identifier: nsim/nsim_sem/mpu_stack_guard
 name: SEM nSIM simulator (stack guard)
 type: sim
 arch: arc

boards/synopsys/nsim/nsim_nsim_sem_mpu_stack_guard_defconfig

@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_ARC_HAS_STACK_CHECKING=n

boards/synopsys/nsim/nsim_nsim_vpx5.yaml

@@ -1,4 +1,4 @@
-identifier: nsim_vpx5
+identifier: nsim/nsim_vpx5
 name: VPX5 nSIM simulator
 type: sim
 simulation: nsim

boards/synopsys/nsim/nsim_nsim_vpx5_defconfig

@@ -1,10 +1,6 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_SOC_NSIM=y
-CONFIG_SOC_NSIM_VPX5=y
-CONFIG_BOARD_NSIM=y
 CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
-CONFIG_XIP=n
 CONFIG_BUILD_OUTPUT_BIN=n
 CONFIG_ARCV2_INTERRUPT_UNIT=y
 CONFIG_ARCV2_TIMER=y