zara
/
zephyr
mirror of https://github.com/zephyrproject-rtos/zephyr
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
Browse Source

soc: nxp: consolidate nxp port pinctrl headers 

NXP PORT IP instantiations often have different features absent, IE
input buffer, open drain, or slew rate support. Check if the relevant
PCR register bitmasks are defined in the common pin control file, and
define the bitmasks to 0x0 (no effect) if they are not. This allows us
to further consolidate the pinctrl_soc.h headers for SOCs using the PORT
IP.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
pull/79821/head
Daniel DeGrasse 8 months ago committed by Mahesh Mahadevan
parent
a36c7ddb36
commit
42cc35f941
8 changed files with 34 additions and 157 deletions
Whitespace
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
Split View
Diff Options
Show Stats Download Patch File Download Diff File
  1. 4
      drivers/pinctrl/pinctrl_nxp_port.c
  2. 51
      include/zephyr/drivers/pinctrl/pinctrl_nxp_port_common.h
  3. 2
      soc/nxp/kinetis/common/pinctrl_soc.h
  4. 2
      soc/nxp/mcx/mcxa/pinctrl_soc.h
  5. 44
      soc/nxp/mcx/mcxc/pinctrl_soc.h
  6. 41
      soc/nxp/mcx/mcxn/pinctrl_soc.h
  7. 2
      soc/nxp/mcx/mcxw/pinctrl_soc.h
  8. 45
      soc/nxp/s32/s32k1/pinctrl_soc.h

4
drivers/pinctrl/pinctrl_nxp_port.c
Unescape View File

@ -32,7 +32,7 @@ static PORT_Type *ports[] = { @@ -32,7 +32,7 @@ static PORT_Type *ports[] = {
#define PIN(mux) (((mux) & 0xFC00000) >> 22)
#define PORT(mux) (((mux) & 0xF0000000) >> 28)
#define PINCFG(mux) ((mux) & Z_PINCTRL_KINETIS_PCR_MASK)
#define PINCFG(mux) ((mux) & Z_PINCTRL_NXP_PORT_PCR_MASK)
struct pinctrl_mcux_config {
const struct device *clock_dev;
@ -47,7 +47,7 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, @@ -47,7 +47,7 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
uint8_t pin = PIN(pins[i]);
uint16_t mux = PINCFG(pins[i]);
base->PCR[pin] = (base->PCR[pin] & (~Z_PINCTRL_KINETIS_PCR_MASK)) | mux;
base->PCR[pin] = (base->PCR[pin] & (~Z_PINCTRL_NXP_PORT_PCR_MASK)) | mux;
}
return 0;
}

51
include/zephyr/drivers/pinctrl/pinctrl_soc_kinetis_common.h → include/zephyr/drivers/pinctrl/pinctrl_nxp_port_common.h
Unescape View File

@ -6,50 +6,49 @@ @@ -6,50 +6,49 @@
/*
* @file
* NXP Kinetis SOC specific helpers for pinctrl driver
* NXP PORT SOC specific helpers for pinctrl driver
*/
#ifndef ZEPHYR_SOC_ARM_NXP_KINETIS_COMMON_PINCTRL_SOC_H_
#define ZEPHYR_SOC_ARM_NXP_KINETIS_COMMON_PINCTRL_SOC_H_
#ifndef ZEPHYR_INCLUDE_DRIVERS_PINCTRL_PINCTRL_NXP_PORT_COMMON_H_
#define ZEPHYR_INCLUDE_DRIVERS_PINCTRL_PINCTRL_NXP_PORT_COMMON_H_
/** @cond INTERNAL_HIDDEN */
#include <zephyr/devicetree.h>
#include <zephyr/types.h>
/* Include SOC headers, so we get definitions for PCR bitmasks */
#include <soc.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef uint32_t pinctrl_soc_pin_t;
/* Kinetis KW/KL/KE series does not support open drain. Define macros to have no effect
* Note: KW22 and KW24 do support open drain, rest of KW series does not
/*
* Some PORT IP instantiations lack certain features, include input buffers,
* open drain, and slew rate. If masks aren't defined for these bitfields,
* define them to have no effect
*/
/* clang-format off */
#if (defined(CONFIG_SOC_SERIES_KINETIS_KWX) && \
!(defined(CONFIG_SOC_MKW24D5) || defined(CONFIG_SOC_MKW22D5))) || \
defined(CONFIG_SOC_SERIES_KINETIS_KL2X) || defined(CONFIG_SOC_SERIES_KINETIS_KE1XF) || \
defined(CONFIG_SOC_SERIES_KE1XZ)
#define PORT_PCR_ODE(x) 0x0
#define PORT_PCR_ODE_MASK 0x0
#ifndef PORT_PCR_IBE_MASK /* Input buffer enable */
#define PORT_PCR_IBE_MASK 0x0
#define PORT_PCR_IBE(x) 0x0
#endif
/* clang-format on */
/* Kinetis KE series does not support slew rate. Define macros to have no effect */
#if defined(CONFIG_SOC_SERIES_KINETIS_KE1XF) || defined(CONFIG_SOC_SERIES_KE1XZ)
#define PORT_PCR_SRE(x) 0x0
#ifndef PORT_PCR_SRE_MASK /* Slew rate */
#define PORT_PCR_SRE_MASK 0x0
#define PORT_PCR_SRE(x) 0x0
#endif
#if !(defined(CONFIG_SOC_SERIES_MCXA))
#define PORT_PCR_IBE(x) 0x0
#define PORT_PCR_IBE_MASK 0x0
#ifndef PORT_PCR_ODE_MASK /* Open drain */
#define PORT_PCR_ODE_MASK 0x0
#define PORT_PCR_ODE(x) 0x0
#endif
#define Z_PINCTRL_KINETIS_PINCFG(node_id) \
typedef uint32_t pinctrl_soc_pin_t;
#define Z_PINCTRL_NXP_PORT_PINCFG(node_id) \
(PORT_PCR_DSE(DT_ENUM_IDX(node_id, drive_strength)) | \
PORT_PCR_PS(DT_PROP(node_id, bias_pull_up)) | \
PORT_PCR_PE(DT_PROP(node_id, bias_pull_up)) | \
@ -59,12 +58,12 @@ typedef uint32_t pinctrl_soc_pin_t; @@ -59,12 +58,12 @@ typedef uint32_t pinctrl_soc_pin_t;
PORT_PCR_IBE(DT_PROP(node_id, input_enable)) | \
PORT_PCR_PFE(DT_PROP(node_id, nxp_passive_filter)))
#define Z_PINCTRL_KINETIS_PCR_MASK \
#define Z_PINCTRL_NXP_PORT_PCR_MASK \
(PORT_PCR_MUX_MASK | PORT_PCR_DSE_MASK | PORT_PCR_ODE_MASK | PORT_PCR_PFE_MASK | \
PORT_PCR_IBE_MASK | PORT_PCR_SRE_MASK | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK)
#define Z_PINCTRL_STATE_PIN_INIT(group, pin_prop, idx) \
DT_PROP_BY_IDX(group, pin_prop, idx) | Z_PINCTRL_KINETIS_PINCFG(group),
DT_PROP_BY_IDX(group, pin_prop, idx) | Z_PINCTRL_NXP_PORT_PINCFG(group),
#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), DT_FOREACH_PROP_ELEM, pinmux, \
@ -76,4 +75,4 @@ typedef uint32_t pinctrl_soc_pin_t; @@ -76,4 +75,4 @@ typedef uint32_t pinctrl_soc_pin_t;
/** @endcond */
#endif /* ZEPHYR_SOC_ARM_NXP_KINETIS_COMMON_PINCTRL_SOC_H_ */
#endif /* ZEPHYR_INCLUDE_DRIVERS_PINCTRL_PINCTRL_NXP_PORT_COMMON_H_ */

2
soc/nxp/kinetis/common/pinctrl_soc.h
Unescape View File

@ -4,4 +4,4 @@ @@ -4,4 +4,4 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/pinctrl/pinctrl_soc_kinetis_common.h>
#include <zephyr/drivers/pinctrl/pinctrl_nxp_port_common.h>

2
soc/nxp/mcx/mcxa/pinctrl_soc.h
Unescape View File

@ -4,4 +4,4 @@ @@ -4,4 +4,4 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/pinctrl/pinctrl_soc_kinetis_common.h>
#include <zephyr/drivers/pinctrl/pinctrl_nxp_port_common.h>

44
soc/nxp/mcx/mcxc/pinctrl_soc.h
Unescape View File

@ -4,46 +4,4 @@ @@ -4,46 +4,4 @@
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_SOC_ARM_NXP_MCXC_COMMON_PINCTRL_SOC_H_
#define ZEPHYR_SOC_ARM_NXP_MCXC_COMMON_PINCTRL_SOC_H_
#include <zephyr/devicetree.h>
#include <zephyr/types.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef uint32_t pinctrl_soc_pin_t;
/* MCXC series does not support open drain. Define macros to have no effect */
#define PORT_PCR_ODE(x) 0x0
#define PORT_PCR_ODE_MASK 0x0
#define Z_PINCTRL_MCXC_PINCFG(node_id) \
(PORT_PCR_DSE(DT_ENUM_IDX(node_id, drive_strength)) | \
PORT_PCR_PS(DT_PROP(node_id, bias_pull_up)) | \
PORT_PCR_PE(DT_PROP(node_id, bias_pull_up)) | \
PORT_PCR_PE(DT_PROP(node_id, bias_pull_down)) | \
PORT_PCR_ODE(DT_PROP(node_id, drive_open_drain)) | \
PORT_PCR_SRE(DT_ENUM_IDX(node_id, slew_rate)) | \
PORT_PCR_PFE(DT_PROP(node_id, nxp_passive_filter)))
#define Z_PINCTRL_KINETIS_PCR_MASK \
(PORT_PCR_MUX_MASK | PORT_PCR_DSE_MASK | PORT_PCR_ODE_MASK | \
PORT_PCR_PFE_MASK | PORT_PCR_SRE_MASK | PORT_PCR_PE_MASK | \
PORT_PCR_PS_MASK)
#define Z_PINCTRL_STATE_PIN_INIT(group, pin_prop, idx) \
DT_PROP_BY_IDX(group, pin_prop, idx) | Z_PINCTRL_MCXC_PINCFG(group),
#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), \
DT_FOREACH_PROP_ELEM, pinmux, Z_PINCTRL_STATE_PIN_INIT)};
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_SOC_ARM_NXP_MCXC_COMMON_PINCTRL_SOC_H_ */
#include <zephyr/drivers/pinctrl/pinctrl_nxp_port_common.h>

41
soc/nxp/mcx/mcxn/pinctrl_soc.h
Unescape View File

@ -4,43 +4,4 @@ @@ -4,43 +4,4 @@
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_SOC_ARM_NXP_MCX_COMMON_PINCTRL_SOC_H_
#define ZEPHYR_SOC_ARM_NXP_MCX_COMMON_PINCTRL_SOC_H_
#include <zephyr/devicetree.h>
#include <zephyr/types.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef uint32_t pinctrl_soc_pin_t;
#define Z_PINCTRL_MCX_PINCFG(node_id) \
(PORT_PCR_DSE(DT_ENUM_IDX(node_id, drive_strength)) | \
PORT_PCR_PS(DT_PROP(node_id, bias_pull_up)) | \
PORT_PCR_PE(DT_PROP(node_id, bias_pull_up)) | \
PORT_PCR_PE(DT_PROP(node_id, bias_pull_down)) | \
PORT_PCR_ODE(DT_PROP(node_id, drive_open_drain)) | \
PORT_PCR_SRE(DT_ENUM_IDX(node_id, slew_rate)) | \
PORT_PCR_IBE(DT_PROP(node_id, input_enable)) | \
PORT_PCR_PFE(DT_PROP(node_id, nxp_passive_filter)))
#define Z_PINCTRL_KINETIS_PCR_MASK \
(PORT_PCR_IBE_MASK | PORT_PCR_MUX_MASK | PORT_PCR_DSE_MASK | \
PORT_PCR_ODE_MASK | PORT_PCR_PFE_MASK | PORT_PCR_SRE_MASK | \
PORT_PCR_PE_MASK | PORT_PCR_PS_MASK)
#define Z_PINCTRL_STATE_PIN_INIT(group, pin_prop, idx) \
DT_PROP_BY_IDX(group, pin_prop, idx) | Z_PINCTRL_MCX_PINCFG(group),
#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), \
DT_FOREACH_PROP_ELEM, pinmux, Z_PINCTRL_STATE_PIN_INIT)};
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_SOC_ARM_NXP_MCX_COMMON_PINCTRL_SOC_H_ */
#include <zephyr/drivers/pinctrl/pinctrl_nxp_port_common.h>

2
soc/nxp/mcx/mcxw/pinctrl_soc.h
Unescape View File

@ -4,4 +4,4 @@ @@ -4,4 +4,4 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/pinctrl/pinctrl_soc_kinetis_common.h>
#include <zephyr/drivers/pinctrl/pinctrl_nxp_port_common.h>

45
soc/nxp/s32/s32k1/pinctrl_soc.h
Unescape View File

@ -1,48 +1,7 @@ @@ -1,48 +1,7 @@
/*
* Copyright 2023 NXP
* Copyright 2023-2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* @file
* NXP S32K1 SOC specific helpers for pinctrl driver
*/
#ifndef ZEPHYR_SOC_ARM_NXP_S32_S32K1_PINCTRL_SOC_H_
#define ZEPHYR_SOC_ARM_NXP_S32_S32K1_PINCTRL_SOC_H_
#include <zephyr/devicetree.h>
#include <zephyr/types.h>
#ifdef __cplusplus
extern "C" {
#endif
/** @cond INTERNAL_HIDDEN */
typedef uint32_t pinctrl_soc_pin_t;
#define Z_PINCTRL_KINETIS_PINCFG(node_id) \
(PORT_PCR_DSE(DT_ENUM_IDX(node_id, drive_strength)) | \
PORT_PCR_PS(DT_PROP(node_id, bias_pull_up)) | \
PORT_PCR_PE(DT_PROP(node_id, bias_pull_up)) | \
PORT_PCR_PE(DT_PROP(node_id, bias_pull_down)) | \
PORT_PCR_PFE(DT_PROP(node_id, nxp_passive_filter)))
#define Z_PINCTRL_KINETIS_PCR_MASK \
(PORT_PCR_MUX_MASK | PORT_PCR_DSE_MASK | PORT_PCR_PFE_MASK | \
PORT_PCR_PE_MASK | PORT_PCR_PS_MASK)
#define Z_PINCTRL_STATE_PIN_INIT(group, pin_prop, idx) \
DT_PROP_BY_IDX(group, pin_prop, idx) | Z_PINCTRL_KINETIS_PINCFG(group),
#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), \
DT_FOREACH_PROP_ELEM, pinmux, Z_PINCTRL_STATE_PIN_INIT)};
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_SOC_ARM_NXP_S32_S32K1_PINCTRL_SOC_H_ */
#include <zephyr/drivers/pinctrl/pinctrl_nxp_port_common.h>

Write Preview
Loading…
Cancel
Save