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Port IMXRT family to HWMV2, including series: - RT11XX - RT10XX - RT6XX Not including RT5XX Co-authored-by: Declan Snyder <declan.snyder@nxp.com> Co-authored-by: Daniel DeGrasse <daniel.degrasse@nxp.com> Co-authored-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com> Co-authored-by: David Leach <david.leach@nxp.com> Co-authored-by: Yves Vandervennet <yves.vandervennet@nxp.com> Co-authored-by: Emilio Benavente <emilio.benavente@nxp.com> Signed-off-by: Declan Snyder <declan.snyder@nxp.com>pull/69687/head
Declan Snyder
1 year ago
committed by
Carles Cufi
80 changed files with 1325 additions and 1508 deletions
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|
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# Copyright 2024 NXP |
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# SPDX-License-Identifier: Apache-2.0 |
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add_subdirectory(${SOC_SERIES}) |
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zephyr_include_directories(.) |
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zephyr_include_directories(${SOC_SERIES}) |
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zephyr_linker_sources_ifdef(CONFIG_NXP_IMXRT_BOOT_HEADER |
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ROM_START SORT_KEY 0 boot_header.ld) |
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if(CONFIG_SOC_SERIES_IMXRT10XX OR CONFIG_SOC_SERIES_IMXRT11XX) |
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if(CONFIG_DEVICE_CONFIGURATION_DATA) |
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set(boot_hdr_dcd_data_section ".boot_hdr.dcd_data") |
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endif() |
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zephyr_sources(mpu_regions.c) |
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zephyr_linker_section_configure( |
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SECTION .rom_start |
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INPUT ".boot_hdr.conf" |
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OFFSET ${CONFIG_FLEXSPI_CONFIG_BLOCK_OFFSET} |
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KEEP |
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PRIO 10 |
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) |
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zephyr_linker_section_configure( |
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SECTION .rom_start |
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INPUT ".boot_hdr.ivt" |
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".boot_hdr.data" |
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${boot_hdr_dcd_data_section} |
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OFFSET ${CONFIG_IMAGE_VECTOR_TABLE_OFFSET} |
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KEEP |
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PRIO 11 |
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) |
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zephyr_compile_definitions(XIP_EXTERNAL_FLASH) |
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endif() |
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if(CONFIG_SOC_SERIES_IMXRT6XX OR CONFIG_SOC_SERIES_IMX_RT5XX) |
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zephyr_linker_sources_ifdef(CONFIG_USB_DEVICE_DRIVER SECTIONS usb.ld) |
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endif() |
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if(CONFIG_MEMC) |
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zephyr_library_include_directories(${ZEPHYR_BASE}/drivers/memc) |
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endif() |
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# Copyright 2024 NXP |
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# SPDX-License-Identifier: Apache-2.0 |
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config SOC_FAMILY_NXP_IMXRT |
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select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE |
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select HAS_PM |
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if SOC_FAMILY_NXP_IMXRT |
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# Source series Kconfig files first, so SOCs |
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# can override the defaults given here |
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rsource "*/Kconfig" |
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# Used for default value in FLASH_MCUX_FLEXSPI_XIP |
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DT_CHOSEN_Z_FLASH := zephyr,flash |
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DT_COMPAT_FLEXSPI := nxp,imx-flexspi |
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# Macros to shorten Kconfig definitions |
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DT_CHOSEN_FLASH_NODE := $(dt_chosen_path,$(DT_CHOSEN_Z_FLASH)) |
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DT_CHOSEN_FLASH_PARENT := $(dt_node_parent,$(DT_CHOSEN_FLASH_NODE)) |
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config FLASH_MCUX_FLEXSPI_XIP |
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bool "MCUX FlexSPI flash access with xip" |
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default $(dt_node_has_compat,$(DT_CHOSEN_FLASH_PARENT),$(DT_COMPAT_FLEXSPI)) |
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select XIP |
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help |
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Allows for the soc to safely initialize the clocks for the |
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FlexSpi when planning to execute code in FlexSpi Memory. |
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# Note- When SECOND_CORE_MCUX is set, the dependencies for this Kconfig |
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# should be set elsewhere, since the determination of which SOC core |
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# requires the boot header is SOC specific. |
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config NXP_IMXRT_BOOT_HEADER |
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bool "Boot header" |
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default y |
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depends on !(BOOTLOADER_MCUBOOT || SECOND_CORE_MCUX) |
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help |
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Enable data structures required by the boot ROM to boot the |
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application from an external flash device. |
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if NXP_IMXRT_BOOT_HEADER |
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choice BOOT_DEVICE |
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prompt "Boot device" |
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default BOOT_FLEXSPI_NOR |
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config BOOT_FLEXSPI_NOR |
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bool "FlexSPI serial NOR" |
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depends on HAS_MCUX_FLEXSPI |
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config BOOT_FLEXSPI_NAND |
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bool "FlexSPI serial NAND" |
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depends on HAS_MCUX_FLEXSPI |
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config BOOT_SEMC_NOR |
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bool "SEMC parallel NOR" |
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depends on HAS_MCUX_SEMC |
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config BOOT_SEMC_NAND |
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bool "SEMC parallel NAND" |
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depends on HAS_MCUX_SEMC |
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endchoice # BOOT_DEVICE |
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config FLEXSPI_CONFIG_BLOCK_OFFSET |
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hex "FlexSPI config block offset" |
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default 0x400 if SOC_SERIES_IMX_RT5XX || SOC_SERIES_IMXRT6XX |
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default 0x0 if BOOT_FLEXSPI_NOR |
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help |
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FlexSPI configuration block consists of parameters regarding specific |
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flash devices including read command sequence, quad mode enablement |
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sequence (optional), etc. The boot ROM expects FlexSPI configuration |
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parameter to be presented in serial nor flash. |
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config IMAGE_VECTOR_TABLE_OFFSET |
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hex "Image vector table offset" |
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default 0x1000 if BOOT_FLEXSPI_NOR || BOOT_SEMC_NOR |
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default 0x400 if BOOT_FLEXSPI_NAND || BOOT_SEMC_NAND |
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help |
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The Image Vector Table (IVT) provides the boot ROM with pointers to |
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the application entry point and device configuration data. The boot |
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ROM requires a fixed IVT offset for each type of boot device. |
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config DEVICE_CONFIGURATION_DATA |
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bool "Device configuration data" |
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help |
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Device configuration data (DCD) provides a sequence of commands to |
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the boot ROM to initialize components such as an SDRAM. This is |
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useful if your application expects components like SDRAM to be |
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initialized at boot time. |
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endif # NXP_IMXRT_BOOT_HEADER |
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config NXP_IMX_EXTERNAL_SDRAM |
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bool "Allow access to external SDRAM region" |
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help |
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Enable access to external SDRAM region managed by the SEMC. This |
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setting should be enabled when the application uses SDRAM, or |
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an MPU region will be defined to disable cached access to the |
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SDRAM memory space. |
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config NXP_IMX_RT_ROM_RAMLOADER |
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depends on !FLASH_MCUX_FLEXSPI_XIP && NXP_IMXRT_BOOT_HEADER |
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# Required so that debugger will load image to correct offset |
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select BUILD_OUTPUT_HEX |
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bool "Create output image that IMX RT ROM can load from FlexSPI to ram" |
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help |
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Builds an output image that the IMX RT BootROM can load from the |
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FlexSPI boot device into RAM region. The image will be loaded |
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from FLEXSPI into the region specified by `zephyr,flash` node. |
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# Setup LMA adjustment if using the RAMLOADER feature of ROM |
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FLASH_CHOSEN := zephyr,flash |
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FLASH_BASE := $(dt_chosen_reg_addr_hex,$(FLASH_CHOSEN)) |
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FLEXSPI_BASE := $(dt_node_reg_addr_hex,/soc/spi@402a8000,1) |
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config BUILD_OUTPUT_ADJUST_LMA |
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default "$(FLEXSPI_BASE) - $(FLASH_BASE)" if NXP_IMX_RT_ROM_RAMLOADER |
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config SECOND_CORE_MCUX |
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bool "Dual core operation on the RT11xx series" |
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depends on SOC_SERIES_IMXRT11XX |
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help |
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Indicates the second core will be enabled, and the part will run |
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in dual core mode. Enables dual core operation on the RT11xx series, |
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by booting an image targeting the Cortex-M4 from the Cortex-M7 CPU. |
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The M4 image will be loaded from flash into RAM based off a |
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generated header specifying the VMA and LMA of each memory section |
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to load |
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config FLEXSPI_CONFIG_BLOCK_OFFSET |
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hex |
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default 0x400 if SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX |
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if SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX |
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config PM_MCUX_GPC |
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bool "MCUX general power controller driver" |
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config PM_MCUX_DCDC |
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bool "MCUX dcdc converter module driver" |
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config PM_MCUX_PMU |
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bool "MCUX power management unit driver" |
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config DCDC_VALUE |
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hex "DCDC value for VDD_SOC" |
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config INIT_ARM_PLL |
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bool "Initialize ARM PLL" |
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config INIT_VIDEO_PLL |
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bool "Initialize Video PLL" |
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config INIT_ENET_PLL |
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bool |
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help |
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If y, the Ethernet PLL is initialized. Always enabled on e.g. |
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MIMXRT1021 - see commit 17f4d6bec7 ("soc: nxp_imx: fix ENET_PLL selection |
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for MIMXRT1021"). |
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endif # SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX |
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endif # SOC_FAMILY_NXP_IMXRT |
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@@ -0,0 +1,10 @@
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# Copyright 2024 NXP |
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# SPDX-License-Identifier: Apache-2.0 |
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config SOC_FAMILY_NXP_IMXRT |
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bool |
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config SOC_FAMILY |
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default "nxp_imxrt" if SOC_FAMILY_NXP_IMXRT |
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rsource "*/Kconfig.soc" |
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/* |
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* Copyright 2024 NXP |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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. = CONFIG_FLEXSPI_CONFIG_BLOCK_OFFSET; |
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#if defined(CONFIG_SOC_SERIES_IMXRT11XX) || defined(CONFIG_SOC_SERIES_IMXRT10XX) |
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KEEP(*(.boot_hdr.conf)) |
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#endif |
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#if defined(CONFIG_SOC_SERIES_IMXRT6XX) || defined(CONFIG_SOC_SERIES_IMX_RT5XX) |
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KEEP(*(.flash_conf)) |
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#endif |
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. = CONFIG_IMAGE_VECTOR_TABLE_OFFSET; |
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KEEP(*(.boot_hdr.ivt)) |
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#if defined(CONFIG_SOC_SERIES_IMXRT11XX) || defined(CONFIG_SOC_SERIES_IMXRT10XX) |
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KEEP(*(.boot_hdr.data)) |
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#ifdef CONFIG_DEVICE_CONFIGURATION_DATA |
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KEEP(*(.boot_hdr.dcd_data)) |
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#endif /* CONFIG_DEVICE_CONFIGURATION_DATA */ |
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#endif /* CONFIG_SOC_SERIES_IMXRT10XX || CONFIG_SOC_SERIES_IMXRT11XX */ |
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# |
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# Copyright 2024 NXP |
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# |
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# SPDX-License-Identifier: Apache-2.0 |
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# |
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zephyr_sources(soc.c) |
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if(CONFIG_PM) |
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zephyr_sources(power.c) |
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zephyr_code_relocate(FILES power.c LOCATION ITCM_TEXT) |
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if(CONFIG_SOC_MIMXRT1064) |
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zephyr_sources(lpm_rt1064.c) |
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zephyr_code_relocate(FILES lpm_rt1064 LOCATION ITCM_TEXT) |
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endif() |
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endif() |
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if(CONFIG_MEMC_MCUX_FLEXSPI) |
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zephyr_sources(flexspi.c) |
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if(CONFIG_FLASH_MCUX_FLEXSPI_XIP) |
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zephyr_code_relocate(FILES flexspi.c LOCATION ITCM_TEXT) |
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endif() |
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endif() |
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zephyr_include_directories(.) |
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set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") |
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# Copyright 2024 NXP |
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# SPDX-License-Identifier: Apache-2.0 |
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config SOC_SERIES_IMXRT10XX |
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select CPU_CORTEX_M7 |
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select CPU_CORTEX_M_HAS_DWT |
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select CPU_HAS_ICACHE |
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select CPU_HAS_DCACHE |
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select PLATFORM_SPECIFIC_INIT |
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select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS |
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select ARM |
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select CLOCK_CONTROL |
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select HAS_MCUX |
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select HAS_MCUX_CACHE |
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select HAS_MCUX_12B1MSPS_SAR if !SOC_MIMXRT1042 |
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select HAS_MCUX_CCM if !SOC_MIMXRT1042 |
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select HAS_MCUX_FLEXSPI |
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select HAS_MCUX_IGPIO |
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select HAS_MCUX_LPI2C if !SOC_MIMXRT1042 |
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select HAS_MCUX_LPSPI if !SOC_MIMXRT1042 |
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select HAS_MCUX_LPUART if !SOC_MIMXRT1042 |
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select HAS_MCUX_GPT if !SOC_MIMXRT1042 |
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select HAS_MCUX_TRNG if !SOC_MIMXRT1042 |
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select HAS_MCUX_EDMA |
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select HAS_MCUX_GPC |
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select HAS_MCUX_IOMUXC |
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select HAS_MCUX_PMU |
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select HAS_MCUX_DCDC |
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select HAS_MCUX_USB_EHCI |
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select HAS_SWO |
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config SOC_MIMXRT1011 |
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select CPU_HAS_FPU |
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select CPU_HAS_ARM_MPU |
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select CPU_HAS_ICACHE |
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select CPU_HAS_DCACHE |
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select INIT_ENET_PLL |
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config SOC_MIMXRT1015 |
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select CPU_HAS_FPU |
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select CPU_HAS_FPU_DOUBLE_PRECISION |
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select CPU_HAS_ARM_MPU |
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select INIT_ENET_PLL |
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config SOC_MIMXRT1021 |
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select HAS_MCUX_ENET |
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select HAS_MCUX_SEMC |
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select CPU_HAS_FPU_DOUBLE_PRECISION |
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select CPU_HAS_ARM_MPU |
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select INIT_ENET_PLL |
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select HAS_MCUX_USDHC1 |
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select HAS_MCUX_USDHC2 |
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select HAS_MCUX_FLEXCAN |
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select HAS_MCUX_PWM |
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config SOC_MIMXRT1024 |
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select HAS_MCUX_ENET |
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select HAS_MCUX_SEMC |
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select CPU_HAS_FPU_DOUBLE_PRECISION |
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select CPU_HAS_ARM_MPU |
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select INIT_ENET_PLL |
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select HAS_MCUX_USDHC1 |
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select HAS_MCUX_USDHC2 |
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select HAS_MCUX_FLEXCAN |
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select HAS_MCUX_SRC |
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config SOC_MIMXRT1042 |
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select HAS_MCUX_SEMC |
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select CPU_HAS_FPU_DOUBLE_PRECISION |
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select CPU_HAS_ARM_MPU |
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select INIT_ARM_PLL |
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config SOC_MIMXRT1051 |
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select HAS_MCUX_ENET |
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select HAS_MCUX_SEMC |
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select CPU_HAS_FPU_DOUBLE_PRECISION |
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select CPU_HAS_ARM_MPU |
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select INIT_ARM_PLL |
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select HAS_MCUX_USDHC1 |
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select HAS_MCUX_USDHC2 |
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select HAS_MCUX_CSI |
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select HAS_MCUX_FLEXCAN |
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config SOC_MIMXRT1052 |
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select HAS_MCUX_ELCDIF |
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select HAS_MCUX_ENET |
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select HAS_MCUX_SEMC |
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select CPU_HAS_FPU_DOUBLE_PRECISION |
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select CPU_HAS_ARM_MPU |
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select INIT_ARM_PLL |
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select INIT_VIDEO_PLL if DISPLAY_MCUX_ELCDIF |
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select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER |
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select HAS_MCUX_USDHC1 |
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select HAS_MCUX_USDHC2 |
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select HAS_MCUX_CSI |
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select HAS_MCUX_FLEXCAN |
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select HAS_MCUX_PWM |
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select HAS_MCUX_SRC |
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select HAS_MCUX_XBARA |
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config SOC_MIMXRT1061 |
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select HAS_MCUX_ENET |
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select HAS_MCUX_SEMC |
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select CPU_HAS_FPU_DOUBLE_PRECISION |
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select CPU_HAS_ARM_MPU |
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select INIT_ARM_PLL |
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select HAS_MCUX_USDHC1 |
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select HAS_MCUX_USDHC2 |
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select HAS_MCUX_CSI |
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select HAS_MCUX_FLEXCAN |
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config SOC_MIMXRT1062 |
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select HAS_MCUX_ELCDIF |
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select HAS_MCUX_ENET |
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select HAS_MCUX_PWM |
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select HAS_MCUX_QTMR |
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select HAS_MCUX_SEMC |
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select HAS_MCUX_SNVS |
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select CPU_HAS_FPU_DOUBLE_PRECISION |
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select CPU_HAS_ARM_MPU |
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select INIT_ARM_PLL |
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select INIT_VIDEO_PLL if DISPLAY_MCUX_ELCDIF |
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select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER |
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select HAS_MCUX_USDHC1 |
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select HAS_MCUX_USDHC2 |
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select HAS_MCUX_CSI |
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select HAS_MCUX_FLEXCAN |
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select HAS_MCUX_I2S |
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select HAS_MCUX_ADC_ETC |
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select HAS_MCUX_SRC |
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select HAS_MCUX_XBARA |
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config SOC_MIMXRT1064 |
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select HAS_MCUX_ELCDIF |
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select HAS_MCUX_ENET |
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select HAS_MCUX_PWM |
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select HAS_MCUX_QTMR |
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select HAS_MCUX_SEMC |
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select HAS_MCUX_SNVS |
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select HAS_MCUX_SRC |
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select CPU_HAS_FPU_DOUBLE_PRECISION |
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select CPU_HAS_ARM_MPU |
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select INIT_ARM_PLL |
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select INIT_VIDEO_PLL if DISPLAY_MCUX_ELCDIF |
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select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER |
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select HAS_MCUX_USDHC1 |
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select HAS_MCUX_USDHC2 |
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select HAS_MCUX_CSI |
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select HAS_MCUX_FLEXCAN |
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select HAS_SWO |
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@ -0,0 +1,28 @@
@@ -0,0 +1,28 @@
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# Copyright 2024 NXP |
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# SPDX-License-Identifier: Apache-2.0 |
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|
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|
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if SOC_SERIES_IMXRT10XX |
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|
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config NUM_IRQS |
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default 80 if SOC_MIMXRT1011 |
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default 142 if SOC_MIMXRT1015 || \ |
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SOC_MIMXRT1021 || \ |
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SOC_MIMXRT1024 |
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default 157 if SOC_MIMXRT1042 |
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default 160 if SOC_MIMXRT1052 || \ |
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SOC_MIMXRT1062 || \ |
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SOC_MIMXRT1064 |
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|
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config DCDC_VALUE |
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default 0x12 if SOC_MIMXRT1011 || \ |
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SOC_MIMXRT1015 || \ |
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SOC_MIMXRT1021 || \ |
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SOC_MIMXRT1024 |
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default 0x13 |
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|
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config GPIO |
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default y |
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|
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endif # SOC_SERIES_IMXRT10XX |
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@@ -0,0 +1,238 @@
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# Copyright 2024 NXP |
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# SPDX-License-Identifier: Apache-2.0 |
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|
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config SOC_SERIES_IMXRT10XX |
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bool |
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select SOC_FAMILY_NXP_IMXRT |
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|
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config SOC_SERIES |
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default "imxrt10xx" if SOC_SERIES_IMXRT10XX |
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|
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config SOC_MIMXRT1011 |
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bool |
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select SOC_SERIES_IMXRT10XX |
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config SOC_MIMXRT1015 |
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bool |
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select SOC_SERIES_IMXRT10XX |
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|
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config SOC_MIMXRT1021 |
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bool |
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select SOC_SERIES_IMXRT10XX |
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|
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config SOC_MIMXRT1024 |
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bool |
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select SOC_SERIES_IMXRT10XX |
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|
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config SOC_MIMXRT1042 |
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bool |
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select SOC_SERIES_IMXRT10XX |
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|
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config SOC_MIMXRT1051 |
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bool |
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select SOC_SERIES_IMXRT10XX |
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|
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config SOC_MIMXRT1052 |
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bool |
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select SOC_SERIES_IMXRT10XX |
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|
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config SOC_MIMXRT1061 |
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bool |
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select SOC_SERIES_IMXRT10XX |
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|
||||
config SOC_MIMXRT1062 |
||||
bool |
||||
select SOC_SERIES_IMXRT10XX |
||||
|
||||
config SOC_MIMXRT1064 |
||||
bool |
||||
select SOC_SERIES_IMXRT10XX |
||||
|
||||
config SOC |
||||
default "mimxrt1011" if SOC_MIMXRT1011 |
||||
default "mimxrt1015" if SOC_MIMXRT1015 |
||||
default "mimxrt1021" if SOC_MIMXRT1021 |
||||
default "mimxrt1024" if SOC_MIMXRT1024 |
||||
default "mimxrt1042" if SOC_MIMXRT1042 |
||||
default "mimxrt1051" if SOC_MIMXRT1051 |
||||
default "mimxrt1052" if SOC_MIMXRT1052 |
||||
default "mimxrt1061" if SOC_MIMXRT1061 |
||||
default "mimxrt1062" if SOC_MIMXRT1062 |
||||
default "mimxrt1064" if SOC_MIMXRT1064 |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1011CAE4A |
||||
bool |
||||
select SOC_MIMXRT1011 |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1011DAE5A |
||||
bool |
||||
select SOC_MIMXRT1011 |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1015CAF4A |
||||
bool |
||||
select SOC_MIMXRT1015 |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1015DAF5A |
||||
bool |
||||
select SOC_MIMXRT1015 |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1021CAF4A |
||||
bool |
||||
select SOC_MIMXRT1021 |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1021CAG4A |
||||
bool |
||||
select SOC_MIMXRT1021 |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1021DAF5A |
||||
bool |
||||
select SOC_MIMXRT1021 |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1021DAG5A |
||||
bool |
||||
select SOC_MIMXRT1021 |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1024CAG4A |
||||
bool |
||||
select SOC_MIMXRT1024 |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1024DAG5A |
||||
bool |
||||
select SOC_MIMXRT1024 |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1041DFP6B |
||||
bool |
||||
select SOC_MIMXRT1042 |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1041DJM6B |
||||
bool |
||||
select SOC_MIMXRT1042 |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1041XFP5B |
||||
bool |
||||
select SOC_MIMXRT1042 |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1041XJM5B |
||||
bool |
||||
select SOC_MIMXRT1042 |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1042DFP6B |
||||
bool |
||||
select SOC_MIMXRT1042 |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1042DJM6B |
||||
bool |
||||
select SOC_MIMXRT1042 |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1042XFP5B |
||||
bool |
||||
select SOC_MIMXRT1042 |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1042XJM5B |
||||
bool |
||||
select SOC_MIMXRT1042 |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1051CVL5A |
||||
bool |
||||
select SOC_MIMXRT1051 |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1051DVL6A |
||||
bool |
||||
select SOC_MIMXRT1051 |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1052CVJ5B |
||||
bool |
||||
select SOC_MIMXRT1052 |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1052CVL5A |
||||
bool |
||||
select SOC_MIMXRT1052 |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1052CVL5B |
||||
bool |
||||
select SOC_MIMXRT1052 |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1052DVJ6B |
||||
bool |
||||
select SOC_MIMXRT1052 |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1052DVL6A |
||||
bool |
||||
select SOC_MIMXRT1052 |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1052DVL6B |
||||
bool |
||||
select SOC_MIMXRT1052 |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1061CVL5A |
||||
bool |
||||
select SOC_MIMXRT1061 |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1061DVL6A |
||||
bool |
||||
select SOC_MIMXRT1061 |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1062CVJ5A |
||||
bool |
||||
select SOC_MIMXRT1062 |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1062CVJ5B |
||||
bool |
||||
select SOC_MIMXRT1062 |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1062CVL5A |
||||
bool |
||||
select SOC_MIMXRT1062 |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1062DVJ6A |
||||
bool |
||||
select SOC_MIMXRT1062 |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1062DVL6A |
||||
bool |
||||
select SOC_MIMXRT1062 |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1064CVL5A |
||||
bool |
||||
select SOC_MIMXRT1064 |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1064DVL6A |
||||
bool |
||||
select SOC_MIMXRT1064 |
||||
|
||||
config SOC_PART_NUMBER |
||||
default "MIMXRT1011CAE4A" if SOC_PART_NUMBER_MIMXRT1011CAE4A |
||||
default "MIMXRT1011DAE5A" if SOC_PART_NUMBER_MIMXRT1011DAE5A |
||||
default "MIMXRT1015CAF4A" if SOC_PART_NUMBER_MIMXRT1015CAF4A |
||||
default "MIMXRT1015DAF5A" if SOC_PART_NUMBER_MIMXRT1015DAF5A |
||||
default "MIMXRT1021CAF4A" if SOC_PART_NUMBER_MIMXRT1021CAF4A |
||||
default "MIMXRT1021CAG4A" if SOC_PART_NUMBER_MIMXRT1021CAG4A |
||||
default "MIMXRT1021DAF5A" if SOC_PART_NUMBER_MIMXRT1021DAF5A |
||||
default "MIMXRT1021DAG5A" if SOC_PART_NUMBER_MIMXRT1021DAG5A |
||||
default "MIMXRT1024CAG4A" if SOC_PART_NUMBER_MIMXRT1024CAG4A |
||||
default "MIMXRT1024DAG5A" if SOC_PART_NUMBER_MIMXRT1024DAG5A |
||||
default "MIMXRT1041DFP6B" if SOC_PART_NUMBER_MIMXRT1041DFP6B |
||||
default "MIMXRT1041DJM6B" if SOC_PART_NUMBER_MIMXRT1041DJM6B |
||||
default "MIMXRT1041XFP5B" if SOC_PART_NUMBER_MIMXRT1041XFP5B |
||||
default "MIMXRT1041XJM5B" if SOC_PART_NUMBER_MIMXRT1041XJM5B |
||||
default "MIMXRT1042DFP6B" if SOC_PART_NUMBER_MIMXRT1042DFP6B |
||||
default "MIMXRT1042DJM6B" if SOC_PART_NUMBER_MIMXRT1042DJM6B |
||||
default "MIMXRT1042XFP5B" if SOC_PART_NUMBER_MIMXRT1042XFP5B |
||||
default "MIMXRT1042XJM5B" if SOC_PART_NUMBER_MIMXRT1042XJM5B |
||||
default "MIMXRT1051CVL5A" if SOC_PART_NUMBER_MIMXRT1051CVL5A |
||||
default "MIMXRT1051DVL6A" if SOC_PART_NUMBER_MIMXRT1051DVL6A |
||||
default "MIMXRT1052CVJ5B" if SOC_PART_NUMBER_MIMXRT1052CVJ5B |
||||
default "MIMXRT1052CVL5A" if SOC_PART_NUMBER_MIMXRT1052CVL5A |
||||
default "MIMXRT1052CVL5B" if SOC_PART_NUMBER_MIMXRT1052CVL5B |
||||
default "MIMXRT1052DVJ6B" if SOC_PART_NUMBER_MIMXRT1052DVJ6B |
||||
default "MIMXRT1052DVL6A" if SOC_PART_NUMBER_MIMXRT1052DVL6A |
||||
default "MIMXRT1052DVL6B" if SOC_PART_NUMBER_MIMXRT1052DVL6B |
||||
default "MIMXRT1061CVL5A" if SOC_PART_NUMBER_MIMXRT1061CVL5A |
||||
default "MIMXRT1061DVL6A" if SOC_PART_NUMBER_MIMXRT1061DVL6A |
||||
default "MIMXRT1062CVJ5A" if SOC_PART_NUMBER_MIMXRT1062CVJ5A |
||||
default "MIMXRT1062CVJ5B" if SOC_PART_NUMBER_MIMXRT1062CVJ5B |
||||
default "MIMXRT1062CVL5A" if SOC_PART_NUMBER_MIMXRT1062CVL5A |
||||
default "MIMXRT1062DVJ6A" if SOC_PART_NUMBER_MIMXRT1062DVJ6A |
||||
default "MIMXRT1062DVL6A" if SOC_PART_NUMBER_MIMXRT1062DVL6A |
||||
default "MIMXRT1064CVL5A" if SOC_PART_NUMBER_MIMXRT1064CVL5A |
||||
default "MIMXRT1064DVL6A" if SOC_PART_NUMBER_MIMXRT1064DVL6A |
||||
@ -0,0 +1,19 @@
@@ -0,0 +1,19 @@
|
||||
# |
||||
# Copyright 2024 NXP |
||||
# |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
# |
||||
|
||||
zephyr_sources(soc.c) |
||||
zephyr_sources_ifdef(CONFIG_PM power.c) |
||||
|
||||
zephyr_include_directories(.) |
||||
|
||||
if(CONFIG_MEMC_MCUX_FLEXSPI) |
||||
zephyr_sources(flexspi.c) |
||||
if(CONFIG_FLASH_MCUX_FLEXSPI_XIP) |
||||
zephyr_code_relocate(FILES flexspi.c LOCATION ITCM_TEXT) |
||||
endif() |
||||
endif() |
||||
|
||||
set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") |
||||
@ -0,0 +1,74 @@
@@ -0,0 +1,74 @@
|
||||
# Copyright 2024 NXP |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
|
||||
config SOC_SERIES_IMXRT11XX |
||||
select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS |
||||
select CPU_CORTEX_M_HAS_DWT |
||||
select PLATFORM_SPECIFIC_INIT |
||||
select ARM |
||||
select CLOCK_CONTROL |
||||
select HAS_MCUX_CACHE |
||||
select HAS_MCUX |
||||
select HAS_MCUX_SEMC |
||||
select HAS_MCUX_CCM_REV2 |
||||
select HAS_MCUX_IGPIO |
||||
select HAS_MCUX_LPI2C |
||||
select HAS_MCUX_LPSPI |
||||
select HAS_MCUX_LPADC |
||||
select HAS_MCUX_LPUART |
||||
select HAS_MCUX_ELCDIF |
||||
select HAS_MCUX_MIPI_DSI |
||||
select HAS_MCUX_GPT |
||||
select HAS_MCUX_FLEXSPI |
||||
select HAS_MCUX_FLEXCAN |
||||
select CPU_HAS_ARM_MPU |
||||
select INIT_ARM_PLL |
||||
select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER |
||||
select INIT_VIDEO_PLL |
||||
select HAS_MCUX_EDMA |
||||
select CPU_HAS_ICACHE if CPU_CORTEX_M7 |
||||
select CPU_HAS_DCACHE if CPU_CORTEX_M7 |
||||
select CPU_HAS_FPU_DOUBLE_PRECISION |
||||
select BYPASS_LDO_LPSR |
||||
select ADJUST_LDO |
||||
select HAS_MCUX_PWM |
||||
select HAS_MCUX_USDHC1 |
||||
select HAS_MCUX_USDHC2 |
||||
select HAS_MCUX_ENET |
||||
select HAS_MCUX_GPC |
||||
select HAS_MCUX_I2S |
||||
select HAS_MCUX_USB_EHCI |
||||
select HAS_MCUX_ACMP |
||||
select HAS_MCUX_SRC_V2 |
||||
select HAS_MCUX_IOMUXC |
||||
select HAS_MCUX_XBARA |
||||
select HAS_SWO |
||||
|
||||
config SOC_MIMXRT1176_CM4 |
||||
select CPU_CORTEX_M4 |
||||
|
||||
config SOC_MIMXRT1176_CM7 |
||||
select CPU_CORTEX_M7 |
||||
|
||||
config SOC_MIMXRT1166_CM4 |
||||
select CPU_CORTEX_M4 |
||||
|
||||
config SOC_MIMXRT1166_CM7 |
||||
select CPU_CORTEX_M7 |
||||
|
||||
if SOC_SERIES_IMXRT11XX |
||||
|
||||
config MCUX_CORE_SUFFIX |
||||
default "_cm7" if SOC_MIMXRT1176_CM7 || SOC_MIMXRT1166_CM7 |
||||
default "_cm4" if SOC_MIMXRT1176_CM4 || SOC_MIMXRT1166_CM4 |
||||
|
||||
config BYPASS_LDO_LPSR |
||||
bool "Bypass LDO lpsr" |
||||
|
||||
config ADJUST_LDO |
||||
bool "Adjust LDO setting" |
||||
|
||||
config ADJUST_DCDC |
||||
bool "Adjust internal DCDC output" |
||||
|
||||
endif # SOC_SERIES_IMXRT11XX |
||||
@ -0,0 +1,35 @@
@@ -0,0 +1,35 @@
|
||||
# Copyright 2024 NXP |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
|
||||
if SOC_SERIES_IMXRT11XX |
||||
|
||||
config NUM_IRQS |
||||
default 218 |
||||
|
||||
config GPIO |
||||
default y |
||||
|
||||
if CORTEX_M_SYSTICK |
||||
|
||||
config SYS_CLOCK_HW_CYCLES_PER_SEC |
||||
default 996000000 if SOC_MIMXRT1176_CM7 |
||||
default 600000000 if SOC_MIMXRT1166_CM7 |
||||
default 400000000 if SOC_MIMXRT1176_CM4 |
||||
default 240000000 if SOC_MIMXRT1166_CM4 |
||||
|
||||
endif # CORTEX_M_SYSTICK |
||||
|
||||
config DCDC_VALUE |
||||
default 0x13 |
||||
|
||||
config FLEXSPI_CONFIG_BLOCK_OFFSET |
||||
default 0x400 if BOOT_FLEXSPI_NOR |
||||
|
||||
if SECOND_CORE_MCUX |
||||
|
||||
# RT Boot header is only needed on primary core |
||||
config NXP_IMXRT_BOOT_HEADER |
||||
depends on CPU_CORTEX_M7 |
||||
|
||||
endif |
||||
endif |
||||
@ -0,0 +1,95 @@
@@ -0,0 +1,95 @@
|
||||
# Copyright 2024 NXP |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
|
||||
config SOC_SERIES_IMXRT11XX |
||||
bool |
||||
select SOC_FAMILY_NXP_IMXRT |
||||
|
||||
config SOC_SERIES |
||||
default "imxrt11xx" if SOC_SERIES_IMXRT11XX |
||||
|
||||
config SOC_MIMXRT1166 |
||||
bool |
||||
select SOC_SERIES_IMXRT11XX |
||||
|
||||
config SOC_MIMXRT1176 |
||||
bool |
||||
select SOC_SERIES_IMXRT11XX |
||||
|
||||
config SOC_MIMXRT1166_CM4 |
||||
bool |
||||
select SOC_MIMXRT1166 |
||||
|
||||
config SOC_MIMXRT1166_CM7 |
||||
bool |
||||
select SOC_MIMXRT1166 |
||||
|
||||
config SOC_MIMXRT1176_CM4 |
||||
bool |
||||
select SOC_MIMXRT1176 |
||||
|
||||
config SOC_MIMXRT1176_CM7 |
||||
bool |
||||
select SOC_MIMXRT1176 |
||||
|
||||
config SOC |
||||
default "mimxrt1166" if SOC_MIMXRT1166 |
||||
default "mimxrt1176" if SOC_MIMXRT1176 |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1166DVM6A |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1176AVM8A |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1176CVM8A |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1176DVMAA |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1175AVM8A |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1175CVM8A |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1175DVMAA |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1173CVM8A |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1172AVM8A |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1172CVM8A |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1172DVMAA |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1171AVM8A |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1171CVM8A |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1171DVMAA |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER |
||||
default "MIMXRT1176AVM8A" if SOC_PART_NUMBER_MIMXRT1176AVM8A |
||||
default "MIMXRT1176CVM8A" if SOC_PART_NUMBER_MIMXRT1176CVM8A |
||||
default "MIMXRT1176DVMAA" if SOC_PART_NUMBER_MIMXRT1176DVMAA |
||||
default "MIMXRT1166DVM6A" if SOC_PART_NUMBER_MIMXRT1166DVM6A |
||||
default "MIMXRT1175AVM8A" if SOC_PART_NUMBER_MIMXRT1175AVM8A |
||||
default "MIMXRT1175CVM8A" if SOC_PART_NUMBER_MIMXRT1175CVM8A |
||||
default "MIMXRT1175DVMAA" if SOC_PART_NUMBER_MIMXRT1175DVMAA |
||||
default "MIMXRT1173CVM8A" if SOC_PART_NUMBER_MIMXRT1173CVM8A |
||||
default "MIMXRT1172AVM8A" if SOC_PART_NUMBER_MIMXRT1172AVM8A |
||||
default "MIMXRT1172CVM8A" if SOC_PART_NUMBER_MIMXRT1172CVM8A |
||||
default "MIMXRT1172DVMAA" if SOC_PART_NUMBER_MIMXRT1172DVMAA |
||||
default "MIMXRT1171AVM8A" if SOC_PART_NUMBER_MIMXRT1171AVM8A |
||||
default "MIMXRT1171CVM8A" if SOC_PART_NUMBER_MIMXRT1171CVM8A |
||||
default "MIMXRT1171DVMAA" if SOC_PART_NUMBER_MIMXRT1171DVMAA |
||||
@ -0,0 +1,65 @@
@@ -0,0 +1,65 @@
|
||||
/*
|
||||
* Copyright (c) 2023, NXP |
||||
* |
||||
* SPDX-License-Identifier: Apache-2.0 |
||||
*/ |
||||
|
||||
#include <fsl_clock.h> |
||||
#include <fsl_flexspi.h> |
||||
#include <soc.h> |
||||
#include <errno.h> |
||||
#include <zephyr/irq.h> |
||||
#include <zephyr/dt-bindings/clock/imx_ccm_rev2.h> |
||||
|
||||
uint32_t flexspi_clock_set_freq(uint32_t clock_name, uint32_t rate) |
||||
{ |
||||
clock_name_t root; |
||||
uint32_t root_rate; |
||||
FLEXSPI_Type *flexspi; |
||||
clock_root_t flexspi_clk; |
||||
clock_ip_name_t clk_gate; |
||||
uint32_t divider; |
||||
|
||||
switch (clock_name) { |
||||
case IMX_CCM_FLEXSPI_CLK: |
||||
flexspi_clk = kCLOCK_Root_Flexspi1; |
||||
flexspi = (FLEXSPI_Type *)DT_REG_ADDR(DT_NODELABEL(flexspi)); |
||||
clk_gate = kCLOCK_Flexspi1; |
||||
break; |
||||
case IMX_CCM_FLEXSPI2_CLK: |
||||
flexspi_clk = kCLOCK_Root_Flexspi2; |
||||
flexspi = (FLEXSPI_Type *)DT_REG_ADDR(DT_NODELABEL(flexspi2)); |
||||
clk_gate = kCLOCK_Flexspi2; |
||||
break; |
||||
default: |
||||
return -ENOTSUP; |
||||
} |
||||
root = CLOCK_GetRootClockSource(flexspi_clk, |
||||
CLOCK_GetRootClockMux(flexspi_clk)); |
||||
/* Get clock root frequency */ |
||||
root_rate = CLOCK_GetFreq(root); |
||||
/* Select a divider based on root clock frequency. We round the
|
||||
* divider up, so that the resulting clock frequency is lower than |
||||
* requested when we can't output the exact requested frequency |
||||
*/ |
||||
divider = ((root_rate + (rate - 1)) / rate); |
||||
/* Cap divider to max value */ |
||||
divider = MIN(divider, CCM_CLOCK_ROOT_CONTROL_DIV_MASK); |
||||
|
||||
while (FLEXSPI_GetBusIdleStatus(flexspi) == false) { |
||||
/* Spin */ |
||||
} |
||||
FLEXSPI_Enable(flexspi, false); |
||||
|
||||
CLOCK_DisableClock(clk_gate); |
||||
|
||||
CLOCK_SetRootClockDiv(flexspi_clk, divider); |
||||
|
||||
CLOCK_EnableClock(clk_gate); |
||||
|
||||
FLEXSPI_Enable(flexspi, true); |
||||
|
||||
FLEXSPI_SoftwareReset(flexspi); |
||||
|
||||
return 0; |
||||
} |
||||
@ -0,0 +1,21 @@
@@ -0,0 +1,21 @@
|
||||
/* |
||||
* Copyright (c) 2014 Wind River Systems, Inc. |
||||
* |
||||
* SPDX-License-Identifier: Apache-2.0 |
||||
*/ |
||||
|
||||
#include <zephyr/devicetree.h> |
||||
|
||||
|
||||
#define IS_CHOSEN_SRAM(x) (DT_DEP_ORD(DT_NODELABEL(x)) == DT_DEP_ORD(DT_CHOSEN(zephyr_sram))) |
||||
|
||||
MEMORY |
||||
{ |
||||
|
||||
#if (DT_REG_SIZE(DT_NODELABEL(sdram0)) > 0) && !IS_CHOSEN_SRAM(sdram0) |
||||
SDRAM (wx) : ORIGIN = DT_REG_ADDR(DT_NODELABEL(sdram0)), LENGTH = DT_REG_SIZE(DT_NODELABEL(sdram0)) |
||||
#endif |
||||
|
||||
} |
||||
|
||||
#include <zephyr/arch/arm/cortex_m/scripts/linker.ld> |
||||
@ -0,0 +1,48 @@
@@ -0,0 +1,48 @@
|
||||
/*
|
||||
* Copyright (c) 2017, NXP |
||||
* |
||||
* SPDX-License-Identifier: Apache-2.0 |
||||
*/ |
||||
|
||||
#ifndef _SOC__H_ |
||||
#define _SOC__H_ |
||||
|
||||
#include <zephyr/sys/util.h> |
||||
|
||||
#ifndef _ASMLANGUAGE |
||||
|
||||
#include <fsl_common.h> |
||||
|
||||
/* Add include for DTS generated information */ |
||||
#include <zephyr/devicetree.h> |
||||
|
||||
#ifdef __cplusplus |
||||
extern "C" { |
||||
#endif |
||||
|
||||
#if CONFIG_I2S_MCUX_SAI |
||||
void imxrt_audio_codec_pll_init(uint32_t clock_name, uint32_t clk_src, |
||||
uint32_t clk_pre_div, uint32_t clk_src_div); |
||||
|
||||
#endif |
||||
|
||||
#if CONFIG_MIPI_DSI |
||||
void imxrt_pre_init_display_interface(void); |
||||
|
||||
void imxrt_post_init_display_interface(void); |
||||
#endif |
||||
|
||||
void flexspi_clock_set_div(uint32_t value); |
||||
uint32_t flexspi_clock_get_freq(void); |
||||
|
||||
#ifdef CONFIG_MEMC |
||||
uint32_t flexspi_clock_set_freq(uint32_t clock_name, uint32_t rate); |
||||
#endif |
||||
|
||||
#ifdef __cplusplus |
||||
} |
||||
#endif |
||||
|
||||
#endif /* !_ASMLANGUAGE */ |
||||
|
||||
#endif /* _SOC__H_ */ |
||||
@ -0,0 +1,65 @@
@@ -0,0 +1,65 @@
|
||||
# Copyright 2020, 2024 NXP |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
|
||||
config SOC_SERIES_IMXRT6XX |
||||
select ARM |
||||
select CPU_CORTEX_M33 |
||||
select CPU_CORTEX_M_HAS_DWT |
||||
select CLOCK_CONTROL |
||||
select CODE_DATA_RELOCATION_SRAM if FLASH_MCUX_FLEXSPI_XIP |
||||
select PLATFORM_SPECIFIC_INIT |
||||
select HAS_PM |
||||
select CPU_HAS_ARM_SAU |
||||
select CPU_HAS_ARM_MPU |
||||
select CPU_HAS_FPU |
||||
select ARMV8_M_DSP |
||||
select ARM_TRUSTZONE_M |
||||
select CPU_CORTEX_M_HAS_SYSTICK |
||||
select HAS_MCUX |
||||
select HAS_MCUX_SYSCON |
||||
select HAS_MCUX_FLEXCOMM |
||||
select HAS_MCUX_FLEXSPI |
||||
select HAS_MCUX_CACHE |
||||
select HAS_MCUX_LPC_DMA |
||||
select HAS_MCUX_LPADC |
||||
select HAS_MCUX_OS_TIMER |
||||
select HAS_MCUX_LPC_RTC |
||||
select HAS_MCUX_TRNG |
||||
select HAS_MCUX_SCTIMER |
||||
select HAS_MCUX_USDHC1 |
||||
select HAS_MCUX_USDHC2 |
||||
select INIT_SYS_PLL |
||||
select HAS_MCUX_USB_LPCIP3511 |
||||
select HAS_MCUX_CTIMER |
||||
|
||||
if SOC_SERIES_IMXRT6XX |
||||
|
||||
config MCUX_CORE_SUFFIX |
||||
default "_cm33" if SOC_MIMXRT685S_CM33 |
||||
|
||||
config INIT_SYS_PLL |
||||
bool "Initialize SYS PLL" |
||||
|
||||
config INIT_AUDIO_PLL |
||||
bool "Initialize Audio PLL" |
||||
|
||||
config XTAL_SYS_CLK_HZ |
||||
int "External oscillator frequency" |
||||
help |
||||
Set the external oscillator frequency in Hz. This should be set by the |
||||
board's defconfig. |
||||
|
||||
config SYSOSC_SETTLING_US |
||||
int "System oscillator settling time" |
||||
help |
||||
Set the board system oscillator settling time in us. This should be set by the |
||||
board's defconfig. |
||||
|
||||
config IMXRT6XX_CODE_CACHE |
||||
bool "Code cache" |
||||
default y |
||||
help |
||||
Enable code cache for FlexSPI region at boot. If this Kconfig is |
||||
cleared, the CACHE64 controller will be disabled during SOC init |
||||
|
||||
endif |
||||
@ -0,0 +1,33 @@
@@ -0,0 +1,33 @@
|
||||
# Copyright 2024 NXP |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
|
||||
config SOC_SERIES_IMXRT6XX |
||||
bool |
||||
select SOC_FAMILY_NXP_IMXRT |
||||
|
||||
config SOC_SERIES |
||||
default "imxrt6xx" if SOC_SERIES_IMXRT6XX |
||||
|
||||
config SOC_MIMXRT685S_CM33 |
||||
bool |
||||
select SOC_SERIES_IMXRT6XX |
||||
|
||||
config SOC |
||||
default "mimxrt685s" if SOC_MIMXRT685S_CM33 |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT685SFVKB |
||||
bool |
||||
select SOC_MIMXRT685S_CM33 |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT685SFFOB |
||||
bool |
||||
select SOC_MIMXRT685S_CM33 |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT685SFAWBR |
||||
bool |
||||
select SOC_MIMXRT685S_CM33 |
||||
|
||||
config SOC_PART_NUMBER |
||||
default "MIMXRT685SFVKB" if SOC_PART_NUMBER_MIMXRT685SFVKB |
||||
default "MIMXRT685SFFOB" if SOC_PART_NUMBER_MIMXRT685SFFOB |
||||
default "MIMXRT685SFAWBR" if SOC_PART_NUMBER_MIMXRT685SFAWBR |
||||
@ -0,0 +1,28 @@
@@ -0,0 +1,28 @@
|
||||
family: |
||||
- name: nxp_imxrt |
||||
series: |
||||
- name: imxrt10xx |
||||
socs: |
||||
- name: mimxrt1011 |
||||
- name: mimxrt1015 |
||||
- name: mimxrt1021 |
||||
- name: mimxrt1024 |
||||
- name: mimxrt1042 |
||||
- name: mimxrt1051 |
||||
- name: mimxrt1052 |
||||
- name: mimxrt1061 |
||||
- name: mimxrt1062 |
||||
- name: mimxrt1064 |
||||
- name: imxrt11xx |
||||
socs: |
||||
- name: mimxrt1166 |
||||
cpuclusters: |
||||
- name: cm7 |
||||
- name: cm4 |
||||
- name: mimxrt1176 |
||||
cpuclusters: |
||||
- name: cm7 |
||||
- name: cm4 |
||||
- name: imxrt6xx |
||||
socs: |
||||
- name: mimxrt685s |
||||
@ -1,5 +1,5 @@
@@ -1,5 +1,5 @@
|
||||
/* |
||||
* Copyright (c) 2021 NXP |
||||
* Copyright 2021-2022, 2024 NXP |
||||
* |
||||
* SPDX-License-Identifier: Apache-2.0 |
||||
*/ |
||||
@ -1,76 +0,0 @@
@@ -1,76 +0,0 @@
|
||||
# |
||||
# Copyright (c) 2017-2021, NXP |
||||
# |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
# |
||||
zephyr_sources_ifdef(CONFIG_SOC_SERIES_IMX_RT11XX soc_rt11xx.c) |
||||
zephyr_sources_ifdef(CONFIG_SOC_SERIES_IMX_RT10XX soc_rt10xx.c) |
||||
|
||||
zephyr_linker_sources_ifdef(CONFIG_NXP_IMX_RT_BOOT_HEADER |
||||
ROM_START SORT_KEY 0 boot_header.ld) |
||||
|
||||
# Add custom mpu regions |
||||
zephyr_sources(mpu_regions.c) |
||||
|
||||
zephyr_linker_section_configure( |
||||
SECTION .rom_start |
||||
INPUT ".boot_hdr.conf" |
||||
OFFSET ${CONFIG_FLEXSPI_CONFIG_BLOCK_OFFSET} |
||||
KEEP |
||||
PRIO 10 |
||||
) |
||||
|
||||
if(CONFIG_DEVICE_CONFIGURATION_DATA) |
||||
set(boot_hdr_dcd_data_section ".boot_hdr.dcd_data") |
||||
endif() |
||||
|
||||
if(CONFIG_PM) |
||||
zephyr_sources_ifdef(CONFIG_SOC_SERIES_IMX_RT11XX power_rt11xx.c) |
||||
endif() |
||||
|
||||
if (CONFIG_SOC_SERIES_IMX_RT10XX AND CONFIG_MEMC_MCUX_FLEXSPI) |
||||
zephyr_sources(flexspi_rt10xx.c) |
||||
if (CONFIG_FLASH_MCUX_FLEXSPI_XIP) |
||||
zephyr_code_relocate(FILES flexspi_rt10xx.c LOCATION ITCM_TEXT) |
||||
endif() |
||||
endif () |
||||
|
||||
|
||||
if (CONFIG_SOC_SERIES_IMX_RT11XX AND CONFIG_MEMC_MCUX_FLEXSPI) |
||||
zephyr_sources(flexspi_rt11xx.c) |
||||
if (CONFIG_FLASH_MCUX_FLEXSPI_XIP) |
||||
zephyr_code_relocate(FILES flexspi_rt11xx.c LOCATION ITCM_TEXT) |
||||
endif() |
||||
endif () |
||||
|
||||
if (CONFIG_PM AND CONFIG_SOC_SERIES_IMX_RT10XX) |
||||
zephyr_sources(power_rt10xx.c) |
||||
zephyr_code_relocate(FILES power_rt10xx.c LOCATION ITCM_TEXT) |
||||
if (CONFIG_SOC_MIMXRT1064) |
||||
zephyr_sources(lpm_rt1064.c) |
||||
zephyr_code_relocate(FILES lpm_rt1064.c LOCATION ITCM_TEXT) |
||||
endif() |
||||
endif() |
||||
|
||||
zephyr_compile_definitions( |
||||
XIP_EXTERNAL_FLASH |
||||
) |
||||
|
||||
zephyr_compile_definitions_ifdef(CONFIG_ENTROPY_MCUX_CAAM CACHE_MODE_WRITE_THROUGH) |
||||
|
||||
zephyr_compile_definitions_ifdef(CONFIG_USB_DEVICE_DRIVER DATA_SECTION_IS_CACHEABLE=1) |
||||
|
||||
# flexram header |
||||
zephyr_library_include_directories(${ZEPHYR_BASE}/drivers/memc) |
||||
|
||||
zephyr_linker_section_configure( |
||||
SECTION .rom_start |
||||
INPUT ".boot_hdr.ivt" |
||||
".boot_hdr.data" |
||||
${boot_hdr_dcd_data_section} |
||||
OFFSET ${CONFIG_IMAGE_VECTOR_TABLE_OFFSET} |
||||
KEEP |
||||
PRIO 11 |
||||
) |
||||
|
||||
set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") |
||||
@ -1,24 +0,0 @@
@@ -1,24 +0,0 @@
|
||||
# i.MX RT1010 |
||||
|
||||
# Copyright (c) 2019, NXP |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
|
||||
if SOC_MIMXRT1011 |
||||
|
||||
config SOC |
||||
string |
||||
default "mimxrt1011" |
||||
|
||||
config NUM_IRQS |
||||
default 80 |
||||
|
||||
config DCDC_VALUE |
||||
default 0x12 |
||||
|
||||
config GPIO |
||||
default y |
||||
|
||||
config FLEXSPI_CONFIG_BLOCK_OFFSET |
||||
default 0x400 |
||||
|
||||
endif # SOC_MIMXRT1010 |
||||
@ -1,20 +0,0 @@
@@ -1,20 +0,0 @@
|
||||
# i.MX RT1015 |
||||
|
||||
# Copyright (c) 2019, NXP |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
|
||||
if SOC_MIMXRT1015 |
||||
|
||||
config SOC |
||||
default "mimxrt1015" |
||||
|
||||
config NUM_IRQS |
||||
default 142 |
||||
|
||||
config DCDC_VALUE |
||||
default 0x12 |
||||
|
||||
config GPIO |
||||
default y |
||||
|
||||
endif # SOC_MIMXRT1015 |
||||
@ -1,20 +0,0 @@
@@ -1,20 +0,0 @@
|
||||
# i.MX RT1021 |
||||
|
||||
# Copyright (c) 2018, NXP |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
|
||||
if SOC_MIMXRT1021 |
||||
|
||||
config SOC |
||||
default "mimxrt1021" |
||||
|
||||
config NUM_IRQS |
||||
default 142 |
||||
|
||||
config DCDC_VALUE |
||||
default 0x12 |
||||
|
||||
config GPIO |
||||
default y |
||||
|
||||
endif # SOC_MIMXRT1021 |
||||
@ -1,20 +0,0 @@
@@ -1,20 +0,0 @@
|
||||
# i.MX RT1024 |
||||
|
||||
# Copyright (c) 2020, NXP |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
|
||||
if SOC_MIMXRT1024 |
||||
|
||||
config SOC |
||||
default "mimxrt1024" |
||||
|
||||
config NUM_IRQS |
||||
default 142 |
||||
|
||||
config DCDC_VALUE |
||||
default 0x12 |
||||
|
||||
config GPIO |
||||
default y |
||||
|
||||
endif # SOC_MIMXRT1024 |
||||
@ -1,19 +0,0 @@
@@ -1,19 +0,0 @@
|
||||
# Copyright 2023 NXP |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
|
||||
if SOC_MIMXRT1042 |
||||
|
||||
config SOC |
||||
default "mimxrt1042" |
||||
|
||||
config NUM_IRQS |
||||
default 157 |
||||
|
||||
config GPIO |
||||
default y |
||||
|
||||
# Set DCDC to 1.275V for 600 MHz AHB operation |
||||
config DCDC_VALUE |
||||
default 0x13 |
||||
|
||||
endif # SOC_MIMXRT1042 |
||||
@ -1,17 +0,0 @@
@@ -1,17 +0,0 @@
|
||||
# i.MX RT1052 |
||||
|
||||
# Copyright (c) 2017, NXP |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
|
||||
if SOC_MIMXRT1052 |
||||
|
||||
config SOC |
||||
default "mimxrt1052" |
||||
|
||||
config NUM_IRQS |
||||
default 160 |
||||
|
||||
config GPIO |
||||
default y |
||||
|
||||
endif # SOC_MIMXRT1052 |
||||
@ -1,17 +0,0 @@
@@ -1,17 +0,0 @@
|
||||
# i.MX RT1062 |
||||
|
||||
# Copyright (c) 2018, NXP |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
|
||||
if SOC_MIMXRT1062 |
||||
|
||||
config SOC |
||||
default "mimxrt1062" |
||||
|
||||
config NUM_IRQS |
||||
default 160 |
||||
|
||||
config GPIO |
||||
default y |
||||
|
||||
endif # SOC_MIMXRT1062 |
||||
@ -1,17 +0,0 @@
@@ -1,17 +0,0 @@
|
||||
# i.MX RT1064 |
||||
|
||||
# Copyright (c) 2018, NXP |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
|
||||
if SOC_MIMXRT1064 |
||||
|
||||
config SOC |
||||
default "mimxrt1064" |
||||
|
||||
config NUM_IRQS |
||||
default 160 |
||||
|
||||
config GPIO |
||||
default y |
||||
|
||||
endif # SOC_MIMXRT1064 |
||||
@ -1,20 +0,0 @@
@@ -1,20 +0,0 @@
|
||||
# i.MX RT1160 CM4 |
||||
|
||||
# Copyright (c) 2021, NXP |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
|
||||
if SOC_MIMXRT1166_CM4 |
||||
|
||||
config SOC |
||||
default "mimxrt1166_cm4" |
||||
|
||||
config NUM_IRQS |
||||
default 218 |
||||
|
||||
config GPIO |
||||
default y |
||||
|
||||
config SYS_CLOCK_HW_CYCLES_PER_SEC |
||||
default 240000000 if CORTEX_M_SYSTICK |
||||
|
||||
endif # SOC_MIMXRT1166_CM4 |
||||
@ -1,20 +0,0 @@
@@ -1,20 +0,0 @@
|
||||
# i.MX RT1160 CM7 |
||||
|
||||
# Copyright (c) 2021, NXP |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
|
||||
if SOC_MIMXRT1166_CM7 |
||||
|
||||
config SOC |
||||
default "mimxrt1166_cm7" |
||||
|
||||
config NUM_IRQS |
||||
default 218 |
||||
|
||||
config GPIO |
||||
default y |
||||
|
||||
config SYS_CLOCK_HW_CYCLES_PER_SEC |
||||
default 600000000 if CORTEX_M_SYSTICK |
||||
|
||||
endif # SOC_MIMXRT1166_CM7 |
||||
@ -1,20 +0,0 @@
@@ -1,20 +0,0 @@
|
||||
# i.MX RT1170 CM4 |
||||
|
||||
# Copyright (c) 2021, NXP |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
|
||||
if SOC_MIMXRT1176_CM4 |
||||
|
||||
config SOC |
||||
default "mimxrt1176_cm4" |
||||
|
||||
config NUM_IRQS |
||||
default 218 |
||||
|
||||
config GPIO |
||||
default y |
||||
|
||||
config SYS_CLOCK_HW_CYCLES_PER_SEC |
||||
default 400000000 if CORTEX_M_SYSTICK |
||||
|
||||
endif # SOC_MIMXRT1170_CM4 |
||||
@ -1,20 +0,0 @@
@@ -1,20 +0,0 @@
|
||||
# i.MX RT1170 CM7 |
||||
|
||||
# Copyright (c) 2021, NXP |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
|
||||
if SOC_MIMXRT1176_CM7 |
||||
|
||||
config SOC |
||||
default "mimxrt1176_cm7" |
||||
|
||||
config NUM_IRQS |
||||
default 218 |
||||
|
||||
config GPIO |
||||
default y |
||||
|
||||
config SYS_CLOCK_HW_CYCLES_PER_SEC |
||||
default 996000000 if CORTEX_M_SYSTICK |
||||
|
||||
endif # SOC_MIMXRT1176_CM7 |
||||
@ -1,14 +0,0 @@
@@ -1,14 +0,0 @@
|
||||
# iMX RT series |
||||
|
||||
# Copyright (c) 2017-2021,2023 NXP |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
|
||||
config SOC_SERIES_IMX_RT |
||||
bool "i.MX RT Series" |
||||
select ARM |
||||
select SOC_FAMILY_IMX |
||||
select CLOCK_CONTROL |
||||
select HAS_PM |
||||
select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS |
||||
help |
||||
Enable support for i.MX RT MCU series |
||||
@ -1,837 +0,0 @@
@@ -1,837 +0,0 @@
|
||||
# i.MX RT series |
||||
|
||||
# Copyright 2017-2021,2023 NXP |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
|
||||
choice |
||||
prompt "i.MX RT Selection" |
||||
depends on SOC_SERIES_IMX_RT |
||||
|
||||
config SOC_MIMXRT1011 |
||||
bool "SOC_MIMXRT1011" |
||||
select SOC_SERIES_IMX_RT10XX |
||||
select HAS_MCUX |
||||
select HAS_MCUX_CACHE |
||||
select HAS_MCUX_12B1MSPS_SAR |
||||
select HAS_MCUX_CCM |
||||
select HAS_MCUX_FLEXSPI |
||||
select HAS_MCUX_IGPIO |
||||
select HAS_MCUX_LPI2C |
||||
select HAS_MCUX_LPSPI |
||||
select HAS_MCUX_LPUART |
||||
select HAS_MCUX_GPT |
||||
select HAS_MCUX_TRNG |
||||
select CPU_HAS_FPU |
||||
select CPU_HAS_ARM_MPU |
||||
select CPU_HAS_ICACHE |
||||
select CPU_HAS_DCACHE |
||||
select INIT_ENET_PLL |
||||
select HAS_MCUX_USB_EHCI |
||||
select HAS_MCUX_EDMA |
||||
select HAS_MCUX_GPC |
||||
select HAS_MCUX_DCDC |
||||
select HAS_MCUX_PMU |
||||
select HAS_MCUX_IOMUXC |
||||
select HAS_SWO |
||||
|
||||
config SOC_MIMXRT1015 |
||||
bool "SOC_MIMXRT1015" |
||||
select SOC_SERIES_IMX_RT10XX |
||||
select HAS_MCUX |
||||
select HAS_MCUX_CACHE |
||||
select HAS_MCUX_12B1MSPS_SAR |
||||
select HAS_MCUX_CCM |
||||
select HAS_MCUX_FLEXSPI |
||||
select HAS_MCUX_IGPIO |
||||
select HAS_MCUX_LPI2C |
||||
select HAS_MCUX_LPSPI |
||||
select HAS_MCUX_LPUART |
||||
select HAS_MCUX_GPT |
||||
select HAS_MCUX_TRNG |
||||
select CPU_HAS_FPU |
||||
select CPU_HAS_FPU_DOUBLE_PRECISION |
||||
select CPU_HAS_ARM_MPU |
||||
select INIT_ENET_PLL |
||||
select HAS_MCUX_USB_EHCI |
||||
select HAS_MCUX_EDMA |
||||
select HAS_MCUX_GPC |
||||
select HAS_MCUX_DCDC |
||||
select HAS_MCUX_PMU |
||||
select HAS_MCUX_IOMUXC |
||||
select HAS_SWO |
||||
|
||||
config SOC_MIMXRT1021 |
||||
bool "SOC_MIMXRT1021" |
||||
select SOC_SERIES_IMX_RT10XX |
||||
select HAS_MCUX |
||||
select HAS_MCUX_CACHE |
||||
select HAS_MCUX_12B1MSPS_SAR |
||||
select HAS_MCUX_CCM |
||||
select HAS_MCUX_ENET |
||||
select HAS_MCUX_FLEXSPI |
||||
select HAS_MCUX_IGPIO |
||||
select HAS_MCUX_LPI2C |
||||
select HAS_MCUX_LPSPI |
||||
select HAS_MCUX_LPUART |
||||
select HAS_MCUX_GPT |
||||
select HAS_MCUX_SEMC |
||||
select HAS_MCUX_TRNG |
||||
select CPU_HAS_FPU_DOUBLE_PRECISION |
||||
select CPU_HAS_ARM_MPU |
||||
select INIT_ENET_PLL |
||||
select HAS_MCUX_USB_EHCI |
||||
select HAS_MCUX_USDHC1 |
||||
select HAS_MCUX_USDHC2 |
||||
select HAS_MCUX_EDMA |
||||
select HAS_MCUX_FLEXCAN |
||||
select HAS_MCUX_PWM |
||||
select HAS_MCUX_GPC |
||||
select HAS_MCUX_DCDC |
||||
select HAS_MCUX_PMU |
||||
select HAS_MCUX_IOMUXC |
||||
select HAS_SWO |
||||
|
||||
config SOC_MIMXRT1024 |
||||
bool "SOC_MIMXRT1024" |
||||
select SOC_SERIES_IMX_RT10XX |
||||
select HAS_MCUX |
||||
select HAS_MCUX_CACHE |
||||
select HAS_MCUX_12B1MSPS_SAR |
||||
select HAS_MCUX_CCM |
||||
select HAS_MCUX_ENET |
||||
select HAS_MCUX_FLEXSPI |
||||
select HAS_MCUX_IGPIO |
||||
select HAS_MCUX_LPI2C |
||||
select HAS_MCUX_LPSPI |
||||
select HAS_MCUX_LPUART |
||||
select HAS_MCUX_GPT |
||||
select HAS_MCUX_SEMC |
||||
select HAS_MCUX_TRNG |
||||
select CPU_HAS_FPU_DOUBLE_PRECISION |
||||
select CPU_HAS_ARM_MPU |
||||
select INIT_ENET_PLL |
||||
select HAS_MCUX_USB_EHCI |
||||
select HAS_MCUX_USDHC1 |
||||
select HAS_MCUX_USDHC2 |
||||
select HAS_MCUX_EDMA |
||||
select HAS_MCUX_FLEXCAN |
||||
select HAS_MCUX_SRC |
||||
select HAS_MCUX_GPC |
||||
select HAS_MCUX_DCDC |
||||
select HAS_MCUX_PMU |
||||
select HAS_MCUX_IOMUXC |
||||
select HAS_SWO |
||||
|
||||
config SOC_MIMXRT1042 |
||||
bool "SOC_MIMXRT1042" |
||||
select SOC_SERIES_IMX_RT10XX |
||||
select HAS_MCUX |
||||
select HAS_MCUX_CACHE |
||||
select HAS_MCUX_FLEXSPI |
||||
select HAS_MCUX_SEMC |
||||
select HAS_MCUX_IGPIO |
||||
select CPU_HAS_FPU_DOUBLE_PRECISION |
||||
select CPU_HAS_ARM_MPU |
||||
select INIT_ARM_PLL |
||||
select HAS_MCUX_EDMA |
||||
select HAS_MCUX_GPC |
||||
select HAS_MCUX_DCDC |
||||
select HAS_MCUX_PMU |
||||
select HAS_MCUX_IOMUXC |
||||
select HAS_SWO |
||||
|
||||
config SOC_MIMXRT1051 |
||||
bool "SOC_MIMXRT1051" |
||||
select SOC_SERIES_IMX_RT10XX |
||||
select HAS_MCUX |
||||
select HAS_MCUX_CACHE |
||||
select HAS_MCUX_12B1MSPS_SAR |
||||
select HAS_MCUX_CCM |
||||
select HAS_MCUX_ENET |
||||
select HAS_MCUX_FLEXSPI |
||||
select HAS_MCUX_IGPIO |
||||
select HAS_MCUX_LPI2C |
||||
select HAS_MCUX_LPSPI |
||||
select HAS_MCUX_LPUART |
||||
select HAS_MCUX_GPT |
||||
select HAS_MCUX_SEMC |
||||
select HAS_MCUX_TRNG |
||||
select CPU_HAS_FPU_DOUBLE_PRECISION |
||||
select CPU_HAS_ARM_MPU |
||||
select INIT_ARM_PLL |
||||
select HAS_MCUX_USB_EHCI |
||||
select HAS_MCUX_USDHC1 |
||||
select HAS_MCUX_USDHC2 |
||||
select HAS_MCUX_CSI |
||||
select HAS_MCUX_EDMA |
||||
select HAS_MCUX_FLEXCAN |
||||
select HAS_MCUX_GPC |
||||
select HAS_MCUX_DCDC |
||||
select HAS_MCUX_PMU |
||||
select HAS_MCUX_IOMUXC |
||||
select HAS_SWO |
||||
|
||||
config SOC_MIMXRT1052 |
||||
bool "SOC_MIMXRT1052" |
||||
select SOC_SERIES_IMX_RT10XX |
||||
select HAS_MCUX |
||||
select HAS_MCUX_CACHE |
||||
select HAS_MCUX_12B1MSPS_SAR |
||||
select HAS_MCUX_CCM |
||||
select HAS_MCUX_ELCDIF |
||||
select HAS_MCUX_ENET |
||||
select HAS_MCUX_FLEXSPI |
||||
select HAS_MCUX_IGPIO |
||||
select HAS_MCUX_LPI2C |
||||
select HAS_MCUX_LPSPI |
||||
select HAS_MCUX_LPUART |
||||
select HAS_MCUX_GPT |
||||
select HAS_MCUX_SEMC |
||||
select HAS_MCUX_TRNG |
||||
select CPU_HAS_FPU_DOUBLE_PRECISION |
||||
select CPU_HAS_ARM_MPU |
||||
select INIT_ARM_PLL |
||||
select INIT_VIDEO_PLL if DISPLAY_MCUX_ELCDIF |
||||
select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER |
||||
select HAS_MCUX_USB_EHCI |
||||
select HAS_MCUX_USDHC1 |
||||
select HAS_MCUX_USDHC2 |
||||
select HAS_MCUX_CSI |
||||
select HAS_MCUX_EDMA |
||||
select HAS_MCUX_FLEXCAN |
||||
select HAS_MCUX_PWM |
||||
select HAS_MCUX_GPC |
||||
select HAS_MCUX_DCDC |
||||
select HAS_MCUX_PMU |
||||
select HAS_MCUX_IOMUXC |
||||
select HAS_MCUX_SRC |
||||
select HAS_SWO |
||||
select HAS_MCUX_XBARA |
||||
|
||||
config SOC_MIMXRT1061 |
||||
bool "SOC_MIMXRT1061" |
||||
select SOC_SERIES_IMX_RT10XX |
||||
select HAS_MCUX |
||||
select HAS_MCUX_CACHE |
||||
select HAS_MCUX_12B1MSPS_SAR |
||||
select HAS_MCUX_CCM |
||||
select HAS_MCUX_ENET |
||||
select HAS_MCUX_FLEXSPI |
||||
select HAS_MCUX_IGPIO |
||||
select HAS_MCUX_LPI2C |
||||
select HAS_MCUX_LPSPI |
||||
select HAS_MCUX_LPUART |
||||
select HAS_MCUX_GPT |
||||
select HAS_MCUX_SEMC |
||||
select HAS_MCUX_TRNG |
||||
select CPU_HAS_FPU_DOUBLE_PRECISION |
||||
select CPU_HAS_ARM_MPU |
||||
select INIT_ARM_PLL |
||||
select HAS_MCUX_USB_EHCI |
||||
select HAS_MCUX_USDHC1 |
||||
select HAS_MCUX_USDHC2 |
||||
select HAS_MCUX_CSI |
||||
select HAS_MCUX_EDMA |
||||
select HAS_MCUX_FLEXCAN |
||||
select HAS_MCUX_GPC |
||||
select HAS_MCUX_DCDC |
||||
select HAS_MCUX_PMU |
||||
select HAS_MCUX_IOMUXC |
||||
select HAS_SWO |
||||
|
||||
config SOC_MIMXRT1062 |
||||
bool "SOC_MIMXRT1062" |
||||
select SOC_SERIES_IMX_RT10XX |
||||
select HAS_MCUX |
||||
select HAS_MCUX_CACHE |
||||
select HAS_MCUX_12B1MSPS_SAR |
||||
select HAS_MCUX_CCM |
||||
select HAS_MCUX_ELCDIF |
||||
select HAS_MCUX_ENET |
||||
select HAS_MCUX_FLEXSPI |
||||
select HAS_MCUX_PWM |
||||
select HAS_MCUX_IGPIO |
||||
select HAS_MCUX_LPI2C |
||||
select HAS_MCUX_LPSPI |
||||
select HAS_MCUX_LPUART |
||||
select HAS_MCUX_GPT |
||||
select HAS_MCUX_QTMR |
||||
select HAS_MCUX_SEMC |
||||
select HAS_MCUX_SNVS |
||||
select HAS_MCUX_TRNG |
||||
select CPU_HAS_FPU_DOUBLE_PRECISION |
||||
select CPU_HAS_ARM_MPU |
||||
select INIT_ARM_PLL |
||||
select INIT_VIDEO_PLL if DISPLAY_MCUX_ELCDIF |
||||
select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER |
||||
select HAS_MCUX_USB_EHCI |
||||
select HAS_MCUX_USDHC1 |
||||
select HAS_MCUX_USDHC2 |
||||
select HAS_MCUX_CSI |
||||
select HAS_MCUX_EDMA |
||||
select HAS_MCUX_FLEXCAN |
||||
select HAS_MCUX_I2S |
||||
select HAS_MCUX_GPC |
||||
select HAS_MCUX_DCDC |
||||
select HAS_MCUX_PMU |
||||
select HAS_MCUX_IOMUXC |
||||
select HAS_MCUX_ADC_ETC |
||||
select HAS_MCUX_SRC |
||||
select HAS_SWO |
||||
select HAS_MCUX_XBARA |
||||
|
||||
config SOC_MIMXRT1064 |
||||
bool "SOC_MIMXRT1064" |
||||
select SOC_SERIES_IMX_RT10XX |
||||
select HAS_MCUX |
||||
select HAS_MCUX_CACHE |
||||
select HAS_MCUX_12B1MSPS_SAR |
||||
select HAS_MCUX_CCM |
||||
select HAS_MCUX_ELCDIF |
||||
select HAS_MCUX_ENET |
||||
select HAS_MCUX_FLEXSPI |
||||
select HAS_MCUX_PWM |
||||
select HAS_MCUX_IGPIO |
||||
select HAS_MCUX_LPI2C |
||||
select HAS_MCUX_LPSPI |
||||
select HAS_MCUX_LPUART |
||||
select HAS_MCUX_GPT |
||||
select HAS_MCUX_QTMR |
||||
select HAS_MCUX_SEMC |
||||
select HAS_MCUX_SNVS |
||||
select HAS_MCUX_SRC |
||||
select HAS_MCUX_TRNG |
||||
select CPU_HAS_FPU_DOUBLE_PRECISION |
||||
select CPU_HAS_ARM_MPU |
||||
select INIT_ARM_PLL |
||||
select INIT_VIDEO_PLL if DISPLAY_MCUX_ELCDIF |
||||
select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER |
||||
select HAS_MCUX_USB_EHCI |
||||
select HAS_MCUX_USDHC1 |
||||
select HAS_MCUX_USDHC2 |
||||
select HAS_MCUX_CSI |
||||
select HAS_MCUX_EDMA |
||||
select HAS_MCUX_FLEXCAN |
||||
select HAS_MCUX_GPC |
||||
select HAS_MCUX_DCDC |
||||
select HAS_MCUX_PMU |
||||
select HAS_MCUX_IOMUXC |
||||
select HAS_SWO |
||||
|
||||
config SOC_MIMXRT1176_CM7 |
||||
bool "SOC_MIMXRT1176_CM7" |
||||
select CPU_CORTEX_M7 |
||||
select CPU_CORTEX_M_HAS_DWT |
||||
select SOC_SERIES_IMX_RT11XX |
||||
select HAS_MCUX_CACHE |
||||
select HAS_MCUX |
||||
select HAS_MCUX_SEMC |
||||
select HAS_MCUX_CCM_REV2 |
||||
select HAS_MCUX_IGPIO |
||||
select HAS_MCUX_LPI2C |
||||
select HAS_MCUX_LPSPI |
||||
select HAS_MCUX_LPADC |
||||
select HAS_MCUX_LPUART |
||||
select HAS_MCUX_ELCDIF |
||||
select HAS_MCUX_MIPI_DSI |
||||
select HAS_MCUX_GPT |
||||
select HAS_MCUX_FLEXSPI |
||||
select HAS_MCUX_FLEXCAN |
||||
select CPU_HAS_ARM_MPU |
||||
select INIT_ARM_PLL |
||||
select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER |
||||
select INIT_VIDEO_PLL |
||||
select HAS_MCUX_EDMA |
||||
select CPU_HAS_ICACHE |
||||
select CPU_HAS_DCACHE |
||||
select CPU_HAS_FPU_DOUBLE_PRECISION |
||||
select BYPASS_LDO_LPSR |
||||
select ADJUST_LDO |
||||
select HAS_MCUX_PWM |
||||
select HAS_MCUX_USDHC1 |
||||
select HAS_MCUX_USDHC2 |
||||
select HAS_MCUX_ENET |
||||
select HAS_MCUX_GPC |
||||
select HAS_MCUX_I2S |
||||
select HAS_MCUX_USB_EHCI |
||||
select HAS_MCUX_ACMP |
||||
select HAS_MCUX_SRC_V2 |
||||
select HAS_MCUX_IOMUXC |
||||
select HAS_MCUX_XBARA |
||||
select HAS_SWO |
||||
|
||||
config SOC_MIMXRT1176_CM4 |
||||
bool "SOC_MIMXRT1176_CM4" |
||||
select CPU_CORTEX_M4 |
||||
select SOC_SERIES_IMX_RT11XX |
||||
select HAS_MCUX_CACHE |
||||
select HAS_MCUX |
||||
select HAS_MCUX_SEMC |
||||
select HAS_MCUX_CCM_REV2 |
||||
select HAS_MCUX_IGPIO |
||||
select HAS_MCUX_LPI2C |
||||
select HAS_MCUX_LPSPI |
||||
select HAS_MCUX_FLEXSPI |
||||
select HAS_MCUX_LPUART |
||||
select HAS_MCUX_GPT |
||||
select CPU_HAS_FPU |
||||
select CPU_HAS_ARM_MPU |
||||
select INIT_ARM_PLL |
||||
select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER |
||||
select INIT_VIDEO_PLL |
||||
select HAS_MCUX_EDMA |
||||
select HAS_MCUX_PWM |
||||
select HAS_MCUX_USDHC1 |
||||
select HAS_MCUX_USDHC2 |
||||
select HAS_MCUX_ENET |
||||
select HAS_MCUX_GPC |
||||
select HAS_MCUX_I2S |
||||
select HAS_MCUX_ACMP |
||||
select HAS_MCUX_SRC_V2 |
||||
select HAS_MCUX_IOMUXC |
||||
select HAS_SWO |
||||
|
||||
config SOC_MIMXRT1166_CM7 |
||||
bool "SOC_MIMXRT1166_CM7" |
||||
select CPU_CORTEX_M7 |
||||
select CPU_CORTEX_M_HAS_DWT |
||||
select SOC_SERIES_IMX_RT11XX |
||||
select HAS_MCUX_CACHE |
||||
select HAS_MCUX |
||||
select HAS_MCUX_SEMC |
||||
select HAS_MCUX_CCM_REV2 |
||||
select HAS_MCUX_IGPIO |
||||
select HAS_MCUX_LPI2C |
||||
select HAS_MCUX_LPSPI |
||||
select HAS_MCUX_LPADC |
||||
select HAS_MCUX_LPUART |
||||
select HAS_MCUX_FLEXSPI |
||||
select HAS_MCUX_GPT |
||||
select HAS_MCUX_FLEXCAN |
||||
select CPU_HAS_ARM_MPU |
||||
select CPU_HAS_ICACHE |
||||
select CPU_HAS_DCACHE |
||||
select INIT_ARM_PLL |
||||
select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER |
||||
select INIT_VIDEO_PLL |
||||
select HAS_MCUX_EDMA |
||||
select CPU_HAS_FPU_DOUBLE_PRECISION |
||||
select BYPASS_LDO_LPSR |
||||
select ADJUST_LDO |
||||
select HAS_MCUX_PWM |
||||
select HAS_MCUX_USDHC1 |
||||
select HAS_MCUX_USDHC2 |
||||
select HAS_MCUX_ENET |
||||
select HAS_MCUX_GPC |
||||
select HAS_MCUX_USB_EHCI |
||||
select HAS_MCUX_SRC_V2 |
||||
select HAS_MCUX_IOMUXC |
||||
select HAS_SWO |
||||
|
||||
|
||||
config SOC_MIMXRT1166_CM4 |
||||
bool "SOC_MIMXRT1166_CM4" |
||||
select CPU_CORTEX_M4 |
||||
select SOC_SERIES_IMX_RT11XX |
||||
select HAS_MCUX_CACHE |
||||
select HAS_MCUX |
||||
select HAS_MCUX_SEMC |
||||
select HAS_MCUX_CCM_REV2 |
||||
select HAS_MCUX_IGPIO |
||||
select HAS_MCUX_LPI2C |
||||
select HAS_MCUX_LPSPI |
||||
select HAS_MCUX_LPUART |
||||
select HAS_MCUX_FLEXSPI |
||||
select HAS_MCUX_GPT |
||||
select CPU_HAS_ARM_MPU |
||||
select CPU_HAS_FPU |
||||
select INIT_ARM_PLL |
||||
select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER |
||||
select INIT_VIDEO_PLL |
||||
select HAS_MCUX_EDMA |
||||
select HAS_MCUX_PWM |
||||
select HAS_MCUX_USDHC1 |
||||
select HAS_MCUX_USDHC2 |
||||
select HAS_MCUX_ENET |
||||
select HAS_MCUX_GPC |
||||
select HAS_MCUX_SRC_V2 |
||||
select HAS_MCUX_IOMUXC |
||||
select HAS_SWO |
||||
|
||||
endchoice |
||||
|
||||
if SOC_SERIES_IMX_RT |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1011CAE4A |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1011DAE5A |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1015CAF4A |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1015DAF5A |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1021CAF4A |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1021CAG4A |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1021DAF5A |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1021DAG5A |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1024CAG4A |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1024DAG5A |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1041DFP6B |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1041DJM6B |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1041XFP5B |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1041XJM5B |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1042DFP6B |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1042DJM6B |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1042XFP5B |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1042XJM5B |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1051CVL5A |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1051DVL6A |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1052CVJ5B |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1052CVL5A |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1052CVL5B |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1052DVJ6B |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1052DVL6A |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1052DVL6B |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1061CVL5A |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1061DVL6A |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1062CVJ5A |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1062CVJ5B |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1062CVL5A |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1062DVJ6A |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1062DVL6A |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1064CVL5A |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1064DVL6A |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1166DVM6A |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1176AVM8A |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1176CVM8A |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1176DVMAA |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1175AVM8A |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1175CVM8A |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1175DVMAA |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1173CVM8A |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1172AVM8A |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1172CVM8A |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1172DVMAA |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1171AVM8A |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1171CVM8A |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT1171DVMAA |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_IMX_RT |
||||
string |
||||
default "MIMXRT1011CAE4A" if SOC_PART_NUMBER_MIMXRT1011CAE4A |
||||
default "MIMXRT1011DAE5A" if SOC_PART_NUMBER_MIMXRT1011DAE5A |
||||
default "MIMXRT1015CAF4A" if SOC_PART_NUMBER_MIMXRT1015CAF4A |
||||
default "MIMXRT1015DAF5A" if SOC_PART_NUMBER_MIMXRT1015DAF5A |
||||
default "MIMXRT1021CAF4A" if SOC_PART_NUMBER_MIMXRT1021CAF4A |
||||
default "MIMXRT1021CAG4A" if SOC_PART_NUMBER_MIMXRT1021CAG4A |
||||
default "MIMXRT1021DAF5A" if SOC_PART_NUMBER_MIMXRT1021DAF5A |
||||
default "MIMXRT1021DAG5A" if SOC_PART_NUMBER_MIMXRT1021DAG5A |
||||
default "MIMXRT1024CAG4A" if SOC_PART_NUMBER_MIMXRT1024CAG4A |
||||
default "MIMXRT1024DAG5A" if SOC_PART_NUMBER_MIMXRT1024DAG5A |
||||
default "MIMXRT1041DFP6B" if SOC_PART_NUMBER_MIMXRT1041DFP6B |
||||
default "MIMXRT1041DJM6B" if SOC_PART_NUMBER_MIMXRT1041DJM6B |
||||
default "MIMXRT1041XFP5B" if SOC_PART_NUMBER_MIMXRT1041XFP5B |
||||
default "MIMXRT1041XJM5B" if SOC_PART_NUMBER_MIMXRT1041XJM5B |
||||
default "MIMXRT1042DFP6B" if SOC_PART_NUMBER_MIMXRT1042DFP6B |
||||
default "MIMXRT1042DJM6B" if SOC_PART_NUMBER_MIMXRT1042DJM6B |
||||
default "MIMXRT1042XFP5B" if SOC_PART_NUMBER_MIMXRT1042XFP5B |
||||
default "MIMXRT1042XJM5B" if SOC_PART_NUMBER_MIMXRT1042XJM5B |
||||
default "MIMXRT1051CVL5A" if SOC_PART_NUMBER_MIMXRT1051CVL5A |
||||
default "MIMXRT1051DVL6A" if SOC_PART_NUMBER_MIMXRT1051DVL6A |
||||
default "MIMXRT1052CVJ5B" if SOC_PART_NUMBER_MIMXRT1052CVJ5B |
||||
default "MIMXRT1052CVL5A" if SOC_PART_NUMBER_MIMXRT1052CVL5A |
||||
default "MIMXRT1052CVL5B" if SOC_PART_NUMBER_MIMXRT1052CVL5B |
||||
default "MIMXRT1052DVJ6B" if SOC_PART_NUMBER_MIMXRT1052DVJ6B |
||||
default "MIMXRT1052DVL6A" if SOC_PART_NUMBER_MIMXRT1052DVL6A |
||||
default "MIMXRT1052DVL6B" if SOC_PART_NUMBER_MIMXRT1052DVL6B |
||||
default "MIMXRT1061CVL5A" if SOC_PART_NUMBER_MIMXRT1061CVL5A |
||||
default "MIMXRT1061DVL6A" if SOC_PART_NUMBER_MIMXRT1061DVL6A |
||||
default "MIMXRT1062CVJ5A" if SOC_PART_NUMBER_MIMXRT1062CVJ5A |
||||
default "MIMXRT1062CVJ5B" if SOC_PART_NUMBER_MIMXRT1062CVJ5B |
||||
default "MIMXRT1062CVL5A" if SOC_PART_NUMBER_MIMXRT1062CVL5A |
||||
default "MIMXRT1062DVJ6A" if SOC_PART_NUMBER_MIMXRT1062DVJ6A |
||||
default "MIMXRT1062DVL6A" if SOC_PART_NUMBER_MIMXRT1062DVL6A |
||||
default "MIMXRT1064CVL5A" if SOC_PART_NUMBER_MIMXRT1064CVL5A |
||||
default "MIMXRT1064DVL6A" if SOC_PART_NUMBER_MIMXRT1064DVL6A |
||||
default "MIMXRT1176AVM8A" if SOC_PART_NUMBER_MIMXRT1176AVM8A |
||||
default "MIMXRT1176CVM8A" if SOC_PART_NUMBER_MIMXRT1176CVM8A |
||||
default "MIMXRT1176DVMAA" if SOC_PART_NUMBER_MIMXRT1176DVMAA |
||||
default "MIMXRT1166DVM6A" if SOC_PART_NUMBER_MIMXRT1166DVM6A |
||||
default "MIMXRT1175AVM8A" if SOC_PART_NUMBER_MIMXRT1175AVM8A |
||||
default "MIMXRT1175CVM8A" if SOC_PART_NUMBER_MIMXRT1175CVM8A |
||||
default "MIMXRT1175DVMAA" if SOC_PART_NUMBER_MIMXRT1175DVMAA |
||||
default "MIMXRT1173CVM8A" if SOC_PART_NUMBER_MIMXRT1173CVM8A |
||||
default "MIMXRT1172AVM8A" if SOC_PART_NUMBER_MIMXRT1172AVM8A |
||||
default "MIMXRT1172CVM8A" if SOC_PART_NUMBER_MIMXRT1172CVM8A |
||||
default "MIMXRT1172DVMAA" if SOC_PART_NUMBER_MIMXRT1172DVMAA |
||||
default "MIMXRT1171AVM8A" if SOC_PART_NUMBER_MIMXRT1171AVM8A |
||||
default "MIMXRT1171CVM8A" if SOC_PART_NUMBER_MIMXRT1171CVM8A |
||||
default "MIMXRT1171DVMAA" if SOC_PART_NUMBER_MIMXRT1171DVMAA |
||||
help |
||||
This string holds the full part number of the SoC. It is a hidden option |
||||
that you should not set directly. The part number selection choice defines |
||||
the default value for this string. |
||||
|
||||
config SOC_SERIES_IMX_RT10XX |
||||
bool "i.MX RT 10XX Series" |
||||
select CPU_CORTEX_M7 |
||||
select CPU_CORTEX_M_HAS_DWT |
||||
select CPU_HAS_ICACHE |
||||
select CPU_HAS_DCACHE |
||||
select PLATFORM_SPECIFIC_INIT |
||||
|
||||
config SOC_SERIES_IMX_RT11XX |
||||
bool "i.MX RT 11XX Series" |
||||
select PLATFORM_SPECIFIC_INIT |
||||
|
||||
config INIT_ARM_PLL |
||||
bool "Initialize ARM PLL" |
||||
|
||||
config INIT_VIDEO_PLL |
||||
bool "Initialize Video PLL" |
||||
|
||||
config INIT_ENET_PLL |
||||
bool |
||||
help |
||||
If y, the Ethernet PLL is initialized. Always enabled on e.g. |
||||
MIMXRT1021 - see commit 17f4d6bec7 ("soc: nxp_imx: fix ENET_PLL selection |
||||
for MIMXRT1021"). |
||||
|
||||
config DCDC_VALUE |
||||
hex "DCDC value for VDD_SOC" |
||||
default 0x13 |
||||
|
||||
config ADJUST_DCDC |
||||
bool "Adjust internal DCDC output" |
||||
default y if SOC_SERIES_IMX_RT11XX |
||||
|
||||
config BYPASS_LDO_LPSR |
||||
bool "Bypass LDO lpsr" |
||||
|
||||
config ADJUST_LDO |
||||
bool "Adjust LDO setting" |
||||
|
||||
config PM_MCUX_GPC |
||||
bool "MCUX general power controller driver" |
||||
|
||||
config PM_MCUX_DCDC |
||||
bool "MCUX dcdc converter module driver" |
||||
|
||||
config PM_MCUX_PMU |
||||
bool "MCUX power management unit driver" |
||||
|
||||
menuconfig NXP_IMX_RT_BOOT_HEADER |
||||
bool "Boot header" |
||||
depends on (!BOOTLOADER_MCUBOOT) && CPU_CORTEX_M7 |
||||
help |
||||
Enable data structures required by the boot ROM to boot the |
||||
application from an external flash device. |
||||
|
||||
if NXP_IMX_RT_BOOT_HEADER |
||||
|
||||
choice BOOT_DEVICE |
||||
prompt "Boot device selection" |
||||
default BOOT_FLEXSPI_NOR |
||||
|
||||
config BOOT_FLEXSPI_NOR |
||||
bool "FlexSPI serial NOR" |
||||
|
||||
config BOOT_FLEXSPI_NAND |
||||
bool "FlexSPI serial NAND" |
||||
|
||||
config BOOT_SEMC_NOR |
||||
bool "SEMC parallel NOR" |
||||
|
||||
config BOOT_SEMC_NAND |
||||
bool "SEMC parallel NAND" |
||||
|
||||
endchoice |
||||
|
||||
config FLEXSPI_CONFIG_BLOCK_OFFSET |
||||
hex "FlexSPI config block offset" |
||||
default 0x0 if BOOT_FLEXSPI_NOR |
||||
help |
||||
FlexSPI configuration block consists of parameters regarding specific |
||||
flash devices including read command sequence, quad mode enablement |
||||
sequence (optional), etc. The boot ROM expects FlexSPI configuration |
||||
parameter to be presented in serial nor flash. |
||||
|
||||
config IMAGE_VECTOR_TABLE_OFFSET |
||||
hex "Image vector table offset" |
||||
default 0x1000 if BOOT_FLEXSPI_NOR || BOOT_SEMC_NOR |
||||
default 0x400 if BOOT_FLEXSPI_NAND || BOOT_SEMC_NAND |
||||
help |
||||
The Image Vector Table (IVT) provides the boot ROM with pointers to |
||||
the application entry point and device configuration data. The boot |
||||
ROM requires a fixed IVT offset for each type of boot device. |
||||
|
||||
config DEVICE_CONFIGURATION_DATA |
||||
bool "Device configuration data" |
||||
help |
||||
Device configuration data (DCD) provides a sequence of commands to |
||||
the boot ROM to initialize components such as an SDRAM. This is |
||||
useful if your application expects components like SDRAM to be |
||||
initialized at boot time. |
||||
|
||||
endif # NXP_IMX_RT_BOOT_HEADER |
||||
|
||||
choice CODE_LOCATION |
||||
prompt "Code location selection" |
||||
default CODE_ITCM |
||||
|
||||
config CODE_SEMC |
||||
bool "Link code into external SEMC-controlled memory" |
||||
imply NXP_IMX_RT_BOOT_HEADER if !BOOTLOADER_MCUBOOT |
||||
|
||||
config CODE_ITCM |
||||
bool "Link code into internal instruction tightly coupled memory (ITCM)" |
||||
imply NXP_IMX_RT_BOOT_HEADER if !BOOTLOADER_MCUBOOT |
||||
|
||||
config CODE_FLEXSPI |
||||
bool "Link code into external FlexSPI-controlled memory" |
||||
imply NXP_IMX_RT_BOOT_HEADER if !BOOTLOADER_MCUBOOT |
||||
|
||||
config CODE_FLEXSPI2 |
||||
bool "Link code into internal FlexSPI-controlled memory" |
||||
imply NXP_IMX_RT_BOOT_HEADER if !BOOTLOADER_MCUBOOT |
||||
|
||||
config CODE_SRAM0 |
||||
bool "Link code into RAM_L memory (RAM_L)" |
||||
imply NXP_IMX_RT_BOOT_HEADER if !BOOTLOADER_MCUBOOT |
||||
|
||||
config CODE_OCRAM |
||||
bool "Link code into OCRAM memory (OCRAM-M4)" |
||||
imply NXP_IMX_RT_BOOT_HEADER if !BOOTLOADER_MCUBOOT |
||||
|
||||
endchoice |
||||
|
||||
config NXP_IMX_EXTERNAL_SDRAM |
||||
bool "Allow access to external SDRAM region" |
||||
help |
||||
Enable access to external SDRAM region managed by the SEMC. This |
||||
setting should be enabled when the application uses SDRAM, or |
||||
an MPU region will be defined to disable cached access to the |
||||
SDRAM memory space. |
||||
|
||||
config NXP_IMX_RT_ROM_RAMLOADER |
||||
depends on !FLASH_MCUX_FLEXSPI_XIP && NXP_IMX_RT_BOOT_HEADER |
||||
# Required so that debugger will load image to correct offset |
||||
select BUILD_OUTPUT_HEX |
||||
bool "Create output image that IMX RT ROM can load from FlexSPI to ram" |
||||
help |
||||
Builds an output image that the IMX RT BootROM can load from the |
||||
FlexSPI boot device into RAM region. The image will be loaded |
||||
from FLEXSPI into the region specified by `zephyr,flash` node. |
||||
|
||||
# Setup LMA adjustment if using the RAMLOADER feature of ROM |
||||
FLASH_CHOSEN := zephyr,flash |
||||
FLASH_BASE := $(dt_chosen_reg_addr_hex,$(FLASH_CHOSEN)) |
||||
FLEXSPI_BASE := $(dt_node_reg_addr_hex,/soc/spi@402a8000,1) |
||||
config BUILD_OUTPUT_ADJUST_LMA |
||||
default "$(FLEXSPI_BASE) - $(FLASH_BASE)" if NXP_IMX_RT_ROM_RAMLOADER |
||||
|
||||
config SECOND_CORE_MCUX |
||||
bool "Dual core operation on the RT11xx series" |
||||
depends on SOC_SERIES_IMX_RT11XX |
||||
help |
||||
Indicates the second core will be enabled, and the part will run |
||||
in dual core mode. Enables dual core operation on the RT11xx series, |
||||
by booting an image targeting the Cortex-M4 from the Cortex-M7 CPU. |
||||
The M4 image will be loaded from flash into RAM based off a |
||||
generated header specifying the VMA and LMA of each memory section |
||||
to load |
||||
|
||||
endif # SOC_SERIES_IMX_RT |
||||
@ -1,15 +0,0 @@
@@ -1,15 +0,0 @@
|
||||
/* |
||||
* Copyright (c) 2019 NXP |
||||
* Copyright (c) 2019 Nordic Semiconductor ASA |
||||
* |
||||
* SPDX-License-Identifier: Apache-2.0 |
||||
*/ |
||||
|
||||
. = CONFIG_FLEXSPI_CONFIG_BLOCK_OFFSET; |
||||
KEEP(*(.boot_hdr.conf)) |
||||
. = CONFIG_IMAGE_VECTOR_TABLE_OFFSET; |
||||
KEEP(*(.boot_hdr.ivt)) |
||||
KEEP(*(.boot_hdr.data)) |
||||
#ifdef CONFIG_DEVICE_CONFIGURATION_DATA |
||||
KEEP(*(.boot_hdr.dcd_data)) |
||||
#endif |
||||
@ -1,15 +0,0 @@
@@ -1,15 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2022, NXP |
||||
* |
||||
* SPDX-License-Identifier: Apache-2.0 |
||||
*/ |
||||
|
||||
#ifndef ZEPHYR_SOC_ARM_NXP_IMX_RT_PINCTRL_SOC_H_ |
||||
#define ZEPHYR_SOC_ARM_NXP_IMX_RT_PINCTRL_SOC_H_ |
||||
#if defined(CONFIG_SOC_SERIES_IMX_RT10XX) |
||||
#include "pinctrl_rt10xx.h" |
||||
#elif defined(CONFIG_SOC_SERIES_IMX_RT11XX) |
||||
#include "pinctrl_rt11xx.h" |
||||
#endif |
||||
|
||||
#endif /* ZEPHYR_SOC_ARM_NXP_IMX_RT_PINCTRL_SOC_H_ */ |
||||
@ -1,32 +0,0 @@
@@ -1,32 +0,0 @@
|
||||
# NXP MIMXRT6XX platform configuration options |
||||
|
||||
# Copyright (c) 2020, NXP |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
|
||||
if SOC_MIMXRT685S_CM33 |
||||
|
||||
config SOC |
||||
default "mimxrt685s_cm33" |
||||
|
||||
config I2S_MCUX_FLEXCOMM |
||||
select INIT_AUDIO_PLL |
||||
|
||||
if MCUX_OS_TIMER |
||||
|
||||
config SYS_CLOCK_HW_CYCLES_PER_SEC |
||||
default 1000000 |
||||
|
||||
endif # MCUX_OS_TIMER |
||||
|
||||
if CORTEX_M_SYSTICK |
||||
|
||||
config SYS_CLOCK_HW_CYCLES_PER_SEC |
||||
default 250105263 |
||||
|
||||
endif # CORTEX_M_SYSTICK |
||||
|
||||
choice USB_MCUX_CONTROLLER_TYPE |
||||
default USB_DC_NXP_LPCIP3511 |
||||
endchoice |
||||
|
||||
endif # SOC_MIMXRT685S_CM33 |
||||
@ -1,17 +0,0 @@
@@ -1,17 +0,0 @@
|
||||
# i.MX RT6XX Series |
||||
|
||||
# Copyright (c) 2020, NXP |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
|
||||
config SOC_SERIES_IMX_RT6XX |
||||
bool "i.MX RT6XX Series Family MCU" |
||||
select ARM |
||||
select CPU_CORTEX_M33 |
||||
select CPU_CORTEX_M_HAS_DWT |
||||
select SOC_FAMILY_IMX |
||||
select CLOCK_CONTROL |
||||
select CODE_DATA_RELOCATION_SRAM if FLASH_MCUX_FLEXSPI_XIP |
||||
select PLATFORM_SPECIFIC_INIT |
||||
select HAS_PM |
||||
help |
||||
Enable support for i.MX RT6XX Series MCU series |
||||
@ -1,136 +0,0 @@
@@ -1,136 +0,0 @@
|
||||
# i.MX RT6XX Series |
||||
|
||||
# Copyright (c) 2020, NXP |
||||
# SPDX-License-Identifier: Apache-2.0 |
||||
|
||||
choice |
||||
prompt "i.MX RT6XX Series MCU Selection" |
||||
depends on SOC_SERIES_IMX_RT6XX |
||||
|
||||
config SOC_MIMXRT685S_CM33 |
||||
bool "SOC_MIMXRT685S M33" |
||||
select CPU_HAS_ARM_SAU |
||||
select CPU_HAS_ARM_MPU |
||||
select CPU_HAS_FPU |
||||
select ARMV8_M_DSP |
||||
select ARM_TRUSTZONE_M |
||||
select CPU_CORTEX_M_HAS_SYSTICK |
||||
select HAS_MCUX |
||||
select HAS_MCUX_SYSCON |
||||
select HAS_MCUX_FLEXCOMM |
||||
select HAS_MCUX_FLEXSPI |
||||
select HAS_MCUX_CACHE |
||||
select HAS_MCUX_LPC_DMA |
||||
select HAS_MCUX_LPADC |
||||
select HAS_MCUX_OS_TIMER |
||||
select HAS_MCUX_LPC_RTC |
||||
select HAS_MCUX_TRNG |
||||
select HAS_MCUX_SCTIMER |
||||
select HAS_MCUX_USDHC1 |
||||
select HAS_MCUX_USDHC2 |
||||
select INIT_SYS_PLL |
||||
select HAS_MCUX_USB_LPCIP3511 |
||||
select HAS_MCUX_CTIMER |
||||
endchoice |
||||
|
||||
if SOC_SERIES_IMX_RT6XX |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT685SFVKB |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT685SFFOB |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_MIMXRT685SFAWBR |
||||
bool |
||||
|
||||
config SOC_PART_NUMBER_IMX_RT6XX |
||||
string |
||||
default "MIMXRT685SFVKB" if SOC_PART_NUMBER_MIMXRT685SFVKB |
||||
default "MIMXRT685SFFOB" if SOC_PART_NUMBER_MIMXRT685SFFOB |
||||
default "MIMXRT685SFAWBR" if SOC_PART_NUMBER_MIMXRT685SFAWBR |
||||
|
||||
help |
||||
This string holds the full part number of the SoC. It is a hidden |
||||
option that you should not set directly. The part number selection |
||||
choice defines the default value for this string. |
||||
|
||||
config INIT_SYS_PLL |
||||
bool "Initialize SYS PLL" |
||||
|
||||
config INIT_AUDIO_PLL |
||||
bool "Initialize Audio PLL" |
||||
|
||||
config XTAL_SYS_CLK_HZ |
||||
int "External oscillator frequency" |
||||
help |
||||
Set the external oscillator frequency in Hz. This should be set by the |
||||
board's defconfig. |
||||
|
||||
config SYSOSC_SETTLING_US |
||||
int "System oscillator settling time" |
||||
help |
||||
Set the board system oscillator settling time in us. This should be set by the |
||||
board's defconfig. |
||||
|
||||
menuconfig NXP_IMX_RT6XX_BOOT_HEADER |
||||
bool "Boot header" |
||||
depends on !BOOTLOADER_MCUBOOT |
||||
help |
||||
Enable data structures required by the boot ROM to boot the |
||||
application from an external flash device. |
||||
|
||||
if NXP_IMX_RT6XX_BOOT_HEADER |
||||
|
||||
choice BOOT_DEVICE |
||||
prompt "Boot device selection" |
||||
default BOOT_FLEXSPI_NOR |
||||
|
||||
config BOOT_FLEXSPI_NOR |
||||
bool "FlexSPI serial NOR" |
||||
|
||||
endchoice |
||||
|
||||
config FLASH_CONFIG_OFFSET |
||||
hex "Flash config data offset" |
||||
default 0x400 |
||||
help |
||||
The flash config offset provides the boot ROM with the on-board |
||||
flash type and parameters. The boot ROM requires a fixed flash config |
||||
offset for FlexSPI device. |
||||
|
||||
config IMAGE_VECTOR_TABLE_OFFSET |
||||
hex "Image vector table offset" |
||||
default 0x1000 |
||||
help |
||||
The Image Vector Table (IVT) provides the boot ROM with pointers to |
||||
the application entry point and device configuration data. The boot |
||||
ROM requires a fixed IVT offset for each type of boot device. |
||||
|
||||
config NXP_IMX_RT_ROM_RAMLOADER |
||||
depends on !FLASH_MCUX_FLEXSPI_XIP |
||||
# Required so that debugger will load image to correct offset |
||||
select BUILD_OUTPUT_HEX |
||||
bool "Create output image that IMX RT ROM can load from FlexSPI to ram" |
||||
help |
||||
Builds an output image that the IMX RT BootROM can load from the |
||||
FlexSPI boot device into RAM region. The image will be loaded |
||||
from FLEXSPI into the region specified by `zephyr,flash` node. |
||||
|
||||
# Setup LMA adjustment if using the RAMLOADER feature of ROM |
||||
FLASH_CHOSEN := zephyr,flash |
||||
FLASH_BASE := $(dt_chosen_reg_addr_hex,$(FLASH_CHOSEN)) |
||||
FLEXSPI_BASE := $(dt_node_reg_addr_hex,/soc/spi@134000,1) |
||||
config BUILD_OUTPUT_ADJUST_LMA |
||||
default "$(FLEXSPI_BASE) - $(FLASH_BASE)" if NXP_IMX_RT_ROM_RAMLOADER |
||||
|
||||
endif # NXP_IMX_RT6XX_BOOT_HEADER |
||||
|
||||
config IMXRT6XX_CODE_CACHE |
||||
bool "Code cache" |
||||
default y |
||||
help |
||||
Enable code cache for FlexSPI region at boot. If this Kconfig is |
||||
cleared, the CACHE64 controller will be disabled during SOC init |
||||
|
||||
endif # SOC_SERIES_IMX_RT6XX |
||||
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Reference in new issue