boards: antmicro: add support for the Myra SiP Baseboard

Add support for the Antmicro's Myra SiP Baseboard. The board uses
Antmicro's Myra SiP which integrates STM32G491XX MCU and its SoC
configuration.

Signed-off-by: Jakub Wasilewski <jwasilewski@internships.antmicro.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>

boards/antmicro/index.rst

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+.. _boards-antmicro:
+
+Antmicro
+###
+
+.. toctree::
+   :maxdepth: 1
+   :glob:
+
+   **/*

boards/antmicro/myra_sip_baseboard/Kconfig.defconfig

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+# Copyright (c) 2024 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_MYRA_SIP_BASEBOARD
+
+config SPI_STM32_INTERRUPT
+	default y
+	depends on SPI
+
+endif # BOARD_MYRA_SIP_BASEBOARD

boards/antmicro/myra_sip_baseboard/Kconfig.myra_sip_baseboard

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+# Copyright (c) 2024 Antmicro
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_MYRA_SIP_BASEBOARD
+	select SOC_MYRA

boards/antmicro/myra_sip_baseboard/board.cmake

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+# Copyright (c) 2024 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+set(SUPPORTED_EMU_PLATFORMS renode)
+set(RENODE_SCRIPT ${CMAKE_CURRENT_LIST_DIR}/support/myra_sip_baseboard.resc)
+set(RENODE_UART sysbus.lpuart1)
+
+board_runner_args(openocd "--config=${BOARD_DIR}/support/openocd_myra_sip_baseboard.cfg")
+
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)

boards/antmicro/myra_sip_baseboard/board.yml

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+board:
+  name: myra_sip_baseboard
+  full_name: Myra SiP Baseboard
+  vendor: antmicro
+  socs:
+    - name: myra

boards/antmicro/myra_sip_baseboard/doc/index.rst

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+.. zephyr:board:: myra_sip_baseboard
+
+Overview
+********
+
+The Myra SiP Baseboard features Antmicro's **Myra** SiP, which integrates the **STM32G491REI6** MCU,
+128kB FRAM, and FTDI FT231XQ USB to UART converter. The board is equipped with temperature,
+humidity, and pressure sensors, designed to help monitor conditions in server rooms.
+
+The sensors are placed on a separate island that is detachable from the main PCB and can be
+installed directly in the required place. It provides local storage for data logging and a battery
+backup for protection against data loss. The board can be used as a building block for PoC solutions
+for monitoring environmental parameters.
+
+Key features include:
+
+- STM32G491REI6 MCU (Cortex-M4, 170 MHz)
+- 128 KB Fujitsu FRAM
+- FTDI FT231XQ USB to UART converter
+- 50 mm x 26.5 mm PCB
+- USB-C Connector for data and power
+- SHT45 temperature + humidity sensor
+- BME280 temperature + humidity + pressure sensor
+- QWIIC connectors for peripheral expansion
+- RTC with battery backup
+
+More information about the board can be found on `Antmicro's Open Hardware Portal <https://openhardware.antmicro.com/boards/environment-sensor-sip-baseboard>`_.
+
+Hardware
+********
+
+Myra SiP provides the following hardware:
+
+- **STM32G491REI6 MCU**:
+
+  - ARM Cortex-M4 CPU with FPU, up to 170 MHz
+  - Clock Sources:
+
+    - 4 to 48 MHz external crystal oscillator (HSE)
+    - 32 kHz crystal oscillator for RTC (LSE)
+    - Internal 16 MHz RC (±1%)
+    - Internal low-power 32 kHz RC (±5%)
+    - 2 PLLs for system clock, USB, audio, ADC
+  - RTC: Real-time clock with hardware calendar, alarms, and calibration
+  - Timers:
+
+    - 1x 32-bit timer and 2x 16-bit timers with up to 4x IC/OC/PWM or pulse counter and quadrature
+      (incremental) encoder input
+    - 3x 16-bit advanced motor control timers with up to 8x PWM channels, dead time generation,
+      emergency stop
+    - 1x 16-bit timer with 2x IC/OC, one OCN/PWM, dead time generation, emergency stop
+    - 2x watchdog timers (independent, window)
+    - 2x 16-bit basic timers
+    - SysTick timer
+    - 1x low-power timer
+  - I/Os: Up to 86 fast I/Os, most 5V tolerant
+  - Memory:
+
+    - 512 KB Flash memory with ECC and PCROP protection
+    - 96 KB SRAM including 32 KB with hardware parity check
+  - Analog peripherals:
+
+    - 3x 16-bit ADCs with up to 36 channels, hardware oversampling, and resolution up to 16-bit
+    - 4x 12-bit DAC channels
+    - 4x ultra-fast rail-to-rail analog comparators
+    - 4x operational amplifiers with built-in PGA
+    - Internal temperature sensor and voltage reference with support for three output voltages
+      (2.048 V, 2.5 V, 2.9 V)
+  - Communication Interfaces:
+
+    - 2x FDCAN controllers supporting flexible data rate
+    - 3x I2C Fast Mode Plus (1 Mbit/s) with 20 mA current sink, SMBus/PMBus support
+    - 5x USART/UART (ISO 7816, LIN, IrDA, modem control)
+    - 1x LPUART
+    - 3x SPI interfaces (2x with multiplexed half-duplex I²S)
+    - 1x SAI (serial audio interface)
+    - USB 2.0 full-speed with LPM and BCD support
+    - IRTIM (infrared interface)
+    - USB Type-C™ / USB Power Delivery (UCPD)
+  - Other Peripherals:
+
+    - 16-channel DMA controller
+    - True Random Number Generator (RNG)
+    - CRC calculation unit, 96-bit unique ID
+    - Development support: SWD, JTAG, Embedded Trace Macrocell™
+    - ECOPACK2® compliant packages
+
+- **128 KB Fujitsu MB85RS1MT FRAM**: Local storage for data logging, allowing non-volatile memory storage.
+
+- **FTDI FT231XQ USB to UART converter**: Provides a reliable USB to UART interface.
+
+
+More information about STM32G491RE can be found here:
+
+- `STM32G491RE on www.st.com`_
+
+Other board's peripherals:
+--------------------------
+
+- USB-C Connector: For data and power.
+- SHT45 sensor:
+
+  - Relative humidity accuracy: ±1.0% RH
+  - Operating humidity range: 0-100% RH
+  - Temperature accuracy: ±0.1°C
+  - Operating temperature range: -40°C to 125°C
+- BME280 sensor:
+
+  - Relative humidity accuracy: ±3% RH
+  - Temperature accuracy: ±1°C
+  - Pressure accuracy: ±1 hPa
+  - Operating temperature range: -40°C to 85°C
+  - Pressure range: 300-1100 hPa
+- QWIIC connectors: For easy peripheral expansion.
+
+Supported Features
+------------------
+
+The Zephyr ``myra_sip_baseboard`` board target supports the following hardware features:
+
++-----------+------------+-------------------------------------+
+| Interface | Controller | Driver/Component                    |
++===========+============+=====================================+
+| NVIC      | on-chip    | nested vector interrupt controller  |
++-----------+------------+-------------------------------------+
+| UART      | on-chip    | serial port-polling; serial         |
+|           |            | port-interrupt                      |
++-----------+------------+-------------------------------------+
+| PINMUX    | on-chip    | pinmux                              |
++-----------+------------+-------------------------------------+
+| GPIO      | on-chip    | gpio                                |
++-----------+------------+-------------------------------------+
+| I2C       | on-chip    | i2c                                 |
++-----------+------------+-------------------------------------+
+| WATCHDOG  | on-chip    | independent watchdog                |
++-----------+------------+-------------------------------------+
+| PWM       | on-chip    | pwm                                 |
++-----------+------------+-------------------------------------+
+| ADC       | on-chip    | adc                                 |
++-----------+------------+-------------------------------------+
+| DAC       | on-chip    | dac controller                      |
++-----------+------------+-------------------------------------+
+| FLASH     | on-chip    | flash memory                        |
++-----------+------------+-------------------------------------+
+| EEPROM    | on-chip    | eeprom                              |
++-----------+------------+-------------------------------------+
+| NVS       | on-chip    | nvs                                 |
++-----------+------------+-------------------------------------+
+| COUNTER   | on-chip    | rtc                                 |
++-----------+------------+-------------------------------------+
+| SPI       | on-chip    | spi                                 |
++-----------+------------+-------------------------------------+
+| die-temp  | on-chip    | die temperature sensor              |
++-----------+------------+-------------------------------------+
+| FDCAN1    | on-chip    | can controller                      |
++-----------+------------+-------------------------------------+
+| RTC       | on-chip    | rtc                                 |
++-----------+------------+-------------------------------------+
+
+Other hardware features are not yet supported on this Zephyr port.
+
+Connections and IOs
+-------------------
+
+Antmicro's Myra SiP Baseboard provides the following default pin mappings for peripherals:
+
+.. rst-class:: rst-columns
+
+- LPUART_1_TX : PA2
+- LPUART_1_RX : PA3
+- I2C_1_SCL : PB8
+- I2C_1_SDA : PB9
+- SPI_CS2 : PB2
+- SPI_CS3 : PA7
+- SPI_2_SCK : PB13
+- SPI_2_MISO : PB14
+- SPI_2_MOSI : PB15
+- PWM_2_CH1 : PA5
+- USER_PB : PC13
+- LD2 : PA5
+- ADC1_IN1 : PA0
+- DAC1_OUT1 : PA4
+- USB_MCU_N : PA11
+- USB_MCU_P : PA12
+- SWDIO-JMTS : PA13
+- SWCLK-JTCK : PA14
+- JTDI : PA15
+- JTDO : PB3
+- JTRST : PB4
+- FRAM_HOLD (ACTIVE LOW) : PB10
+- FRAM_WP (ACTIVE LOW) : PB11
+- FRAM_CS (ACTIVE LOW) : PB12
+- GPIO_PC10 : PC10
+- GPIO_PC11 : PC11
+- GPIO_PC12 : PC12
+- PF0_OSC : PF0
+
+System Clock
+------------
+
+System clock can be driven by an internal or an external oscillator, as well as by the main PLL
+clock. By default, system clock is driven by PLL clock at 170MHz (boost mode selected), which in
+turn, is driven by the 8MHz high speed external oscillator (HSE). While the HSE oscillator is
+capable of operating at frequencies up to 48 MHz by default, in this configuration, it is
+specifically set to 8 MHz.
+
+Serial Port
+-----------
+
+The Myra SiP Baseboard has 5 U(S)ARTs. The Zephyr console output is assigned to LPUART1. The default
+settings are 115200 8N1.
+
+Programming and Debugging
+*************************
+
+Applications for the ``myra_sip_baseboard`` board target can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details).
+
+Flashing
+********
+
+This board has a USB-JTAG interface and can be used with OpenOCD.
+
+Connect the Myra SiP Baseboard to your host computer using the USB port, then build and flash
+the application. Here is an example for :zephyr:code-sample:`hello_world`.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: myra_sip_baseboard
+   :goals: build flash
+
+Then run a serial host program to connect with the Myra SiP Baseboard, e.g. using picocom:
+
+.. code-block:: console
+
+   $ picocom /dev/ttyUSB0 -b 115200
+
+.. warning::
+   The board has only one port that is used for both programming and the console. For this reason, it is
+   recommended to set ``CONFIG_BOOT_DELAY`` to an arbitrary value. This is especially important when
+   running twister tests on the device. You should then also use the ``--flash-before`` and
+   ``--device-flash-timeout=120`` options:
+
+   .. code-block:: console
+
+       $ scripts/twister --device-testing --device-serial /dev/ttyUSB0 --device-serial-baud 115200 -p myra_sip_baseboard --flash-before --device-flash-timeout=120 -v
+
+Debugging
+*********
+
+You can debug an application in the usual way. Here is an example for the
+:zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: myra_sip_baseboard
+   :maybe-skip-config:
+   :goals: debug
+
+.. _STM32G491RE on www.st.com:
+   https://www.st.com/en/microcontrollers-microprocessors/stm32g491re.html

boards/antmicro/myra_sip_baseboard/myra_sip_baseboard.dts

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+/*
+ * Copyright (c) 2024 Antmicro <www.antmicro.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+#include <antmicro/myra.dtsi>
+
+/ {
+	compatible = "antmicro,myra-sip-baseboard";
+	model = "Myra SiP Baseboard";
+
+	chosen {
+		zephyr,console = &lpuart1;
+		zephyr,shell-uart = &lpuart1;
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+		zephyr,canbus = &fdcan1;
+		zephyr,code-partition = &slot0_partition;
+	};
+
+	leds: leds {
+		compatible = "gpio-leds";
+		green_led: led_0 {
+			gpios = <&gpioa 5 GPIO_ACTIVE_HIGH>;
+			label = "User LD2";
+		};
+	};
+
+	pwmleds {
+		compatible = "pwm-leds";
+
+		green_pwm_led: green_pwm_led {
+			pwms = <&pwm2 1 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		user_button: button {
+			label = "User";
+			gpios = <&gpioc 13 GPIO_ACTIVE_LOW>;
+			zephyr,code = <INPUT_KEY_0>;
+		};
+	};
+
+	aliases {
+		led0 = &green_led;
+		mcuboot-led0 = &green_led;
+		pwm-led0 = &green_pwm_led;
+		sw0 = &user_button;
+		watchdog0 = &iwdg;
+		volt-sensor0 = &vref;
+		volt-sensor1 = &vbat;
+		rtc = &rtc;
+	};
+};
+
+&clk_lse {
+	status = "okay";
+};
+
+&clk_lsi {
+	status = "okay";
+};
+
+&clk_hsi48 {
+	status = "okay";
+};
+
+&clk_hse {
+	clock-frequency = <DT_FREQ_M(8)>;
+	status = "okay";
+};
+
+&pll {
+	div-m = <2>;
+	mul-n = <85>;
+	div-p = <7>;
+	div-q = <2>;
+	div-r = <2>;
+	clocks = <&clk_hse>;
+	status = "okay";
+};
+
+&rcc {
+	clocks = <&pll>;
+	clock-frequency = <DT_FREQ_M(170)>;
+	ahb-prescaler = <1>;
+	apb1-prescaler = <1>;
+	apb2-prescaler = <1>;
+};
+
+&lpuart1 {
+	pinctrl-0 = <&lpuart1_tx_pa2 &lpuart1_rx_pa3>;
+	pinctrl-1 = <&analog_pa2 &analog_pa3>;
+	pinctrl-names = "default", "sleep";
+	current-speed = <115200>;
+	status = "okay";
+};
+
+&i2c1 {
+	pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	bme280@76 {
+		compatible = "bosch,bme280";
+		reg = <0x76>;
+	};
+
+	sht4x@44 {
+		compatible = "sensirion,sht4x";
+		repeatability = <2>;
+		reg = <0x44>;
+	};
+};
+
+&timers2 {
+	status = "okay";
+
+	pwm2: pwm {
+		status = "okay";
+		pinctrl-0 = <&tim2_ch1_pa5>;
+		pinctrl-names = "default";
+	};
+};
+
+stm32_lp_tick_source: &lptim1 {
+	clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>,
+		<&rcc STM32_SRC_LSI LPTIM1_SEL(1)>;
+	status = "okay";
+};
+
+&rtc {
+	clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000400>,
+		 <&rcc STM32_SRC_LSE RTC_SEL(1)>;
+	status = "okay";
+};
+
+&flash0 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		boot_partition: partition@0 {
+			label = "mcuboot";
+			reg = <0x00000000 DT_SIZE_K(34)>;
+		};
+		slot0_partition: partition@8800 {
+			label = "image-0";
+			reg = <0x00008800 DT_SIZE_K(240)>;
+		};
+		slot1_partition: partition@44800 {
+			label = "image-1";
+			reg = <0x00044800 DT_SIZE_K(234)>;
+		};
+		/* Set 4Kb of storage at the end of the 512Kb of flash */
+		storage_partition: partition@7f000 {
+			label = "storage";
+			reg = <0x0007f000 DT_SIZE_K(4)>;
+		};
+	};
+};
+
+&iwdg {
+	status = "okay";
+};
+
+&rng {
+	status = "okay";
+};
+
+&adc1 {
+	pinctrl-0 = <&adc1_in1_pa0>;
+	pinctrl-names = "default";
+	st,adc-clock-source = "SYNC";
+	st,adc-prescaler = <4>;
+	status = "okay";
+};
+
+&die_temp {
+	status = "okay";
+};
+
+&dac1 {
+	pinctrl-0 = <&dac1_out1_pa4>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&fdcan1 {
+	clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>,
+		 <&rcc STM32_SRC_HSE FDCAN_SEL(0)>;
+	pinctrl-0 = <&fdcan1_rx_pa11 &fdcan1_tx_pa12>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&vref {
+	status = "okay";
+};
+
+&vbat {
+	status = "okay";
+};
+
+&timers6 {
+	status = "okay";
+	st,prescaler = <1>;
+};
+
+&timers7 {
+	status = "okay";
+	st,prescaler = <1>;
+};

boards/antmicro/myra_sip_baseboard/myra_sip_baseboard.yaml

@@ -0,0 +1,27 @@
+identifier: myra_sip_baseboard
+name: Myra SiP Baseboard
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gnuarmemb
+ram: 128
+flash: 512
+supported:
+  - nvs
+  - pwm
+  - i2c
+  - gpio
+  - usb device
+  - spi
+  - watchdog
+  - dma
+  - can
+  - rtc
+  - sensors
+testing:
+  timeout_multiplier: 3
+  renode:
+    uart: sysbus.lpuart1
+    resc: boards/antmicro/myra_sip_baseboard/support/myra_sip_baseboard.resc
+vendor: antmicro

boards/antmicro/myra_sip_baseboard/myra_sip_baseboard_defconfig

@@ -0,0 +1,10 @@
+# Copyright (c) 2024 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SERIAL=y
+CONFIG_GPIO=y
+CONFIG_CLOCK_CONTROL=y
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_ARM_MPU=y
+CONFIG_HW_STACK_PROTECTION=y

boards/antmicro/myra_sip_baseboard/support/myra_sip_baseboard.repl

@@ -0,0 +1,87 @@
+flash0: Memory.MappedMemory @ sysbus 0x8000000
+    size: 0x80000
+
+sram0: Memory.MappedMemory @ sysbus 0x20000000
+    size: 0x1c000
+
+timers2: Timers.STM32_Timer @ sysbus <0x40000000, +0x400>
+    frequency: 10000000
+    initialLimit: 0xffffffff
+    ->nvic0@28
+
+timers6: Timers.STM32_Timer @ sysbus <0x40001000, +0x400>
+    frequency: 10000000
+    initialLimit: 0xffffffff
+    ->nvic0@54
+
+timers7: Timers.STM32_Timer @ sysbus <0x40001400, +0x400>
+    frequency: 10000000
+    initialLimit: 0xffffffff
+    ->nvic0@55
+
+clk_lse: Python.PythonPeripheral @ sysbus 0x40007000
+    size: 0x4
+    initable: true
+    filename: "scripts/pydev/rolling-bit.py"
+
+gpioa: GPIOPort.STM32_GPIOPort @ sysbus <0x48000000, +0x400>
+
+gpiob: GPIOPort.STM32_GPIOPort @ sysbus <0x48000400, +0x400>
+
+gpioc: GPIOPort.STM32_GPIOPort @ sysbus <0x48000800, +0x400>
+
+gpiod: GPIOPort.STM32_GPIOPort @ sysbus <0x48000c00, +0x400>
+
+gpioe: GPIOPort.STM32_GPIOPort @ sysbus <0x48001000, +0x400>
+
+gpiof: GPIOPort.STM32_GPIOPort @ sysbus <0x48001400, +0x400>
+
+gpiog: GPIOPort.STM32_GPIOPort @ sysbus <0x48001800, +0x400>
+
+greenled: Miscellaneous.LED @ gpioa 0x5
+
+gpioa:
+    5 -> greenled@0
+
+nvic0: IRQControllers.NVIC @ {
+    sysbus new Bus.BusPointRegistration { address: 0xe000e000; cpu: cpu0 }
+}
+    -> cpu0@0
+
+cpu0: CPU.CortexM @ sysbus
+    cpuType: "cortex-m4f"
+    nvic: nvic0
+
+i2c1: I2C.STM32F7_I2C @ sysbus 0x40005400
+    EventInterrupt->nvic0@31
+    ErrorInterrupt->nvic0@32
+
+sht4x: I2C.SHT45 @ i2c1 0x44
+
+adc1: Analog.STM32_ADC @ sysbus 0x50000000
+    IRQ->nvic0@18
+
+lpuart1: UART.STM32F7_USART @ sysbus 0x40008000
+    frequency: 200000000
+    lowPowerMode: true
+    IRQ->nvic0@91
+
+rcc: Python.PythonPeripheral @ sysbus 0x40021000
+    size: 0x400
+    initable: true
+    filename: "scripts/pydev/flipflop.py"
+
+rng: Miscellaneous.STM32F4_RNG @ sysbus 0x50060800
+    ->nvic0@90
+
+rtc: Timers.STM32F4_RTC @ sysbus 0x40002800
+    AlarmIRQ->nvic0@41
+
+spi2: SPI.STM32SPI @ sysbus 0x40003800
+    IRQ->nvic0@36
+
+iwdg: Timers.STM32_IndependentWatchdog @ sysbus 0x40003000
+    frequency: 32000
+
+dwt: Miscellaneous.DWT @ sysbus 0xE0001000
+    frequency: 72000000

boards/antmicro/myra_sip_baseboard/support/myra_sip_baseboard.resc

@@ -0,0 +1,17 @@
+:name: Myra SiP Baseboard
+:description: This script is prepared to run Zephyr on the Myra SiP Baseboard.
+
+$name?="Myra SiP Baseboard"
+
+using sysbus
+mach create $name
+machine LoadPlatformDescription $ORIGIN/myra_sip_baseboard.repl
+
+showAnalyzer lpuart1
+
+macro reset
+"""
+    sysbus LoadELF $elf
+    cpu0 VectorTableOffset `sysbus GetSymbolAddress "_vector_table"`
+"""
+runMacro $reset

boards/antmicro/myra_sip_baseboard/support/openocd_myra_sip_baseboard.cfg

@@ -0,0 +1,13 @@
+adapter driver ft232r
+adapter speed 1000
+
+ft232r vid_pid 0x0403 0x6015
+ft232r tck_num RTS
+ft232r tms_num DTR
+ft232r tdi_num RI
+ft232r tdo_num CTS
+ft232r trst_num DSR
+ft232r srst_num DCD
+
+ft232r restore_serial 0x0015
+source [find target/stm32g4x.cfg]

dts/arm/antmicro/myra.dtsi

@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2024 Antmicro <www.antmicro.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/g4/stm32g491Xe.dtsi>
+#include <st/g4/stm32g491r(c-e)tx-pinctrl.dtsi>
+#include <mem.h>
+#include <freq.h>
+
+&spi2 {
+	pinctrl-0 = <&spi2_nss_pb12 &spi2_sck_pb13
+		     &spi2_miso_pb14 &spi2_mosi_pb15>;
+	pinctrl-names = "default";
+	status = "okay";
+};

dts/bindings/vendor-prefixes.txt

@@ -57,6 +57,7 @@ ams	AMS AG
 amstaos	AMS-Taos Inc.
 analogix	Analogix Semiconductor, Inc.
 andestech	Andes Technology Corporation
+antmicro	Antmicro
 anvo	Anvo-Systems Dresden GmbH
 aosong	Guangzhou Aosong Electronic Co., Ltd.
 ap	Angst+Pfister

soc/antmicro/myra/Kconfig

@@ -0,0 +1,5 @@
+# Copyright (c) 2024 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_MYRA
+	select SOC_STM32G491XX

soc/antmicro/myra/Kconfig.soc

@@ -0,0 +1,18 @@
+# Copyright (c) 2024 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+# The Myra is technically a SiP (System-in-Package) that consists of
+# the STM32G491REI6 MCU and additional components like FRAM. So for
+# Antmicro Myra SiP Baseboard the STM32G491XX SoC is to be indicated as
+# the build target, but since the Myra SiP is what a user can actually
+# see on a board, using only STM32G491XX in the Zephyr build
+# infrastructure might be confusing. That's why in the top level of SoC
+# definitions (for user-configurable options in Kconfig, for example)
+# the Myra term is used and STM32G491XX underneath.
+config SOC_MYRA
+	bool
+	help
+	  Antmicro Myra System-in-Package
+
+config SOC
+	default "myra" if SOC_MYRA

soc/antmicro/myra/soc.yml

@@ -0,0 +1,2 @@
+socs:
+  - name: myra