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dts: bindings: clock: Change clock control binding for Renesas RA 

Background of this modification is to make clock control
driver code provided by Renesas vendor to support for Renesas MCU
on Zephyr.

Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>
pull/71174/head
Quy Tran 1 year ago committed by Anas Nashif
parent
516794843d
commit
370bd31d2a
47 changed files with 115 additions and 112 deletions
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  1. 2
      boards/renesas/ek_ra6e2/doc/index.rst
  2. 1
      boards/renesas/ek_ra6e2/ek_ra6e2.dts
  3. 1
      boards/renesas/ek_ra6e2/ek_ra6e2_defconfig
  4. 2
      boards/renesas/ek_ra6m1/doc/index.rst
  5. 1
      boards/renesas/ek_ra6m1/ek_ra6m1_defconfig
  6. 2
      boards/renesas/ek_ra6m2/doc/index.rst
  7. 6
      boards/renesas/ek_ra6m2/ek_ra6m2.dts
  8. 1
      boards/renesas/ek_ra6m2/ek_ra6m2_defconfig
  9. 2
      boards/renesas/ek_ra6m3/doc/index.rst
  10. 1
      boards/renesas/ek_ra6m3/ek_ra6m3.dts
  11. 1
      boards/renesas/ek_ra6m3/ek_ra6m3_defconfig
  12. 2
      boards/renesas/ek_ra6m4/doc/index.rst
  13. 1
      boards/renesas/ek_ra6m4/ek_ra6m4.dts
  14. 1
      boards/renesas/ek_ra6m4/ek_ra6m4_defconfig
  15. 2
      boards/renesas/ek_ra6m5/doc/index.rst
  16. 1
      boards/renesas/ek_ra6m5/ek_ra6m5.dts
  17. 1
      boards/renesas/ek_ra6m5/ek_ra6m5_defconfig
  18. 1
      boards/renesas/fpb_ra6e1/fpb_ra6e1.dts
  19. 2
      boards/renesas/fpb_ra6e1/fpb_ra6e1_defconfig
  20. 6
      boards/renesas/fpb_ra6e2/fpb_ra6e2.dts
  21. 1
      boards/renesas/fpb_ra6e2/fpb_ra6e2_defconfig
  22. 2
      drivers/clock_control/Kconfig
  23. 0
      drivers/clock_control/Kconfig.renesas_ra_cgc
  24. 2
      drivers/clock_control/clock_control_renesas_ra_cgc.c
  25. 1
      dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi
  26. 1
      dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi
  27. 48
      dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi
  28. 46
      dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi
  29. 48
      dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi
  30. 4
      dts/bindings/clock/renesas,ra-cgc-busclk.yaml
  31. 4
      dts/bindings/clock/renesas,ra-cgc-external-clock.yaml
  32. 4
      dts/bindings/clock/renesas,ra-cgc-pclk-block.yaml
  33. 4
      dts/bindings/clock/renesas,ra-cgc-pclk.yaml
  34. 6
      dts/bindings/clock/renesas,ra-cgc-pll.yaml
  35. 4
      dts/bindings/clock/renesas,ra-cgc-subclk.yaml
  36. 1
      soc/renesas/ra/ra6e1/Kconfig
  37. 2
      soc/renesas/ra/ra6e1/soc.c
  38. 1
      soc/renesas/ra/ra6e2/Kconfig
  39. 2
      soc/renesas/ra/ra6e2/soc.c
  40. 1
      soc/renesas/ra/ra6m1/Kconfig
  41. 1
      soc/renesas/ra/ra6m1/soc.c
  42. 1
      soc/renesas/ra/ra6m2/Kconfig
  43. 1
      soc/renesas/ra/ra6m2/soc.c
  44. 1
      soc/renesas/ra/ra6m3/Kconfig
  45. 1
      soc/renesas/ra/ra6m3/soc.c
  46. 1
      soc/renesas/ra/ra6m5/Kconfig
  47. 2
      soc/renesas/ra/ra6m5/soc.c

2
boards/renesas/ek_ra6e2/doc/index.rst
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@ -96,6 +96,8 @@ The below features are currently supported on Zephyr OS for EK-RA6E2 board: @@ -96,6 +96,8 @@ The below features are currently supported on Zephyr OS for EK-RA6E2 board:
+-----------+------------+----------------------+
| UART | on-chip | serial |
+-----------+------------+----------------------+
| CLOCK | on-chip | clock control |
+-----------+------------+----------------------+
Other hardware features are currently not supported by the port.

1
boards/renesas/ek_ra6e2/ek_ra6e2.dts
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@ -97,6 +97,5 @@ @@ -97,6 +97,5 @@
source = <RA_PLL_SOURCE_MAIN_OSC>;
div = <RA_PLL_DIV_1>;
mul = <10 0>;
freq = <DT_FREQ_M(200)>;
status = "okay";
};

1
boards/renesas/ek_ra6e2/ek_ra6e2_defconfig
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@ -15,3 +15,4 @@ CONFIG_CONSOLE=y @@ -15,3 +15,4 @@ CONFIG_CONSOLE=y
CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_BUILD_NO_GAP_FILL=y
CONFIG_CLOCK_CONTROL=y

2
boards/renesas/ek_ra6m1/doc/index.rst
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@ -92,6 +92,8 @@ The below features are currently supported on Zephyr OS for EK-RA6M1 board: @@ -92,6 +92,8 @@ The below features are currently supported on Zephyr OS for EK-RA6M1 board:
+-----------+------------+----------------------+
| UART | on-chip | serial |
+-----------+------------+----------------------+
| CLOCK | on-chip | clock control |
+-----------+------------+----------------------+
Other hardware features are currently not supported by the port.

1
boards/renesas/ek_ra6m1/ek_ra6m1_defconfig
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@ -9,6 +9,7 @@ CONFIG_PINCTRL=y @@ -9,6 +9,7 @@ CONFIG_PINCTRL=y
CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_BUILD_NO_GAP_FILL=y
CONFIG_CLOCK_CONTROL=y
# Enable Console
CONFIG_SERIAL=y

2
boards/renesas/ek_ra6m2/doc/index.rst
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@ -86,6 +86,8 @@ The below features are currently supported on Zephyr OS for EK-RA6M2 board: @@ -86,6 +86,8 @@ The below features are currently supported on Zephyr OS for EK-RA6M2 board:
+-----------+------------+----------------------+
| UART | on-chip | serial |
+-----------+------------+----------------------+
| CLOCK | on-chip | clock control |
+-----------+------------+----------------------+
Other hardware features are currently not supported by the port.

6
boards/renesas/ek_ra6m2/ek_ra6m2.dts
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@ -65,9 +65,3 @@ @@ -65,9 +65,3 @@
mul = <20 0>;
status = "okay";
};
&pclka {
clk_src = <RA_CLOCK_SOURCE_PLL>;
clk_div = <RA_SCI_CLOCK_DIV_2>;
status = "okay";
};

1
boards/renesas/ek_ra6m2/ek_ra6m2_defconfig
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@ -9,6 +9,7 @@ CONFIG_PINCTRL=y @@ -9,6 +9,7 @@ CONFIG_PINCTRL=y
CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_BUILD_NO_GAP_FILL=y
CONFIG_CLOCK_CONTROL=y
# Enable Console
CONFIG_SERIAL=y

2
boards/renesas/ek_ra6m3/doc/index.rst
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@ -94,6 +94,8 @@ The below features are currently supported on Zephyr OS for EK-RA6M3 board: @@ -94,6 +94,8 @@ The below features are currently supported on Zephyr OS for EK-RA6M3 board:
+-----------+------------+----------------------+
| UART | on-chip | serial |
+-----------+------------+----------------------+
| CLOCK | on-chip | clock control |
+-----------+------------+----------------------+
Other hardware features are currently not supported by the port.

1
boards/renesas/ek_ra6m3/ek_ra6m3.dts
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@ -75,6 +75,5 @@ @@ -75,6 +75,5 @@
source = <RA_PLL_SOURCE_MAIN_OSC>;
div = <RA_PLL_DIV_2>;
mul = <20 0>;
freq = <DT_FREQ_M(240)>;
status = "okay";
};

1
boards/renesas/ek_ra6m3/ek_ra6m3_defconfig
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@ -15,3 +15,4 @@ CONFIG_UART_CONSOLE=y @@ -15,3 +15,4 @@ CONFIG_UART_CONSOLE=y
CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_BUILD_NO_GAP_FILL=y
CONFIG_CLOCK_CONTROL=y

2
boards/renesas/ek_ra6m4/doc/index.rst
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@ -99,6 +99,8 @@ The below features are currently supported on Zephyr OS for EK-RA6M4 board: @@ -99,6 +99,8 @@ The below features are currently supported on Zephyr OS for EK-RA6M4 board:
+-----------+------------+----------------------+
| UART | on-chip | serial |
+-----------+------------+----------------------+
| CLOCK | on-chip | clock control |
+-----------+------------+----------------------+
Other hardware features are currently not supported by the port.

1
boards/renesas/ek_ra6m4/ek_ra6m4.dts
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@ -71,7 +71,6 @@ @@ -71,7 +71,6 @@
source = <RA_PLL_SOURCE_MAIN_OSC>;
div = <RA_PLL_DIV_3>;
mul = <25 0>;
freq = <DT_FREQ_M(200)>;
status = "okay";
};

1
boards/renesas/ek_ra6m4/ek_ra6m4_defconfig
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@ -15,3 +15,4 @@ CONFIG_UART_CONSOLE=y @@ -15,3 +15,4 @@ CONFIG_UART_CONSOLE=y
CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_BUILD_NO_GAP_FILL=y
CONFIG_CLOCK_CONTROL=y

2
boards/renesas/ek_ra6m5/doc/index.rst
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@ -97,6 +97,8 @@ The below features are currently supported on Zephyr OS for EK-RA6M5 board: @@ -97,6 +97,8 @@ The below features are currently supported on Zephyr OS for EK-RA6M5 board:
+-----------+------------+----------------------+
| UART | on-chip | serial |
+-----------+------------+----------------------+
| CLOCK | on-chip | clock control |
+-----------+------------+----------------------+
Other hardware features are currently not supported by the port.

1
boards/renesas/ek_ra6m5/ek_ra6m5.dts
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@ -71,6 +71,5 @@ @@ -71,6 +71,5 @@
source = <RA_PLL_SOURCE_MAIN_OSC>;
div = <RA_PLL_DIV_3>;
mul = <25 0>;
freq = <DT_FREQ_M(200)>;
status = "okay";
};

1
boards/renesas/ek_ra6m5/ek_ra6m5_defconfig
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@ -9,6 +9,7 @@ CONFIG_PINCTRL=y @@ -9,6 +9,7 @@ CONFIG_PINCTRL=y
CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_BUILD_NO_GAP_FILL=y
CONFIG_CLOCK_CONTROL=y
# Enable Console
CONFIG_SERIAL=y

1
boards/renesas/fpb_ra6e1/fpb_ra6e1.dts
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@ -60,7 +60,6 @@ @@ -60,7 +60,6 @@
source = <RA_PLL_SOURCE_HOCO>;
div = <RA_PLL_DIV_2>;
mul = <20 0>;
freq = <DT_FREQ_M(200)>;
status = "okay";
};

2
boards/renesas/fpb_ra6e1/fpb_ra6e1_defconfig
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@ -15,3 +15,5 @@ CONFIG_SERIAL=y @@ -15,3 +15,5 @@ CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_UART_CONSOLE=y
CONFIG_CONSOLE=y
CONFIG_CLOCK_CONTROL=y

6
boards/renesas/fpb_ra6e2/fpb_ra6e2.dts
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@ -81,9 +81,3 @@ @@ -81,9 +81,3 @@
mul = <10 0>;
status = "okay";
};
&pclka {
clk_src = <RA_CLOCK_SOURCE_PLL>;
clk_div = <RA_SCI_CLOCK_DIV_2>;
status = "okay";
};

1
boards/renesas/fpb_ra6e2/fpb_ra6e2_defconfig
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@ -15,3 +15,4 @@ CONFIG_CONSOLE=y @@ -15,3 +15,4 @@ CONFIG_CONSOLE=y
CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_BUILD_NO_GAP_FILL=y
CONFIG_CLOCK_CONTROL=y

2
drivers/clock_control/Kconfig
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@ -82,7 +82,7 @@ source "drivers/clock_control/Kconfig.agilex5" @@ -82,7 +82,7 @@ source "drivers/clock_control/Kconfig.agilex5"
source "drivers/clock_control/Kconfig.renesas_ra"
source "drivers/clock_control/Kconfig.renesas_ra8"
source "drivers/clock_control/Kconfig.renesas_ra_cgc"
source "drivers/clock_control/Kconfig.max32"

0
drivers/clock_control/Kconfig.renesas_ra8 → drivers/clock_control/Kconfig.renesas_ra_cgc
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2
drivers/clock_control/clock_control_renesas_ra_cgc.c
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@ -77,7 +77,7 @@ static const struct clock_control_driver_api clock_control_reneas_ra_api = { @@ -77,7 +77,7 @@ static const struct clock_control_driver_api clock_control_reneas_ra_api = {
};
#define INIT_PCLK(node_id) \
IF_ENABLED(DT_NODE_HAS_COMPAT(node_id, renesas_ra8_cgc_pclk), \
IF_ENABLED(DT_NODE_HAS_COMPAT(node_id, renesas_ra_cgc_pclk), \
(static const struct clock_control_ra_pclk_cfg node_id##_cfg = \
{.clk_src = DT_PROP_OR(node_id, clk_src, RA_CLOCK_SOURCE_DISABLE), \
.clk_div = DT_PROP_OR(node_id, clk_div, RA_SYS_CLOCK_DIV_1)}; \

1
dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi
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@ -67,7 +67,6 @@ @@ -67,7 +67,6 @@
source = <RA_PLL_SOURCE_MAIN_OSC>;
div = <RA_PLL_DIV_1>;
mul = <20 0>;
freq = <DT_FREQ_M(120)>;
status = "disabled";
};

1
dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi
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@ -228,7 +228,6 @@ @@ -228,7 +228,6 @@
source = <RA_PLL_SOURCE_MAIN_OSC>;
div = <RA_PLL_DIV_3>;
mul = <25 0>;
freq = <DT_FREQ_M(200)>;
status = "disabled";
};

48
dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi
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@ -10,7 +10,7 @@ @@ -10,7 +10,7 @@
/ {
clocks: clocks {
xtal: clock-xtal {
compatible = "renesas,ra8-cgc-external-clock";
compatible = "renesas,ra-cgc-external-clock";
clock-frequency = <DT_FREQ_M(20)>;
#clock-cells = <0>;
status = "disabled";
@ -35,14 +35,14 @@ @@ -35,14 +35,14 @@
};
subclk: clock-subclk {
compatible = "renesas,ra8-cgc-subclk";
compatible = "renesas,ra-cgc-subclk";
clock-frequency = <32768>;
#clock-cells = <0>;
status = "disabled";
};
pll: pll {
compatible = "renesas,ra8-cgc-pll";
compatible = "renesas,ra-cgc-pll";
#clock-cells = <0>;
/* PLL */
@ -59,7 +59,7 @@ @@ -59,7 +59,7 @@
};
pll2: pll2 {
compatible = "renesas,ra8-cgc-pll";
compatible = "renesas,ra-cgc-pll";
#clock-cells = <0>;
/* PLL2 */
@ -76,65 +76,65 @@ @@ -76,65 +76,65 @@
};
pclkblock: pclkblock {
compatible = "renesas,ra8-cgc-pclk-block";
compatible = "renesas,ra-cgc-pclk-block";
#clock-cells = <0>;
sysclock-src = <RA_CLOCK_SOURCE_PLL1P>;
status = "okay";
cpuclk: cpuclk {
compatible = "renesas,ra8-cgc-pclk";
compatible = "renesas,ra-cgc-pclk";
clk_div = <RA_SYS_CLOCK_DIV_1>;
#clock-cells = <2>;
status = "okay";
};
iclk: iclk {
compatible = "renesas,ra8-cgc-pclk";
compatible = "renesas,ra-cgc-pclk";
clk_div = <RA_SYS_CLOCK_DIV_2>;
#clock-cells = <2>;
status = "okay";
};
pclka: pclka {
compatible = "renesas,ra8-cgc-pclk";
compatible = "renesas,ra-cgc-pclk";
clk_div = <RA_SYS_CLOCK_DIV_4>;
#clock-cells = <2>;
status = "okay";
};
pclkb: pclkb {
compatible = "renesas,ra8-cgc-pclk";
compatible = "renesas,ra-cgc-pclk";
clk_div = <RA_SYS_CLOCK_DIV_8>;
#clock-cells = <2>;
status = "okay";
};
pclkc: pclkc {
compatible = "renesas,ra8-cgc-pclk";
compatible = "renesas,ra-cgc-pclk";
clk_div = <RA_SYS_CLOCK_DIV_8>;
#clock-cells = <2>;
status = "okay";
};
pclkd: pclkd {
compatible = "renesas,ra8-cgc-pclk";
compatible = "renesas,ra-cgc-pclk";
clk_div = <RA_SYS_CLOCK_DIV_4>;
#clock-cells = <2>;
status = "okay";
};
pclke: pclke {
compatible = "renesas,ra8-cgc-pclk";
compatible = "renesas,ra-cgc-pclk";
clk_div = <RA_SYS_CLOCK_DIV_2>;
#clock-cells = <2>;
status = "okay";
};
bclk: bclk {
compatible = "renesas,ra8-cgc-pclk";
compatible = "renesas,ra-cgc-pclk";
clk_div = <RA_SYS_CLOCK_DIV_4>;
bclkout: bclkout {
compatible = "renesas,ra8-cgc-busclk";
compatible = "renesas,ra-cgc-busclk";
clk_out_div = <2>;
sdclk = <1>;
#clock-cells = <0>;
@ -144,62 +144,62 @@ @@ -144,62 +144,62 @@
};
fclk: fclk {
compatible = "renesas,ra8-cgc-pclk";
compatible = "renesas,ra-cgc-pclk";
clk_div = <RA_SYS_CLOCK_DIV_8>;
#clock-cells = <2>;
status = "okay";
};
clkout: clkout {
compatible = "renesas,ra8-cgc-pclk";
compatible = "renesas,ra-cgc-pclk";
#clock-cells = <2>;
status = "disabled";
};
sciclk: sciclk {
compatible = "renesas,ra8-cgc-pclk";
compatible = "renesas,ra-cgc-pclk";
#clock-cells = <2>;
status = "disabled";
};
spiclk: spiclk {
compatible = "renesas,ra8-cgc-pclk";
compatible = "renesas,ra-cgc-pclk";
#clock-cells = <2>;
status = "disabled";
};
canfdclk: canfdclk {
compatible = "renesas,ra8-cgc-pclk";
compatible = "renesas,ra-cgc-pclk";
#clock-cells = <2>;
status = "disabled";
};
i3cclk: i3cclk {
compatible = "renesas,ra8-cgc-pclk";
compatible = "renesas,ra-cgc-pclk";
#clock-cells = <2>;
status = "disabled";
};
uclk: uclk {
compatible = "renesas,ra8-cgc-pclk";
compatible = "renesas,ra-cgc-pclk";
#clock-cells = <2>;
status = "disabled";
};
u60clk: u60clk {
compatible = "renesas,ra8-cgc-pclk";
compatible = "renesas,ra-cgc-pclk";
#clock-cells = <2>;
status = "disabled";
};
octaspiclk: octaspiclk {
compatible = "renesas,ra8-cgc-pclk";
compatible = "renesas,ra-cgc-pclk";
#clock-cells = <2>;
status = "disabled";
};
lcdclk: lcdclk {
compatible = "renesas,ra8-cgc-pclk";
compatible = "renesas,ra-cgc-pclk";
#clock-cells = <2>;
status = "disabled";
};

46
dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi
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@ -10,7 +10,7 @@ @@ -10,7 +10,7 @@
/ {
clocks: clocks {
xtal: clock-xtal {
compatible = "renesas,ra8-cgc-external-clock";
compatible = "renesas,ra-cgc-external-clock";
clock-frequency = <DT_FREQ_M(20)>;
#clock-cells = <0>;
status = "disabled";
@ -35,14 +35,14 @@ @@ -35,14 +35,14 @@
};
subclk: clock-subclk {
compatible = "renesas,ra8-cgc-subclk";
compatible = "renesas,ra-cgc-subclk";
clock-frequency = <32768>;
#clock-cells = <0>;
status = "disabled";
};
pll: pll {
compatible = "renesas,ra8-cgc-pll";
compatible = "renesas,ra-cgc-pll";
#clock-cells = <0>;
/* PLL */
@ -59,7 +59,7 @@ @@ -59,7 +59,7 @@
};
pll2: pll2 {
compatible = "renesas,ra8-cgc-pll";
compatible = "renesas,ra-cgc-pll";
#clock-cells = <0>;
/* PLL2 */
@ -76,65 +76,65 @@ @@ -76,65 +76,65 @@
};
pclkblock: pclkblock {
compatible = "renesas,ra8-cgc-pclk-block";
compatible = "renesas,ra-cgc-pclk-block";
#clock-cells = <0>;
sysclock-src = <RA_CLOCK_SOURCE_PLL1P>;
status = "okay";
cpuclk: cpuclk {
compatible = "renesas,ra8-cgc-pclk";
compatible = "renesas,ra-cgc-pclk";
clk_div = <RA_SYS_CLOCK_DIV_1>;
#clock-cells = <2>;
status = "okay";
};
iclk: iclk {
compatible = "renesas,ra8-cgc-pclk";
compatible = "renesas,ra-cgc-pclk";
clk_div = <RA_SYS_CLOCK_DIV_2>;
#clock-cells = <2>;
status = "okay";
};
pclka: pclka {
compatible = "renesas,ra8-cgc-pclk";
compatible = "renesas,ra-cgc-pclk";
clk_div = <RA_SYS_CLOCK_DIV_4>;
#clock-cells = <2>;
status = "okay";
};
pclkb: pclkb {
compatible = "renesas,ra8-cgc-pclk";
compatible = "renesas,ra-cgc-pclk";
clk_div = <RA_SYS_CLOCK_DIV_8>;
#clock-cells = <2>;
status = "okay";
};
pclkc: pclkc {
compatible = "renesas,ra8-cgc-pclk";
compatible = "renesas,ra-cgc-pclk";
clk_div = <RA_SYS_CLOCK_DIV_8>;
#clock-cells = <2>;
status = "okay";
};
pclkd: pclkd {
compatible = "renesas,ra8-cgc-pclk";
compatible = "renesas,ra-cgc-pclk";
clk_div = <RA_SYS_CLOCK_DIV_4>;
#clock-cells = <2>;
status = "okay";
};
pclke: pclke {
compatible = "renesas,ra8-cgc-pclk";
compatible = "renesas,ra-cgc-pclk";
clk_div = <RA_SYS_CLOCK_DIV_2>;
#clock-cells = <2>;
status = "okay";
};
bclk: bclk {
compatible = "renesas,ra8-cgc-pclk";
compatible = "renesas,ra-cgc-pclk";
clk_div = <RA_SYS_CLOCK_DIV_4>;
bclkout: bclkout {
compatible = "renesas,ra8-cgc-busclk";
compatible = "renesas,ra-cgc-busclk";
clk_out_div = <2>;
sdclk = <1>;
#clock-cells = <0>;
@ -144,56 +144,56 @@ @@ -144,56 +144,56 @@
};
fclk: fclk {
compatible = "renesas,ra8-cgc-pclk";
compatible = "renesas,ra-cgc-pclk";
clk_div = <RA_SYS_CLOCK_DIV_8>;
#clock-cells = <2>;
status = "okay";
};
clkout: clkout {
compatible = "renesas,ra8-cgc-pclk";
compatible = "renesas,ra-cgc-pclk";
#clock-cells = <2>;
status = "disabled";
};
sciclk: sciclk {
compatible = "renesas,ra8-cgc-pclk";
compatible = "renesas,ra-cgc-pclk";
#clock-cells = <2>;
status = "disabled";
};
spiclk: spiclk {
compatible = "renesas,ra8-cgc-pclk";
compatible = "renesas,ra-cgc-pclk";
#clock-cells = <2>;
status = "disabled";
};
canfdclk: canfdclk {
compatible = "renesas,ra8-cgc-pclk";
compatible = "renesas,ra-cgc-pclk";
#clock-cells = <2>;
status = "disabled";
};
i3cclk: i3cclk {
compatible = "renesas,ra8-cgc-pclk";
compatible = "renesas,ra-cgc-pclk";
#clock-cells = <2>;
status = "disabled";
};
uclk: uclk {
compatible = "renesas,ra8-cgc-pclk";
compatible = "renesas,ra-cgc-pclk";
#clock-cells = <2>;
status = "disabled";
};
u60clk: u60clk {
compatible = "renesas,ra8-cgc-pclk";
compatible = "renesas,ra-cgc-pclk";
#clock-cells = <2>;
status = "disabled";
};
octaspiclk: octaspiclk {
compatible = "renesas,ra8-cgc-pclk";
compatible = "renesas,ra-cgc-pclk";
#clock-cells = <2>;
status = "disabled";
};

48
dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi
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@ -10,7 +10,7 @@ @@ -10,7 +10,7 @@
/ {
clocks: clocks {
xtal: clock-xtal {
compatible = "renesas,ra8-cgc-external-clock";
compatible = "renesas,ra-cgc-external-clock";
clock-frequency = <DT_FREQ_M(24)>;
#clock-cells = <0>;
status = "disabled";
@ -35,14 +35,14 @@ @@ -35,14 +35,14 @@
};
subclk: clock-subclk {
compatible = "renesas,ra8-cgc-subclk";
compatible = "renesas,ra-cgc-subclk";
clock-frequency = <32768>;
#clock-cells = <0>;
status = "disabled";
};
pll: pll {
compatible = "renesas,ra8-cgc-pll";
compatible = "renesas,ra-cgc-pll";
#clock-cells = <0>;
/* PLL */
@ -59,7 +59,7 @@ @@ -59,7 +59,7 @@
};
pll2: pll2 {
compatible = "renesas,ra8-cgc-pll";
compatible = "renesas,ra-cgc-pll";
#clock-cells = <0>;
/* PLL2 */
@ -76,65 +76,65 @@ @@ -76,65 +76,65 @@
};
pclkblock: pclkblock {
compatible = "renesas,ra8-cgc-pclk-block";
compatible = "renesas,ra-cgc-pclk-block";
#clock-cells = <0>;
sysclock-src = <RA_CLOCK_SOURCE_PLL1P>;
status = "okay";
cpuclk: cpuclk {
compatible = "renesas,ra8-cgc-pclk";
compatible = "renesas,ra-cgc-pclk";
clk_div = <RA_SYS_CLOCK_DIV_1>;
#clock-cells = <2>;
status = "okay";
};
iclk: iclk {
compatible = "renesas,ra8-cgc-pclk";
compatible = "renesas,ra-cgc-pclk";
clk_div = <RA_SYS_CLOCK_DIV_2>;
#clock-cells = <2>;
status = "okay";
};
pclka: pclka {
compatible = "renesas,ra8-cgc-pclk";
compatible = "renesas,ra-cgc-pclk";
clk_div = <RA_SYS_CLOCK_DIV_4>;
#clock-cells = <2>;
status = "okay";
};
pclkb: pclkb {
compatible = "renesas,ra8-cgc-pclk";
compatible = "renesas,ra-cgc-pclk";
clk_div = <RA_SYS_CLOCK_DIV_8>;
#clock-cells = <2>;
status = "okay";
};
pclkc: pclkc {
compatible = "renesas,ra8-cgc-pclk";
compatible = "renesas,ra-cgc-pclk";
clk_div = <RA_SYS_CLOCK_DIV_8>;
#clock-cells = <2>;
status = "okay";
};
pclkd: pclkd {
compatible = "renesas,ra8-cgc-pclk";
compatible = "renesas,ra-cgc-pclk";
clk_div = <RA_SYS_CLOCK_DIV_4>;
#clock-cells = <2>;
status = "okay";
};
pclke: pclke {
compatible = "renesas,ra8-cgc-pclk";
compatible = "renesas,ra-cgc-pclk";
clk_div = <RA_SYS_CLOCK_DIV_2>;
#clock-cells = <2>;
status = "okay";
};
bclk: bclk {
compatible = "renesas,ra8-cgc-pclk";
compatible = "renesas,ra-cgc-pclk";
clk_div = <RA_SYS_CLOCK_DIV_4>;
bclkout: bclkout {
compatible = "renesas,ra8-cgc-busclk";
compatible = "renesas,ra-cgc-busclk";
clk_out_div = <2>;
sdclk = <1>;
#clock-cells = <0>;
@ -144,62 +144,62 @@ @@ -144,62 +144,62 @@
};
fclk: fclk {
compatible = "renesas,ra8-cgc-pclk";
compatible = "renesas,ra-cgc-pclk";
clk_div = <RA_SYS_CLOCK_DIV_8>;
#clock-cells = <2>;
status = "okay";
};
clkout: clkout {
compatible = "renesas,ra8-cgc-pclk";
compatible = "renesas,ra-cgc-pclk";
#clock-cells = <2>;
status = "disabled";
};
sciclk: sciclk {
compatible = "renesas,ra8-cgc-pclk";
compatible = "renesas,ra-cgc-pclk";
#clock-cells = <2>;
status = "disabled";
};
spiclk: spiclk {
compatible = "renesas,ra8-cgc-pclk";
compatible = "renesas,ra-cgc-pclk";
#clock-cells = <2>;
status = "disabled";
};
canfdclk: canfdclk {
compatible = "renesas,ra8-cgc-pclk";
compatible = "renesas,ra-cgc-pclk";
#clock-cells = <2>;
status = "disabled";
};
i3cclk: i3cclk {
compatible = "renesas,ra8-cgc-pclk";
compatible = "renesas,ra-cgc-pclk";
#clock-cells = <2>;
status = "disabled";
};
uclk: uclk {
compatible = "renesas,ra8-cgc-pclk";
compatible = "renesas,ra-cgc-pclk";
#clock-cells = <2>;
status = "disabled";
};
u60clk: u60clk {
compatible = "renesas,ra8-cgc-pclk";
compatible = "renesas,ra-cgc-pclk";
#clock-cells = <2>;
status = "disabled";
};
octaspiclk: octaspiclk {
compatible = "renesas,ra8-cgc-pclk";
compatible = "renesas,ra-cgc-pclk";
#clock-cells = <2>;
status = "disabled";
};
lcdclk: lcdclk {
compatible = "renesas,ra8-cgc-pclk";
compatible = "renesas,ra-cgc-pclk";
#clock-cells = <2>;
status = "disabled";
};

4
dts/bindings/clock/renesas,ra8-cgc-busclk.yaml → dts/bindings/clock/renesas,ra-cgc-busclk.yaml
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@ -1,9 +1,9 @@ @@ -1,9 +1,9 @@
# Copyright (c) 2024 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
description: Renesas RA8 External Bus Clock
description: Renesas RA External Bus Clock
compatible: "renesas,ra8-cgc-busclk"
compatible: "renesas,ra-cgc-busclk"
include: [clock-controller.yaml, base.yaml]

4
dts/bindings/clock/renesas,ra8-cgc-external-clock.yaml → dts/bindings/clock/renesas,ra-cgc-external-clock.yaml
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@ -1,9 +1,9 @@ @@ -1,9 +1,9 @@
# Copyright (c) 2024 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
description: Renesas RA8 Clock Generation Circuit external clock configuration
description: Renesas RA Clock Generation Circuit external clock configuration
compatible: "renesas,ra8-cgc-external-clock"
compatible: "renesas,ra-cgc-external-clock"
include: [fixed-clock.yaml, base.yaml]

4
dts/bindings/clock/renesas,ra8-cgc-pclk-block.yaml → dts/bindings/clock/renesas,ra-cgc-pclk-block.yaml
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@ -1,9 +1,9 @@ @@ -1,9 +1,9 @@
# Copyright (c) 2024 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
description: Renesas RA8 clock control node pclk block
description: Renesas RA Clock Control node pclk block
compatible: "renesas,ra8-cgc-pclk-block"
compatible: "renesas,ra-cgc-pclk-block"
include: [clock-controller.yaml, base.yaml]

4
dts/bindings/clock/renesas,ra8-cgc-pclk.yaml → dts/bindings/clock/renesas,ra-cgc-pclk.yaml
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@ -1,9 +1,9 @@ @@ -1,9 +1,9 @@
# Copyright (c) 2024 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
description: Renesas RA8 Clock Control Peripheral Clock
description: Renesas RA Clock Control Peripheral Clock
compatible: "renesas,ra8-cgc-pclk"
compatible: "renesas,ra-cgc-pclk"
include: [clock-controller.yaml, base.yaml]

6
dts/bindings/clock/renesas,ra8-cgc-pll.yaml → dts/bindings/clock/renesas,ra-cgc-pll.yaml
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@ -1,9 +1,9 @@ @@ -1,9 +1,9 @@
# Copyright (c) 2024 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
description: Renesas RA8 Clock Generation Circuit PLL Clock
description: Renesas RA Clock Generation Circuit PLL Clock
compatible: "renesas,ra8-cgc-pll"
compatible: "renesas,ra-cgc-pll"
include: [clock-controller.yaml, base.yaml]
@ -18,10 +18,8 @@ properties: @@ -18,10 +18,8 @@ properties:
required: true
type: array
divp:
required: true
type: int
freqp:
required: true
type: int
divq:
type: int

4
dts/bindings/clock/renesas,ra8-cgc-subclk.yaml → dts/bindings/clock/renesas,ra-cgc-subclk.yaml
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@ -1,9 +1,9 @@ @@ -1,9 +1,9 @@
# Copyright (c) 2024 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
description: Renesas RA8 Sub-Clock
description: Renesas RA Sub-Clock
compatible: "renesas,ra8-cgc-subclk"
compatible: "renesas,ra-cgc-subclk"
include: fixed-clock.yaml

1
soc/renesas/ra/ra6e1/Kconfig
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@ -6,6 +6,7 @@ config SOC_SERIES_RA6E1 @@ -6,6 +6,7 @@ config SOC_SERIES_RA6E1
select CPU_CORTEX_M33
select CPU_HAS_ARM_MPU
select HAS_RENESAS_RA_FSP
select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_FPU
select ARMV8_M_DSP

2
soc/renesas/ra/ra6e1/soc.c
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@ -38,6 +38,7 @@ static int renesas_ra6e1_init(void) @@ -38,6 +38,7 @@ static int renesas_ra6e1_init(void)
uint32_t key;
extern volatile uint16_t g_protect_counters[];
for (uint32_t i = 0; i < 4; i++) {
g_protect_counters[i] = 0;
}
@ -64,7 +65,6 @@ static int renesas_ra6e1_init(void) @@ -64,7 +65,6 @@ static int renesas_ra6e1_init(void)
SystemCoreClock = BSP_MOCO_HZ;
g_protect_pfswe_counter = 0;
bsp_clock_init();
irq_unlock(key);

1
soc/renesas/ra/ra6e2/Kconfig
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@ -6,6 +6,7 @@ config SOC_SERIES_RA6E2 @@ -6,6 +6,7 @@ config SOC_SERIES_RA6E2
select CPU_CORTEX_M33
select CPU_HAS_ARM_MPU
select HAS_RENESAS_RA_FSP
select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_FPU
select ARMV8_M_DSP

2
soc/renesas/ra/ra6e2/soc.c
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@ -40,6 +40,7 @@ static int renesas_ra6e2_init(void) @@ -40,6 +40,7 @@ static int renesas_ra6e2_init(void)
key = irq_lock();
extern volatile uint16_t g_protect_counters[];
for (uint32_t i = 0; i < 4; i++) {
g_protect_counters[i] = 0;
}
@ -64,7 +65,6 @@ static int renesas_ra6e2_init(void) @@ -64,7 +65,6 @@ static int renesas_ra6e2_init(void)
SystemCoreClock = BSP_MOCO_HZ;
g_protect_pfswe_counter = 0;
bsp_clock_init();
irq_unlock(key);

1
soc/renesas/ra/ra6m1/Kconfig
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@ -6,6 +6,7 @@ config SOC_SERIES_RA6M1 @@ -6,6 +6,7 @@ config SOC_SERIES_RA6M1
select CPU_CORTEX_M4
select CPU_HAS_ARM_MPU
select HAS_RENESAS_RA_FSP
select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_FPU
select FPU

1
soc/renesas/ra/ra6m1/soc.c
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@ -41,7 +41,6 @@ static int renesas_ra6m1_init(void) @@ -41,7 +41,6 @@ static int renesas_ra6m1_init(void)
SystemCoreClock = BSP_MOCO_HZ;
g_protect_pfswe_counter = 0;
bsp_clock_init();
irq_unlock(key);

1
soc/renesas/ra/ra6m2/Kconfig
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@ -6,6 +6,7 @@ config SOC_SERIES_RA6M2 @@ -6,6 +6,7 @@ config SOC_SERIES_RA6M2
select CPU_CORTEX_M4
select CPU_HAS_ARM_MPU
select HAS_RENESAS_RA_FSP
select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_FPU
select FPU

1
soc/renesas/ra/ra6m2/soc.c
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@ -41,7 +41,6 @@ static int renesas_ra6m2_init(void) @@ -41,7 +41,6 @@ static int renesas_ra6m2_init(void)
SystemCoreClock = BSP_MOCO_HZ;
g_protect_pfswe_counter = 0;
bsp_clock_init();
irq_unlock(key);

1
soc/renesas/ra/ra6m3/Kconfig
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@ -6,6 +6,7 @@ config SOC_SERIES_RA6M3 @@ -6,6 +6,7 @@ config SOC_SERIES_RA6M3
select CPU_CORTEX_M4
select CPU_HAS_ARM_MPU
select HAS_RENESAS_RA_FSP
select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_FPU
select FPU

1
soc/renesas/ra/ra6m3/soc.c
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@ -41,7 +41,6 @@ static int renesas_ra6m3_init(void) @@ -41,7 +41,6 @@ static int renesas_ra6m3_init(void)
SystemCoreClock = BSP_MOCO_HZ;
g_protect_pfswe_counter = 0;
bsp_clock_init();
irq_unlock(key);

1
soc/renesas/ra/ra6m5/Kconfig
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@ -6,6 +6,7 @@ config SOC_SERIES_RA6M5 @@ -6,6 +6,7 @@ config SOC_SERIES_RA6M5
select CPU_CORTEX_M33
select CPU_HAS_ARM_MPU
select HAS_RENESAS_RA_FSP
select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_FPU
select ARMV8_M_DSP

2
soc/renesas/ra/ra6m5/soc.c
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@ -40,6 +40,7 @@ static int renesas_ra6m5_init(void) @@ -40,6 +40,7 @@ static int renesas_ra6m5_init(void)
key = irq_lock();
extern volatile uint16_t g_protect_counters[];
for (uint32_t i = 0; i < 4; i++) {
g_protect_counters[i] = 0;
}
@ -64,7 +65,6 @@ static int renesas_ra6m5_init(void) @@ -64,7 +65,6 @@ static int renesas_ra6m5_init(void)
SystemCoreClock = BSP_MOCO_HZ;
g_protect_pfswe_counter = 0;
bsp_clock_init();
irq_unlock(key);

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