drivers: mspi_dw: Add error reporting on RX FIFO overflow

Immediately finish an RX transfer when the RX FIFO overflow is
encountered and return the -EIO error code, which better indicates
the problem than -ETIMEDOUT that was returned previously in such
case.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>

drivers/mspi/mspi_dw.c

@@ -101,6 +101,7 @@ DEFINE_MM_REG_RD(rxflr,		0x24)
 DEFINE_MM_REG_RD(sr,		0x28)
 DEFINE_MM_REG_WR(imr,		0x2c)
 DEFINE_MM_REG_RD(isr,		0x30)
+DEFINE_MM_REG_RD(risr,		0x34)
 DEFINE_MM_REG_RD_WR(dr,		0x60)
 DEFINE_MM_REG_WR(spi_ctrlr0,	0xf4)
 
@@ -279,6 +280,11 @@ static void mspi_dw_isr(const struct device *dev)
 					break;
 				}
 
+				if (read_risr(dev) & RISR_RXOIR_BIT) {
+					finished = true;
+					break;
+				}
+
 				int_status = read_isr(dev);
 			}
 
@@ -977,7 +983,11 @@ static int start_next_packet(const struct device *dev, k_timeout_t timeout)
 	write_imr(dev, imr);
 
 	rc = k_sem_take(&dev_data->finished, timeout);
-	if (rc < 0) {
+	if (read_risr(dev) & RISR_RXOIR_BIT) {
+		LOG_ERR("RX FIFO overflow occurred");
+		rc = -EIO;
+	} else if (rc < 0) {
+		LOG_ERR("Transfer timed out");
 		rc = -ETIMEDOUT;
 	}
 

drivers/mspi/mspi_dw.h

@@ -66,6 +66,19 @@
 #define ISR_RXFIS_BIT		BIT(4)
 #define ISR_MSTIS_BIT		BIT(5)
 
+/* RISR - Raw Interrupt Status Register */
+#define RISR_TXEIR_BIT		BIT(0)
+#define RISR_TXOIR_BIT		BIT(1)
+#define RISR_RXUIR_BIT		BIT(2)
+#define RISR_RXOIR_BIT		BIT(3)
+#define RISR_RXFIR_BIT		BIT(4)
+#define RISR_MSTIR_BIT		BIT(5)
+#define RISR_XRXOIR_BIT		BIT(6)
+#define RISR_TXUIR_BIT		BIT(7)
+#define RISR_AXIER_BIT		BIT(8)
+#define RISR_SPITER_BIT		BIT(10)
+#define RISR_DONER_BIT		BIT(11)
+
 /* SPI_CTRLR0 - SPI Control Register */
 #define SPI_CTRLR0_CLK_STRETCH_EN_BIT		BIT(30)
 #define SPI_CTRLR0_XIP_PREFETCH_EN_BIT		BIT(29)