From 258cc7e9cfd0148887709ab209e1c7f32b5090fb Mon Sep 17 00:00:00 2001 From: Saravanan Sekar Date: Tue, 15 Apr 2025 11:56:07 +0530 Subject: [PATCH] drivers: pinctrl: mspm0: Add a pinctrl driver for TI MSPM0 Added a pinctrl driver support for MSPM0 Family. Signed-off-by: Saravanan Sekar Signed-off-by: Jackson Farley --- drivers/pinctrl/CMakeLists.txt | 1 + drivers/pinctrl/Kconfig | 1 + drivers/pinctrl/Kconfig.mspm0 | 9 ++ drivers/pinctrl/pinctrl_mspm0.c | 39 ++++++ dts/bindings/pinctrl/ti,mspm0-pinctrl.yaml | 122 ++++++++++++++++++ .../dt-bindings/pinctrl/mspm0-pinctrl.h | 29 +++++ soc/ti/mspm0/mspm0g/pinctrl_soc.h | 50 +++++++ 7 files changed, 251 insertions(+) create mode 100644 drivers/pinctrl/Kconfig.mspm0 create mode 100644 drivers/pinctrl/pinctrl_mspm0.c create mode 100644 dts/bindings/pinctrl/ti,mspm0-pinctrl.yaml create mode 100644 include/zephyr/dt-bindings/pinctrl/mspm0-pinctrl.h create mode 100644 soc/ti/mspm0/mspm0g/pinctrl_soc.h diff --git a/drivers/pinctrl/CMakeLists.txt b/drivers/pinctrl/CMakeLists.txt index 6e0747667a8..5efe0bd6abc 100644 --- a/drivers/pinctrl/CMakeLists.txt +++ b/drivers/pinctrl/CMakeLists.txt @@ -16,6 +16,7 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_ITE_IT8XXX2 pinctrl_ite_it8xxx2.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_NPCX pinctrl_npcx.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_NUMICRO pinctrl_numicro.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_NRF pinctrl_nrf.c) +zephyr_library_sources_ifdef(CONFIG_PINCTRL_MSPM0 pinctrl_mspm0.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_RPI_PICO pinctrl_rpi_pico.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_SAM pinctrl_sam.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_SAM0 pinctrl_sam0.c) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index df6ab582e0e..a47c4392a78 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -45,6 +45,7 @@ source "drivers/pinctrl/Kconfig.it8xxx2" source "drivers/pinctrl/Kconfig.npcx" source "drivers/pinctrl/Kconfig.numicro" source "drivers/pinctrl/Kconfig.nrf" +source "drivers/pinctrl/Kconfig.mspm0" source "drivers/pinctrl/Kconfig.rpi_pico" source "drivers/pinctrl/Kconfig.sam" source "drivers/pinctrl/Kconfig.sam0" diff --git a/drivers/pinctrl/Kconfig.mspm0 b/drivers/pinctrl/Kconfig.mspm0 new file mode 100644 index 00000000000..1bd21a1c606 --- /dev/null +++ b/drivers/pinctrl/Kconfig.mspm0 @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2025 Texas Instruments + +config PINCTRL_MSPM0 + bool "TI pinctrl MSPM0 driver" + default y + depends on DT_HAS_TI_MSPM0_PINCTRL_ENABLED + help + Enable support for the PINCTRL on TI MSPM0 series. diff --git a/drivers/pinctrl/pinctrl_mspm0.c b/drivers/pinctrl/pinctrl_mspm0.c new file mode 100644 index 00000000000..fc8055c196e --- /dev/null +++ b/drivers/pinctrl/pinctrl_mspm0.c @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2025 Texas Instruments + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +#define DT_DRV_COMPAT ti_mspm0_pinctrl + +#define MSPM0_PINCM(pinmux) (pinmux >> 0x10) +#define MSPM0_PIN_FUNCTION(pinmux) (pinmux & 0x3F) + +int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, + uint8_t pin_cnt, + uintptr_t reg) +{ + ARG_UNUSED(reg); + + uint8_t pin_function; + uint32_t pin_cm; + uint32_t iomux; + + for (int i = 0; i < pin_cnt; i++) { + pin_cm = MSPM0_PINCM(pins[i].pinmux); + pin_function = MSPM0_PIN_FUNCTION(pins[i].pinmux); + iomux = pins[i].iomux; + if (pin_function == 0x00) { + DL_GPIO_initPeripheralAnalogFunction(pin_cm); + } else { + DL_GPIO_initPeripheralFunction(pin_cm, + (iomux | pin_function)); + } + } + + return 0; +} diff --git a/dts/bindings/pinctrl/ti,mspm0-pinctrl.yaml b/dts/bindings/pinctrl/ti,mspm0-pinctrl.yaml new file mode 100644 index 00000000000..68c632c5cd8 --- /dev/null +++ b/dts/bindings/pinctrl/ti,mspm0-pinctrl.yaml @@ -0,0 +1,122 @@ +# Copyright (c) 2025 Texas Instruments +# Copyright (c) 2025 Linumiz +# SPDX-License-Identifier: Apache-2.0 + +description: | + TI MSPM0 pinctrl node. + + Device pin configuration should be placed in the child nodes of this node. + Populate the 'pinmux' field with a pair consisting of a pin number and its + IO functions. + + The node has the 'pinctrl' node label set in your SoC's devicetree, + so you can modify it like this: + + &pinctrl { + /* your modifications go here */ + }; + + All device pin configurations should be placed in child nodes of the + 'pinctrl' node, as in the i2c0 example shown at the end. + + Here is a list of + supported standard pin properties: + + - bias-disable: Disable pull-up/down. + - bias-pull-down: Enable pull-down resistor. + - bias-pull-up: Enable pull-up resistor. + - drive-open-drain: Output driver is open-drain. + - drive-open-drain: Output driver is open-source. + - drive-strength: Maximum current that can be sourced from the pin. + - input-enable: enable input. + - ti,invert: enable logical inversion of a digital input or output + - ti,hysteresis: enable hysteresis control on open-drain pins + + An example for MSPM0 family, include the chip level pinctrl + DTSI file in the board level DTS: + + #include + + We want to configure the I2C pins to open drain, with pullup enabled + and input enabled. + + To change a pin's pinctrl default properties add a reference to the + pin in the board's DTS file or in the project overlay and set the + properties. + + &i2c1 { + pinctrl-0 = <&i2c1_scl_pb2_pull_up &i2c1_sda_pb3_pull_up>; + pinctrl-names = "default"; + } + + The i2c1_scl_pb2_pull_up corresponds to the following pin configuration in + the board dts file: + + &pinctrl { + i2c1_scl_pb2_pull_up: i2c1_scl_pb2_pull_up { + pinmux = ; + input-enable; + bias-pull-up; + drive-open-drain; + }; + }; + + Pin pb2 refers to the device pin name that one would see printed on the + launchpad, and the number 15 in the pinmux define refers to the PINCMx. + + These are obtained from the device-specific datasheet. + +compatible: "ti,mspm0-pinctrl" + +include: base.yaml + +properties: + reg: + required: true + +child-binding: + description: | + This binding gives a base representation of the MSPM0 + pins configuration. + + include: + - name: pincfg-node.yaml + property-allowlist: + - bias-disable + - bias-pull-down + - bias-pull-up + - bias-high-impedance + - drive-open-drain + - drive-open-source + - drive-strength + - input-enable + + properties: + pinmux: + required: true + type: int + description: | + MSPM0 pin's configuration (IO pin, IO function). + + drive-strength: + enum: + - 6 + - 20 + default: 6 + description: | + The drive strength controls the maximum output drive strength sunk or + sourced by an I/O pin. + 6: max 6 mA (SoC default) + 20: max 20 mA on high-drive capable IOs only (HDIO). + + ti,invert: + type: boolean + description: | + Enables inversion of the input or output using the internal + inversion capability of the GPIO + + ti,hysteresis: + type: boolean + description: | + Enables the hysteresis control for access to CMOS logic + (on open-drain capable pins) diff --git a/include/zephyr/dt-bindings/pinctrl/mspm0-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/mspm0-pinctrl.h new file mode 100644 index 00000000000..e2ec3d3335a --- /dev/null +++ b/include/zephyr/dt-bindings/pinctrl/mspm0-pinctrl.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2025 Texas Instruments + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _MSPM0_DT_BINDINGS_PINCTRL_H_ +#define _MSPM0_DT_BINDINGS_PINCTRL_H_ + +#define MSP_PORT_INDEX_BY_NAME(x) ((x == "PORTA") ? 0 : 1) + +#define MSPM0_PIN_FUNCTION_ANALOG (0x00000000) +#define MSPM0_PIN_FUNCTION_GPIO (0x00000001) +#define MSPM0_PIN_FUNCTION_2 (0x00000002) +#define MSPM0_PIN_FUNCTION_3 (0x00000003) +#define MSPM0_PIN_FUNCTION_4 (0x00000004) +#define MSPM0_PIN_FUNCTION_5 (0x00000005) +#define MSPM0_PIN_FUNCTION_6 (0x00000006) +#define MSPM0_PIN_FUNCTION_7 (0x00000007) +#define MSPM0_PIN_FUNCTION_8 (0x00000008) +#define MSPM0_PIN_FUNCTION_9 (0x00000009) +#define MSPM0_PIN_FUNCTION_10 (0x0000000A) + +/* Creates a concatenation of the correct pin function based on the pin control + * management register offset and the function suffix. + */ +#define MSP_PINMUX(pincm, function) (((pincm - 1) << 0x10) | function) + +#endif diff --git a/soc/ti/mspm0/mspm0g/pinctrl_soc.h b/soc/ti/mspm0/mspm0g/pinctrl_soc.h new file mode 100644 index 00000000000..0433f072604 --- /dev/null +++ b/soc/ti/mspm0/mspm0g/pinctrl_soc.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2025 Texas Instruments + * Copyright (c) 2025 Linumiz + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __ZEPHYR_SOC_ARM_TI_MSPM0_M0G_PINCTRL_SOC_H__ +#define __ZEPHYR_SOC_ARM_TI_MSPM0_M0G_PINCTRL_SOC_H__ + +#include +#include +#include + +#define MSP_GPIO_RESISTOR_PULL_DOWN (16) +#define MSP_GPIO_RESISTOR_PULL_UP (17) +#define MSP_GPIO_INPUT_ENABLE (18) +#define MSP_GPIO_HYSTERESIS_ENABLED (19) +#define MSP_GPIO_HIGH_DRIVE (20) +#define MSP_GPIO_OPEN_DRAIN_OUTPUT (25) +#define MSP_GPIO_INVERSION_ENABLED (26) + +#define MSP_PINMUX_INIT(node_id) DT_PROP(node_id, pinmux) + +#define MSP_PIN_CONTROL_IOMUX_INIT(node_id) \ + ((DT_PROP(node_id, bias_pull_up) << MSP_GPIO_RESISTOR_PULL_UP) | \ + (DT_PROP(node_id, bias_pull_down) << MSP_GPIO_RESISTOR_PULL_DOWN) | \ + (DT_PROP(node_id, drive_open_drain) << MSP_GPIO_OPEN_DRAIN_OUTPUT) | \ + (DT_ENUM_IDX(node_id, drive_strength) << MSP_GPIO_HIGH_DRIVE) | \ + (DT_PROP(node_id, ti_hysteresis) << MSP_GPIO_HYSTERESIS_ENABLED) | \ + (DT_PROP(node_id, ti_invert) << MSP_GPIO_INVERSION_ENABLED) | \ + (DT_PROP(node_id, input_enable) << MSP_GPIO_INPUT_ENABLE)) + +typedef struct pinctrl_soc_pin { + /* PINCM register index and pin function */ + uint32_t pinmux; + /* IOMUX Pin Control Management (direction, inversion, pullups) */ + uint32_t iomux; +} pinctrl_soc_pin_t; + +#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \ + {.pinmux = MSP_PINMUX_INIT(DT_PROP_BY_IDX(node_id, prop, idx)), \ + .iomux = MSP_PIN_CONTROL_IOMUX_INIT(DT_PROP_BY_IDX(node_id, prop, idx))}, + +#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \ + { \ + DT_FOREACH_PROP_ELEM(node_id, prop, Z_PINCTRL_STATE_PIN_INIT) \ + } + +#endif /* __ZEPHYR_SOC_ARM_TI_MSPM0_M0G_PINCTRL_SOC_H__ */