soc: nxp: convert NXP S32 family to hwmv2

Convert NXP S32 family to hardware model v2.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>

drivers/can/Kconfig.mcux

@@ -31,9 +31,9 @@ config CAN_MCUX_FLEXCAN_WAIT_TIMEOUT
 config CAN_MAX_MB
 	int "Maximum number of message buffers for concurrent active instances"
 	default 16
-	depends on SOC_SERIES_S32K3XX || SOC_SERIES_S32K1XX
+	depends on SOC_SERIES_S32K3 || SOC_SERIES_S32K1
-	range 1 96 if SOC_SERIES_S32K3XX
+	range 1 96 if SOC_SERIES_S32K3
-	range 1 32 if SOC_SERIES_S32K1XX && !SOC_S32K142W && !SOC_S32K144W
+	range 1 32 if SOC_SERIES_S32K1 && !SOC_S32K142W && !SOC_S32K144W
 	range 1 64 if SOC_S32K142W || SOC_S32K144W
 	help
 	  Defines maximum number of message buffers for concurrent active instances.
@@ -44,8 +44,8 @@ config CAN_MAX_FILTER
 	range 1 15 if SOC_SERIES_KINETIS_KE1XF || SOC_SERIES_KINETIS_K6X
 	range 1 13 if SOC_SERIES_IMX_RT && CAN_MCUX_FLEXCAN_FD
 	range 1 63 if SOC_SERIES_IMX_RT
-	range 1 96 if SOC_SERIES_S32K3XX
+	range 1 96 if SOC_SERIES_S32K3
-	range 1 32 if SOC_SERIES_S32K1XX && !SOC_S32K142W && !SOC_S32K144W
+	range 1 32 if SOC_SERIES_S32K1 && !SOC_S32K142W && !SOC_S32K144W
 	range 1 64 if SOC_S32K142W || SOC_S32K144W
 	help
 	  Defines maximum number of concurrent active RX filters

drivers/dma/Kconfig.mcux_edma

@@ -28,10 +28,10 @@ config DMA_TCD_QUEUE_SIZE
 
 config DMA_MCUX_TEST_SLOT_START
 	int "test slot start num"
-	depends on (SOC_SERIES_KINETIS_K6X || SOC_SERIES_KINETIS_KE1XF || SOC_SERIES_S32K3XX)
+	depends on (SOC_SERIES_KINETIS_K6X || SOC_SERIES_KINETIS_KE1XF || SOC_SERIES_S32K3)
 	default 58 if SOC_SERIES_KINETIS_K6X
 	default 60 if SOC_SERIES_KINETIS_KE1XF
-	default 62 if SOC_SERIES_S32K3XX
+	default 62 if SOC_SERIES_S32K3
 	help
 	  test slot start num
 

drivers/ethernet/eth_nxp_s32_gmac.c

@@ -147,7 +147,7 @@ static void phy_link_state_changed(const struct device *pdev,
 	}
 }
 
-#if defined(CONFIG_SOC_SERIES_S32K3XX)
+#if defined(CONFIG_SOC_SERIES_S32K3)
 static int select_phy_interface(Gmac_Ip_MiiModeType mode)
 {
 	uint32_t regval;
@@ -174,7 +174,7 @@ static int select_phy_interface(Gmac_Ip_MiiModeType mode)
 }
 #else
 #error "SoC not supported"
-#endif /* CONFIG_SOC_SERIES_S32K3XX */
+#endif /* CONFIG_SOC_SERIES_S32K3 */
 
 static int eth_nxp_s32_init(const struct device *dev)
 {

samples/subsys/llext/shell_loader/sample.yaml

@@ -3,7 +3,7 @@ common:
   arch_allow:
     - arm
     - xtensa
-  filter: not CONFIG_MPU and not CONFIG_MMU and not CONFIG_SOC_SERIES_S32ZE_R52
+  filter: not CONFIG_MPU and not CONFIG_MMU and not CONFIG_SOC_SERIES_S32ZE
   platform_exclude:
     - numaker_pfm/m487 # See #63167
 sample:

soc/nxp/s32/Kconfig

@@ -1,15 +1,8 @@
-# Copyright 2022-2023 NXP
+# Copyright 2022-2024 NXP
 # SPDX-License-Identifier: Apache-2.0
 
-config SOC_FAMILY_NXP_S32
-	bool
-
 if SOC_FAMILY_NXP_S32
 
-config SOC_FAMILY
-	string
-	default "nxp_s32"
-
 config NXP_S32_FUNC_RESET_THRESHOLD
 	int "Functional Reset Escalation threshold"
 	default 15
@@ -33,6 +26,6 @@ config NXP_S32_DEST_RESET_THRESHOLD
 	  written to beforehand.
 	  Default to disabled (hardware reset value).
 
-source "soc/soc_legacy/arm/nxp_s32/*/Kconfig.soc"
+rsource "*/Kconfig"
 
 endif # SOC_FAMILY_NXP_S32

soc/nxp/s32/Kconfig.defconfig

@@ -0,0 +1,8 @@
+# Copyright 2022,2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_FAMILY_NXP_S32
+
+rsource "*/Kconfig.defconfig"
+
+endif # SOC_FAMILY_NXP_S32

soc/nxp/s32/Kconfig.soc

@@ -0,0 +1,10 @@
+# Copyright 2022,2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_FAMILY_NXP_S32
+	bool
+
+config SOC_FAMILY
+	default "nxp_s32" if SOC_FAMILY_NXP_S32
+
+rsource "*/Kconfig.soc"

soc/nxp/s32/common/CMakeLists.txt

@@ -3,4 +3,4 @@
 
 zephyr_include_directories(.)
 zephyr_sources(osif.c)
-zephyr_sources_ifdef(CONFIG_SOC_SERIES_S32K3XX power_soc.c)
+zephyr_sources_ifdef(CONFIG_SOC_SERIES_S32K3 power_soc.c)

soc/nxp/s32/common/osif.c

@@ -8,7 +8,7 @@
 #include <OsIf.h>
 #include <OsIf_Cfg_TypesDef.h>
 
-#if defined(CONFIG_SOC_SERIES_S32K1XX)
+#if defined(CONFIG_SOC_SERIES_S32K1)
 /* Aliases needed to build with different SoC-specific HAL versions */
 #define CPXNUM                  CPxNUM
 #define MSCM_CPXNUM_CPN_MASK    MSCM_CPxNUM_CPN_MASK

soc/nxp/s32/common/power_soc.c

@@ -71,7 +71,7 @@ static int nxp_s32_power_init(void)
 	};
 
 	const Power_Ip_PMC_ConfigType pmc_cfg = {
-#ifdef CONFIG_SOC_SERIES_S32K3XX
+#ifdef CONFIG_SOC_SERIES_S32K3
 		/* PMC Configuration Register (CONFIG) */
 		.ConfigRegister = PMC_CONFIG_LMEN(IS_ENABLED(CONFIG_NXP_S32_PMC_LMEN))
 			| PMC_CONFIG_LMBCTLEN(IS_ENABLED(CONFIG_NXP_S32_PMC_LMBCTLEN)),

soc/nxp/s32/s32k1/CMakeLists.txt

@@ -1,6 +1,8 @@
-# Copyright 2023 NXP
+# Copyright 2023-2024 NXP
 # SPDX-License-Identifier: Apache-2.0
 
+zephyr_include_directories(.)
+
 set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
 
 zephyr_sources(soc.c)

soc/nxp/s32/s32k1/Kconfig

@@ -0,0 +1,124 @@
+# NXP S32K1XX MCUs series
+
+# Copyright 2023-2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_S32K1
+	select ARM
+	select HAS_NXP_S32_HAL
+	select HAS_MCUX
+	select CPU_HAS_NXP_MPU
+	select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
+	select MPU_ALLOW_FLASH_WRITE if !XIP
+	select CLOCK_CONTROL
+	select HAS_MCUX_LPUART
+	select HAS_MCUX_LPI2C
+	select HAS_MCUX_LPSPI
+	select HAS_MCUX_FTM
+	select HAS_MCUX_FLEXCAN
+	select HAS_MCUX_WDOG32
+	select HAS_MCUX_RTC
+
+config SOC_S32K116
+	select CPU_CORTEX_M0PLUS
+
+config SOC_S32K118
+	select CPU_CORTEX_M0PLUS
+
+config SOC_S32K142
+	select CPU_CORTEX_M4
+	select CPU_CORTEX_M_HAS_DWT
+	select CPU_HAS_FPU
+	select HAS_MCUX_CACHE
+
+config SOC_S32K142W
+	select CPU_CORTEX_M4
+	select CPU_CORTEX_M_HAS_DWT
+	select CPU_HAS_FPU
+	select HAS_MCUX_CACHE
+
+config SOC_S32K144
+	select CPU_CORTEX_M4
+	select CPU_CORTEX_M_HAS_DWT
+	select CPU_HAS_FPU
+	select HAS_MCUX_CACHE
+
+config SOC_S32K144W
+	select CPU_CORTEX_M4
+	select CPU_CORTEX_M_HAS_DWT
+	select CPU_HAS_FPU
+	select HAS_MCUX_CACHE
+
+config SOC_S32K146
+	select CPU_CORTEX_M4
+	select CPU_CORTEX_M_HAS_DWT
+	select CPU_HAS_FPU
+	select HAS_MCUX_CACHE
+
+config SOC_S32K148
+	select CPU_CORTEX_M4
+	select CPU_CORTEX_M_HAS_DWT
+	select CPU_HAS_FPU
+	select HAS_MCUX_CACHE
+
+if SOC_SERIES_S32K1
+
+config WDOG_INIT
+	bool
+	default y
+
+config NXP_S32_FLASH_CONFIG
+	bool "NXP S32 flash configuration field"
+	default y if XIP && !BOOTLOADER_MCUBOOT
+	help
+	  Include the 16-byte flash configuration field that stores default
+	  protection settings (loaded on reset) and security information that
+	  allows the MCU to restrict access to the FTFx module.
+
+if NXP_S32_FLASH_CONFIG
+
+config NXP_S32_FLASH_CONFIG_OFFSET
+	hex "NXP S32 flash configuration field offset"
+	default 0x400
+
+config NXP_S32_FLASH_CONFIG_FSEC
+	hex "Flash security byte (FSEC)"
+	range 0 0xff
+	default 0xfe
+	help
+	  Configures the reset value of the FSEC register, which includes
+	  backdoor key access, mass erase, factory access, and flash security
+	  options.
+
+config NXP_S32_FLASH_CONFIG_FOPT
+	hex "Flash nonvolatile option byte (FOPT)"
+	range 0 0xff
+	default 0xff
+	help
+	  Configures the reset value of the FOPT register, which includes boot,
+	  NMI, and EzPort options.
+
+config NXP_S32_FLASH_CONFIG_FEPROT
+	hex "EEPROM protection byte (FEPROT)"
+	range 0 0xff
+	default 0xff
+	help
+	  Configures the reset value of the FEPROT register for FlexNVM
+	  devices. For program flash only devices, this byte is reserved.
+
+config NXP_S32_FLASH_CONFIG_FDPROT
+	hex "Data flash protection byte (FDPROT)"
+	range 0 0xff
+	default 0xff
+	help
+	  Configures the reset value of the FDPROT register for FlexNVM
+	  devices. For program flash only devices, this byte is reserved.
+
+endif # NXP_S32_FLASH_CONFIG
+
+config NXP_S32_ENABLE_CODE_CACHE
+	bool "Code cache"
+	default y
+	depends on HAS_MCUX_CACHE
+
+endif # SOC_SERIES_S32K1

soc/nxp/s32/s32k1/Kconfig.defconfig

@@ -1,12 +1,9 @@
 # NXP S32K1XX MCU series
 
-# Copyright 2023 NXP
+# Copyright 2023-2024 NXP
 # SPDX-License-Identifier: Apache-2.0
 
-if SOC_SERIES_S32K1XX
+if SOC_SERIES_S32K1
-
-config SOC_SERIES
-	default "s32k1"
 
 config SYS_CLOCK_HW_CYCLES_PER_SEC
 	default 80000000
@@ -15,6 +12,9 @@ config NUM_IRQS
 	default 239 if CPU_CORTEX_M4
 	default 47 if CPU_CORTEX_M0PLUS
 
+config FPU
+	default y if CPU_HAS_FPU
+
 if !XIP
 config FLASH_SIZE
 	default 0
@@ -27,6 +27,4 @@ endif
 config HW_STACK_PROTECTION
 	default y if !USERSPACE
 
-source "soc/soc_legacy/arm/nxp_s32/s32k1/Kconfig.defconfig.s32k1*"
+endif # SOC_SERIES_S32K1
-
-endif # SOC_SERIES_S32K1XX

soc/nxp/s32/s32k1/Kconfig.soc

@@ -1,65 +1,56 @@
-# NXP S32K1XX MCUs line
+# NXP S32K1XX MCUs series
 
-# Copyright 2023 NXP
+# Copyright 2023-2024 NXP
 # SPDX-License-Identifier: Apache-2.0
 
-choice
+config SOC_SERIES_S32K1
-	prompt "NXP S32K1XX MCU selection"
+	bool
-	depends on SOC_SERIES_S32K1XX
+	select SOC_FAMILY_NXP_S32
+
+config SOC_SERIES
+	default "s32k1" if SOC_SERIES_S32K1
 
 config SOC_S32K116
-	bool "S32K116"
+	bool
-	select CPU_CORTEX_M0PLUS
+	select SOC_SERIES_S32K1
 
 config SOC_S32K118
-	bool "S32K118"
+	bool
-	select CPU_CORTEX_M0PLUS
+	select SOC_SERIES_S32K1
 
 config SOC_S32K142
-	bool "S32K142"
+	bool
-	select CPU_CORTEX_M4
+	select SOC_SERIES_S32K1
-	select CPU_CORTEX_M_HAS_DWT
-	select CPU_HAS_FPU
-	select HAS_MCUX_CACHE
 
 config SOC_S32K142W
-	bool "S32K142W"
+	bool
-	select CPU_CORTEX_M4
+	select SOC_SERIES_S32K1
-	select CPU_CORTEX_M_HAS_DWT
-	select CPU_HAS_FPU
-	select HAS_MCUX_CACHE
 
 config SOC_S32K144
-	bool "S32K144"
+	bool
-	select CPU_CORTEX_M4
+	select SOC_SERIES_S32K1
-	select CPU_CORTEX_M_HAS_DWT
-	select CPU_HAS_FPU
-	select HAS_MCUX_CACHE
 
 config SOC_S32K144W
-	bool "S32K144W"
+	bool
-	select CPU_CORTEX_M4
+	select SOC_SERIES_S32K1
-	select CPU_CORTEX_M_HAS_DWT
-	select CPU_HAS_FPU
-	select HAS_MCUX_CACHE
 
 config SOC_S32K146
-	bool "S32K146"
+	bool
-	select CPU_CORTEX_M4
+	select SOC_SERIES_S32K1
-	select CPU_CORTEX_M_HAS_DWT
-	select CPU_HAS_FPU
-	select HAS_MCUX_CACHE
 
 config SOC_S32K148
-	bool "S32K148"
+	bool
-	select CPU_CORTEX_M4
+	select SOC_SERIES_S32K1
-	select CPU_CORTEX_M_HAS_DWT
-	select CPU_HAS_FPU
-	select HAS_MCUX_CACHE
-
-endchoice
 
-if SOC_SERIES_S32K1XX
+config SOC
+	default "s32k116" if SOC_S32K116
+	default "s32k118" if SOC_S32K118
+	default "s32k142" if SOC_S32K142
+	default "s32k142w" if SOC_S32K142W
+	default "s32k144" if SOC_S32K144
+	default "s32k144w" if SOC_S32K144W
+	default "s32k146" if SOC_S32K146
+	default "s32k148" if SOC_S32K148
 
 config SOC_PART_NUMBER_FS32K116LAT0MFMT
 	bool
@@ -298,8 +289,7 @@ config SOC_PART_NUMBER_FS32K148UJT0VMHR
 config SOC_PART_NUMBER_FS32K148UJT0VMHT
 	bool
 
-config SOC_PART_NUMBER_S32K1XX
+config SOC_PART_NUMBER
-	string
 	default "FS32K116LAT0MFMT" if SOC_PART_NUMBER_FS32K116LAT0MFMT
 	default "FS32K116LAT0MLFR" if SOC_PART_NUMBER_FS32K116LAT0MLFR
 	default "FS32K116LAT0MLFT" if SOC_PART_NUMBER_FS32K116LAT0MLFT
@@ -379,67 +369,3 @@ config SOC_PART_NUMBER_S32K1XX
 	default "FS32K148UJT0VLUT" if SOC_PART_NUMBER_FS32K148UJT0VLUT
 	default "FS32K148UJT0VMHR" if SOC_PART_NUMBER_FS32K148UJT0VMHR
 	default "FS32K148UJT0VMHT" if SOC_PART_NUMBER_FS32K148UJT0VMHT
-	help
-	  This string holds the full part number of the SoC. It is a hidden option
-	  that you should not set directly. The part number selection choice defines
-	  the default value for this string.
-
-config WDOG_INIT
-	bool
-	default y
-
-config NXP_S32_FLASH_CONFIG
-	bool "NXP S32 flash configuration field"
-	default y if XIP && !BOOTLOADER_MCUBOOT
-	help
-	  Include the 16-byte flash configuration field that stores default
-	  protection settings (loaded on reset) and security information that
-	  allows the MCU to restrict access to the FTFx module.
-
-if NXP_S32_FLASH_CONFIG
-
-config NXP_S32_FLASH_CONFIG_OFFSET
-	hex "NXP S32 flash configuration field offset"
-	default 0x400
-
-config NXP_S32_FLASH_CONFIG_FSEC
-	hex "Flash security byte (FSEC)"
-	range 0 0xff
-	default 0xfe
-	help
-	  Configures the reset value of the FSEC register, which includes
-	  backdoor key access, mass erase, factory access, and flash security
-	  options.
-
-config NXP_S32_FLASH_CONFIG_FOPT
-	hex "Flash nonvolatile option byte (FOPT)"
-	range 0 0xff
-	default 0xff
-	help
-	  Configures the reset value of the FOPT register, which includes boot,
-	  NMI, and EzPort options.
-
-config NXP_S32_FLASH_CONFIG_FEPROT
-	hex "EEPROM protection byte (FEPROT)"
-	range 0 0xff
-	default 0xff
-	help
-	  Configures the reset value of the FEPROT register for FlexNVM
-	  devices. For program flash only devices, this byte is reserved.
-
-config NXP_S32_FLASH_CONFIG_FDPROT
-	hex "Data flash protection byte (FDPROT)"
-	range 0 0xff
-	default 0xff
-	help
-	  Configures the reset value of the FDPROT register for FlexNVM
-	  devices. For program flash only devices, this byte is reserved.
-
-endif # NXP_S32_FLASH_CONFIG
-
-config NXP_S32_ENABLE_CODE_CACHE
-	bool "Code cache"
-	default y
-	depends on HAS_MCUX_CACHE
-
-endif # SOC_SERIES_S32K1XX

soc/nxp/s32/s32k3/CMakeLists.txt

@@ -1,8 +1,10 @@
-# Copyright 2023 NXP
+# Copyright 2023-2024 NXP
 # SPDX-License-Identifier: Apache-2.0
 
 zephyr_library()
 
+zephyr_include_directories(.)
+
 zephyr_library_sources(soc.c)
 zephyr_library_sources_ifdef(CONFIG_CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS mpu_regions.c)
 zephyr_linker_sources(SECTIONS sections.ld)

soc/nxp/s32/s32k3/Kconfig

@@ -1,29 +1,28 @@
 # NXP S32K3XX MCU series
 
-# Copyright 2023 NXP
+# Copyright 2023-2024 NXP
 # SPDX-License-Identifier: Apache-2.0
 
-choice
+config SOC_SERIES_S32K3
-	prompt "NXP S32K3XX MCU selection"
+	select ARM
-	depends on SOC_SERIES_S32K3XX
+	select CPU_CORTEX_M7
-
+	select HAS_NXP_S32_HAL
-config SOC_S32K344
+	select CPU_HAS_FPU
-	bool "s32k344"
+	select CPU_HAS_ARM_MPU
-
+	select CPU_HAS_ICACHE
-endchoice
+	select CPU_HAS_DCACHE
-
+	select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
-if SOC_SERIES_S32K3XX
+	select PLATFORM_SPECIFIC_INIT if XIP
-
+	select USE_DT_CODE_PARTITION if XIP
-config SOC_PART_NUMBER_PS32K344EHVPBS
+	select CLOCK_CONTROL
-	bool
+	select HAS_MCUX
-
+	select HAS_MCUX_LPUART
-config SOC_PART_NUMBER
+	select HAS_MCUX_FLEXCAN
-	string
+	select HAS_MCUX_LPI2C
-	default "PS32K344EHVPBS" if SOC_PART_NUMBER_PS32K344EHVPBS
+	select HAS_MCUX_LPSPI
-	help
+	select HAS_MCUX_CACHE
-	  This string holds the full part number of the SoC. It is a hidden option
+
-	  that you should not set directly. The part number selection choice defines
+if SOC_SERIES_S32K3
-	  the default value for this string.
 
 config IVT_HEADER_OFFSET
 	hex
@@ -58,4 +57,4 @@ config NXP_S32_PMC_LMBCTLEN
 	  VRC_CTRL pin and is controlled by the PMC to regulate a voltage of
 	  1.5V on V15 pin.
 
-endif
+endif # SOC_SERIES_S32K3

soc/nxp/s32/s32k3/Kconfig.defconfig

@@ -3,10 +3,7 @@
 # Copyright 2023-2024 NXP
 # SPDX-License-Identifier: Apache-2.0
 
-if SOC_SERIES_S32K3XX
+if SOC_SERIES_S32K3
-
-config SOC_SERIES
-	default "s32k3"
 
 config SYS_CLOCK_HW_CYCLES_PER_SEC
 	default 2000000
@@ -15,6 +12,9 @@ config NUM_IRQS
 	# must be >= the highest interrupt number used
 	default 239
 
+config FPU
+	default y
+
 if !XIP
 config FLASH_SIZE
 	default 0
@@ -35,6 +35,4 @@ endif # NET_L2_ETHERNET
 config CACHE_MANAGEMENT
 	default y
 
-source "soc/soc_legacy/arm/nxp_s32/s32k3/Kconfig.defconfig.s32k*"
+endif # SOC_SERIES_S32K3
-
-endif # SOC_SERIES_S32K3XX

soc/nxp/s32/s32k3/Kconfig.soc

@@ -0,0 +1,24 @@
+# NXP S32K3XX MCU series
+
+# Copyright 2023-2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_S32K3
+	bool
+	select SOC_FAMILY_NXP_S32
+
+config SOC_SERIES
+	default "s32k3" if SOC_SERIES_S32K3
+
+config SOC_S32K344
+	bool
+	select SOC_SERIES_S32K3
+
+config SOC
+	default "s32k344" if SOC_S32K344
+
+config SOC_PART_NUMBER_PS32K344EHVPBS
+	bool
+
+config SOC_PART_NUMBER
+	default "PS32K344EHVPBS" if SOC_PART_NUMBER_PS32K344EHVPBS

soc/nxp/s32/s32ze/CMakeLists.txt

@@ -1,6 +1,8 @@
-# Copyright 2022 NXP
+# Copyright 2022,2024 NXP
 # SPDX-License-Identifier: Apache-2.0
 
+zephyr_include_directories(.)
+
 zephyr_library_sources(
   soc.c
 )

soc/nxp/s32/s32ze/Kconfig

@@ -0,0 +1,30 @@
+# NXP S32ZE MCUs series
+
+# Copyright 2022-2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_S32ZE
+	select ARM
+	select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS
+	select CPU_CORTEX_R52
+	select CPU_HAS_DCLS
+	select CPU_HAS_ARM_MPU
+	select GIC_SINGLE_SECURITY_STATE
+	select VFP_DP_D16
+	select PLATFORM_SPECIFIC_INIT
+	select CLOCK_CONTROL
+	select HAS_NXP_S32_HAL
+	select HAS_MCUX
+	select HAS_MCUX_PIT
+
+if SOC_SERIES_S32ZE
+
+config NXP_S32_RTU_INDEX
+	int
+	range 0 1
+	default 0 if SOC_S32Z270_RTU0
+	default 1 if SOC_S32Z270_RTU1
+	help
+	  This option indicates the index of the target RTU (Real-Time Unit) subsystem.
+
+endif # SOC_SERIES_S32ZE

soc/nxp/s32/s32ze/Kconfig.defconfig

@@ -1,12 +1,9 @@
-# NXP S32Z/E MCUs family default configuration
+# NXP S32ZE MCUs series
 
-# Copyright 2022 NXP
+# Copyright 2022,2024 NXP
 # SPDX-License-Identifier: Apache-2.0
 
-if SOC_SERIES_S32ZE_R52
+if SOC_SERIES_S32ZE
-
-config SOC_SERIES
-	default "s32ze"
 
 config NUM_IRQS
 	# must be >= the highest interrupt number used
@@ -40,6 +37,4 @@ config NET_UDP_CHECKSUM
 
 endif # NET_L2_ETHERNET
 
-source "soc/soc_legacy/arm/nxp_s32/s32ze/Kconfig.defconfig.s32*"
+endif # SOC_SERIES_S32ZE
-
-endif # SOC_SERIES_S32ZE_R52

soc/nxp/s32/s32ze/Kconfig.soc

@@ -0,0 +1,32 @@
+# NXP S32ZE MCUs series
+
+# Copyright 2022-2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_S32ZE
+	bool
+	select SOC_FAMILY_NXP_S32
+
+config SOC_SERIES
+	default "s32ze" if SOC_SERIES_S32ZE
+
+config SOC_S32Z270
+	bool
+	select SOC_SERIES_S32ZE
+
+config SOC_S32Z270_RTU0
+	bool
+	select SOC_S32Z270
+
+config SOC_S32Z270_RTU1
+	bool
+	select SOC_S32Z270
+
+config SOC
+	default "s32z270" if SOC_S32Z270
+
+config SOC_PART_NUMBER_P32Z270ADCK0MJFT
+	bool
+
+config SOC_PART_NUMBER
+	default "P32Z270ADCK0MJFT" if SOC_PART_NUMBER_P32Z270ADCK0MJFT

soc/nxp/s32/s32ze/soc.h

@@ -1,5 +1,5 @@
 /*
- * Copyright 2022-2023 NXP
+ * Copyright 2022-2024 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -10,7 +10,7 @@
 /* Do not let CMSIS to handle GIC */
 #define __GIC_PRESENT 0
 
-#if defined(CONFIG_SOC_S32Z27_R52)
+#if defined(CONFIG_SOC_S32Z270)
 #include <S32Z2.h>
 #else
 #error "SoC not supported"

soc/nxp/s32/soc.yml

@@ -0,0 +1,22 @@
+family:
+- name: nxp_s32
+  series:
+  - name: s32k1
+    socs:
+    - name: s32k116
+    - name: s32k118
+    - name: s32k142
+    - name: s32k142w
+    - name: s32k144
+    - name: s32k144w
+    - name: s32k146
+    - name: s32k148
+  - name: s32k3
+    socs:
+    - name: s32k344
+  - name: s32ze
+    socs:
+    - name: s32z270
+      cpuclusters:
+      - name: rtu0
+      - name: rtu1

soc/soc_legacy/arm/nxp_s32/Kconfig.defconfig

@@ -1,4 +0,0 @@
-# Copyright 2022 NXP
-# SPDX-License-Identifier: Apache-2.0
-
-source "soc/soc_legacy/arm/nxp_s32/*/Kconfig.defconfig.series"

soc/soc_legacy/arm/nxp_s32/Kconfig.soc

@@ -1,4 +0,0 @@
-# Copyright 2022 NXP
-# SPDX-License-Identifier: Apache-2.0
-
-source "soc/soc_legacy/arm/nxp_s32/*/Kconfig.series"

soc/soc_legacy/arm/nxp_s32/s32k1/Kconfig.defconfig.s32k146

@@ -1,14 +0,0 @@
-# NXP S32K146
-
-# Copyright 2023 NXP
-# SPDX-License-Identifier: Apache-2.0
-
-if SOC_S32K146
-
-config SOC
-	default "s32k146"
-
-config FPU
-	default y
-
-endif # SOC_S32K146

soc/soc_legacy/arm/nxp_s32/s32k1/Kconfig.series

@@ -1,24 +0,0 @@
-# NXP S32K1XX MCU series
-
-# Copyright 2023-2024 NXP
-# SPDX-License-Identifier: Apache-2.0
-
-config SOC_SERIES_S32K1XX
-	bool "NXP S32K1XX MCU series"
-	select ARM
-	select SOC_FAMILY_NXP_S32
-	select HAS_NXP_S32_HAL
-	select HAS_MCUX
-	select CPU_HAS_NXP_MPU
-	select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
-	select MPU_ALLOW_FLASH_WRITE if !XIP
-	select CLOCK_CONTROL
-	select HAS_MCUX_LPUART
-	select HAS_MCUX_LPI2C
-	select HAS_MCUX_LPSPI
-	select HAS_MCUX_FTM
-	select HAS_MCUX_FLEXCAN
-	select HAS_MCUX_WDOG32
-	select HAS_MCUX_RTC
-	help
-	  Enable support for NXP S32K1XX MCU series.

soc/soc_legacy/arm/nxp_s32/s32k3/Kconfig.defconfig.s32k344

@@ -1,14 +0,0 @@
-# NXP S32K344
-
-# Copyright 2023 NXP
-# SPDX-License-Identifier: Apache-2.0
-
-if SOC_S32K344
-
-config SOC
-	default "s32k344"
-
-config FPU
-	default y
-
-endif # SOC_S32K344

soc/soc_legacy/arm/nxp_s32/s32k3/Kconfig.series

@@ -1,27 +0,0 @@
-# NXP S32K3XX MCU series
-
-# Copyright 2023 NXP
-# SPDX-License-Identifier: Apache-2.0
-
-config SOC_SERIES_S32K3XX
-	bool "NXP S32K3XX MCU series"
-	select ARM
-	select CPU_CORTEX_M7
-	select SOC_FAMILY_NXP_S32
-	select HAS_NXP_S32_HAL
-	select CPU_HAS_FPU
-	select CPU_HAS_ARM_MPU
-	select CPU_HAS_ICACHE
-	select CPU_HAS_DCACHE
-	select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
-	select PLATFORM_SPECIFIC_INIT if XIP
-	select USE_DT_CODE_PARTITION if XIP
-	select CLOCK_CONTROL
-	select HAS_MCUX
-	select HAS_MCUX_LPUART
-	select HAS_MCUX_FLEXCAN
-	select HAS_MCUX_LPI2C
-	select HAS_MCUX_LPSPI
-	select HAS_MCUX_CACHE
-	help
-	  Enable support for NXP S32K3XX MCU series.

soc/soc_legacy/arm/nxp_s32/s32ze/Kconfig.defconfig.s32z27

@@ -1,9 +0,0 @@
-# Copyright 2022 NXP
-# SPDX-License-Identifier: Apache-2.0
-
-if SOC_S32Z27_R52
-
-config SOC
-	default "s32z27"
-
-endif # SOC_S32Z27_R52

soc/soc_legacy/arm/nxp_s32/s32ze/Kconfig.series

@@ -1,21 +0,0 @@
-# NXP S32Z/E MCUs family
-
-# Copyright 2022-2023 NXP
-# SPDX-License-Identifier: Apache-2.0
-
-config SOC_SERIES_S32ZE_R52
-	bool "NXP S32Z/E series"
-	select ARM
-	select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS
-	select CPU_CORTEX_R52
-	select CPU_HAS_DCLS
-	select CPU_HAS_ARM_MPU
-	select GIC_SINGLE_SECURITY_STATE
-	select VFP_DP_D16
-	select PLATFORM_SPECIFIC_INIT
-	select SOC_FAMILY_NXP_S32
-	select CLOCK_CONTROL
-	select HAS_MCUX
-	select HAS_MCUX_PIT
-	help
-	  Enable support for NXP S32Z/E MCUs family on Cortex-R52 cores.

soc/soc_legacy/arm/nxp_s32/s32ze/Kconfig.soc

@@ -1,35 +0,0 @@
-# NXP S32Z/E MCUs family
-
-# Copyright 2022-2023 NXP
-# SPDX-License-Identifier: Apache-2.0
-
-choice
-	prompt "NXP S32Z/E MCUs family SoC selection"
-	depends on SOC_SERIES_S32ZE_R52
-
-config SOC_S32Z27_R52
-	bool "SOC_S32Z27_R52"
-	select HAS_NXP_S32_HAL
-
-endchoice
-
-if SOC_SERIES_S32ZE_R52
-
-config SOC_PART_NUMBER_S32Z27
-	bool
-
-config SOC_PART_NUMBER
-	string
-	default "S32Z27" if SOC_PART_NUMBER_S32Z27
-	help
-	  This string holds the full part number of the SoC. It is a hidden option
-	  that you should not set directly. The part number selection choice defines
-	  the default value for this string.
-
-config NXP_S32_RTU_INDEX
-	int
-	range 0 1
-	help
-	  This option indicates the index of the target RTU (Real-Time Unit) subsystem.
-
-endif # SOC_SERIES_S32ZE_R52

subsys/testsuite/Kconfig

@@ -143,7 +143,7 @@ config TEST_ENABLE_USERSPACE
 config TEST_USERSPACE_WITHOUT_HW_STACK_PROTECTION
 	bool "Run User Mode tests without additionally enabling stack protection"
 	depends on TEST_ENABLE_USERSPACE
-	default y if SOC_SERIES_KINETIS_KE1XF || SOC_SERIES_S32K1XX
+	default y if SOC_SERIES_KINETIS_KE1XF || SOC_SERIES_S32K1
 	help
 	  A HW platform might not have sufficient MPU/MMU capabilities to support
 	  running all test cases with User Mode and HW Stack Protection features

tests/subsys/llext/hello_world/testcase.yaml

@@ -8,7 +8,7 @@ common:
 tests:
   llext.simple.readonly:
     arch_exclude: xtensa # for now
-    filter: not CONFIG_MPU and not CONFIG_MMU and not CONFIG_SOC_SERIES_S32ZE_R52
+    filter: not CONFIG_MPU and not CONFIG_MMU and not CONFIG_SOC_SERIES_S32ZE
     extra_configs:
       - arch:arm:CONFIG_ARM_MPU=n
       - CONFIG_LLEXT_STORAGE_WRITABLE=n
@@ -19,7 +19,7 @@ tests:
       - CONFIG_USERSPACE=y
       - CONFIG_LLEXT_STORAGE_WRITABLE=n
   llext.simple.writable:
-    filter: not CONFIG_MPU and not CONFIG_MMU and not CONFIG_SOC_SERIES_S32ZE_R52
+    filter: not CONFIG_MPU and not CONFIG_MMU and not CONFIG_SOC_SERIES_S32ZE
     extra_configs:
       - arch:arm:CONFIG_ARM_MPU=n
       - CONFIG_LLEXT_STORAGE_WRITABLE=y