soc: fvp_aemv8*: Port to HWMv2

Ports the fvp_aemv8* SoC configuration to hardware model version 2

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>

soc/arm64/arm/CMakeLists.txt

@@ -1,4 +0,0 @@
-# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved.
-# SPDX-License-Identifier: Apache-2.0
-
-add_subdirectory(${SOC_SERIES})

soc/arm64/arm/Kconfig

@@ -1,16 +0,0 @@
-# ARM LTD SoC configuration options
-
-# Copyright (c) 2016 Linaro Limited
-# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved.
-# SPDX-License-Identifier: Apache-2.0
-
-config SOC_FAMILY_ARM64
-	bool
-
-if SOC_FAMILY_ARM64
-config SOC_FAMILY
-	string
-	default "arm"
-
-source "soc/arm64/arm/*/Kconfig.soc"
-endif # SOC_FAMILY_ARM

soc/arm64/arm/Kconfig.defconfig

@@ -1,7 +0,0 @@
-# ARM LTD SoC configuration options
-
-# Copyright (c) 2016 Linaro Limited
-# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved.
-# SPDX-License-Identifier: Apache-2.0
-
-source "soc/arm64/arm/*/Kconfig.defconfig.series"

soc/arm64/arm/Kconfig.soc

@@ -1,7 +0,0 @@
-# ARM LTD SoC configuration options
-
-# Copyright (c) 2016 Linaro Limited
-# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved.
-# SPDX-License-Identifier: Apache-2.0
-
-source "soc/arm64/arm/*/Kconfig.series"

soc/arm64/arm/fvp_aemv8a/Kconfig.soc

@@ -1,12 +0,0 @@
-# Copyright (c) 2021 Carlo Caione <ccaione@baylibre.com>
-# SPDX-License-Identifier: Apache-2.0
-
-choice
-	prompt "ARM FVP AEMv8A AArch64 SoCs"
-	depends on SOC_SERIES_FVP_AEMV8A
-
-config SOC_FVP_BASE_REVC_2XAEMV8A
-	bool "ARM FVP Base RevC 2xAEMv8A AArch64 simulation"
-	select CPU_CORTEX_A53
-
-endchoice

soc/v2/arm/CMakeLists.txt

@@ -0,0 +1,4 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory(${SOC_SERIES})

soc/v2/arm/Kconfig

@@ -0,0 +1,4 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+rsource "*/Kconfig"

soc/v2/arm/Kconfig.defconfig

@@ -0,0 +1,8 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_FAMILY_ARM64
+
+rsource "*/Kconfig.defconfig"
+
+endif # SOC_FAMILY_ARM64

soc/v2/arm/Kconfig.soc

@@ -0,0 +1,10 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_FAMILY_ARM64
+	bool
+
+config SOC_FAMILY
+	default "arm64" if SOC_FAMILY_ARM64
+
+rsource "*/Kconfig.soc"

soc/v2/arm/fvp_aemv8a/CMakeLists.txt

@@ -3,4 +3,6 @@
 
 zephyr_library_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c)
 
+zephyr_include_directories(.)
+
 set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "")

soc/v2/arm/fvp_aemv8a/Kconfig

@@ -2,8 +2,9 @@
 # SPDX-License-Identifier: Apache-2.0
 
 config SOC_SERIES_FVP_AEMV8A
-	bool "ARM FVP AEMv8A AArch64 Series"
 	select ARM64
-	select SOC_FAMILY_ARM64
 	help
 	  Enable support for ARM FVP AEMv8A AArch64 Series
+
+config SOC_FVP_BASE_REVC_2XAEMV8A
+	select CPU_CORTEX_A53

soc/v2/arm/fvp_aemv8a/Kconfig.defconfig

@@ -3,9 +3,6 @@
 
 if SOC_SERIES_FVP_AEMV8A
 
-config SOC_SERIES
-	default "fvp_aemv8a"
-
 config SYS_CLOCK_HW_CYCLES_PER_SEC
 	default 100000000
 
@@ -15,9 +12,6 @@ config NUM_IRQS
 
 if SOC_FVP_BASE_REVC_2XAEMV8A
 
-config SOC
-	default "fvp_base_revc_2xaemv8a"
-
 # Workaround for not being able to have commas in macro arguments
 DT_CHOSEN_Z_FLASH := zephyr,flash
 

soc/v2/arm/fvp_aemv8a/Kconfig.soc

@@ -0,0 +1,15 @@
+# Copyright (c) 2021 Carlo Caione <ccaione@baylibre.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_FVP_AEMV8A
+	bool
+	select SOC_FAMILY_ARM64
+
+config SOC_FVP_BASE_REVC_2XAEMV8A
+	bool
+
+config SOC
+	default "fvp_base_revc_2xaemv8a" if SOC_FVP_BASE_REVC_2XAEMV8A
+
+config SOC_SERIES
+	default "fvp_aemv8a" if SOC_SERIES_FVP_AEMV8A

soc/v2/arm/fvp_aemv8r/CMakeLists.txt

@@ -6,4 +6,6 @@ zephyr_library_sources(
 
 zephyr_library_sources_ifdef(CONFIG_ARM_MPU arm_mpu_regions.c)
 
+zephyr_include_directories(.)
+
 set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "")

soc/v2/arm/fvp_aemv8r/Kconfig

@@ -2,8 +2,12 @@
 # SPDX-License-Identifier: Apache-2.0
 
 config SOC_SERIES_FVP_AEMV8R
-	bool "ARM FVP AEMv8R AArch64 Series"
 	select ARM64
-	select SOC_FAMILY_ARM64
 	help
 	  Enable support for ARM FVP AEMv8R AArch64 Series
+
+config SOC_FVP_AEMV8R_AARCH64
+	select SOC_SERIES_FVP_AEMV8R
+	select CPU_CORTEX_R82
+	select CPU_HAS_MPU
+	select GIC_SINGLE_SECURITY_STATE

soc/v2/arm/fvp_aemv8r/Kconfig.defconfig

@@ -3,9 +3,6 @@
 
 if SOC_SERIES_FVP_AEMV8R
 
-config SOC_SERIES
-	default "fvp_aemv8r"
-
 config SYS_CLOCK_HW_CYCLES_PER_SEC
 	default 100000000
 
@@ -14,9 +11,6 @@ config NUM_IRQS
 
 if SOC_FVP_AEMV8R_AARCH64
 
-config SOC
-	default "fvp_aemv8r_aarch64"
-
 # Workaround for not being able to have commas in macro arguments
 DT_CHOSEN_Z_FLASH := zephyr,flash
 

soc/v2/arm/fvp_aemv8r/Kconfig.soc

@@ -1,17 +1,12 @@
 # Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved.
 # SPDX-License-Identifier: Apache-2.0
 
-choice
+config SOC_SERIES_FVP_AEMV8R
-	prompt "ARM FVP AEMv8R AArch64 SoCs"
+	bool
-	depends on SOC_SERIES_FVP_AEMV8R
+	select SOC_FAMILY_ARM64
 
 config SOC_FVP_AEMV8R_AARCH64
-	bool "ARM FVP AEMv8R aarch64 simulation"
+	bool
-	select CPU_CORTEX_R82
-	select CPU_HAS_MPU
-	select GIC_SINGLE_SECURITY_STATE
-
-endchoice
 
 config SOC_FVP_AEMV8R_SIMULATE_CPU_PM
 	bool "Simulate CPU Power Management for FVP_BaseR_AEMv8R"
@@ -21,3 +16,9 @@ config SOC_FVP_AEMV8R_SIMULATE_CPU_PM
 	  FVP_BaseR_AEMv8R. When zephyr kernel try to bring up secondary
 	  core through pm_cpu_on(), it always succeeds because
 	  it indeed bring up secondary core successfully.
+
+config SOC_SERIES
+	default "fvp_aemv8r" if SOC_SERIES_FVP_AEMV8R
+
+config SOC
+	default "fvp_aemv8r_aarch64" if SOC_FVP_AEMV8R_AARCH64

soc/v2/arm/soc.yml

@@ -0,0 +1,9 @@
+family:
+- name: arm64
+  series:
+  - name: fvp_aemv8a
+    socs:
+    - name: fvp_base_revc_2xaemv8a
+  - name: fvp_aemv8r
+    socs:
+    - name: fvp_aemv8r_aarch64