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drivers: gpio: Add support for RZ/A3UL

Add GPIO driver support for RZ/A3UL

Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Signed-off-by: Quang Le <quang.le.eb@bp.renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
pull/87318/head
Nhut Nguyen 4 months ago committed by Benjamin Cabé
parent
commit
16c77ba448
  1. 1
      boards/renesas/rza3ul_smarc/rza3ul_smarc.dts
  2. 7
      drivers/gpio/Kconfig.renesas_rz
  3. 62
      drivers/gpio/gpio_renesas_rz.c
  4. 17
      drivers/gpio/gpio_renesas_rz.h
  5. 211
      dts/arm64/renesas/rz/rza/r9a07g063.dtsi
  6. 34
      include/zephyr/dt-bindings/gpio/renesas-rz-gpio.h
  7. 26
      tests/drivers/gpio/gpio_api_1pin/boards/rza3ul_smarc.overlay
  8. 1
      tests/drivers/gpio/gpio_basic_api/boards/rza3ul_smarc.conf
  9. 21
      tests/drivers/gpio/gpio_basic_api/boards/rza3ul_smarc.overlay

1
boards/renesas/rza3ul_smarc/rza3ul_smarc.dts

@ -7,6 +7,7 @@ @@ -7,6 +7,7 @@
#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
#include <zephyr/dt-bindings/input/input-event-codes.h>
#include <zephyr/dt-bindings/gpio/renesas-rz-gpio.h>
#include <freq.h>
#include <arm64/renesas/rz/rza/r9a07g063.dtsi>
#include "rza3ul_smarc-pinctrl.dtsi"

7
drivers/gpio/Kconfig.renesas_rz

@ -8,3 +8,10 @@ config GPIO_RENESAS_RZ @@ -8,3 +8,10 @@ config GPIO_RENESAS_RZ
select USE_RZ_FSP_IOPORT
help
Enable Renesas RZ series gpio driver.
config GPIO_RENESAS_RZ_HAS_GPIO_INTERRUPT
bool
default y
depends on DT_HAS_RENESAS_RZ_GPIO_INT_ENABLED
help
GPIO pins can generate interrupts at port mode.

62
drivers/gpio/gpio_renesas_rz.c

@ -15,7 +15,7 @@ @@ -15,7 +15,7 @@
#include <zephyr/drivers/gpio/gpio_utils.h>
#include "gpio_renesas_rz.h"
#include <zephyr/logging/log.h>
#if defined(CONFIG_SOC_SERIES_RZN2L) || defined(CONFIG_SOC_SERIES_RZT2L)
#if defined(CONFIG_RENESAS_RZ_EXT_IRQ)
#include "r_icu.h"
#include <zephyr/drivers/interrupt_controller/intc_rz_ext_irq.h>
#endif
@ -33,7 +33,7 @@ struct gpio_rz_config { @@ -33,7 +33,7 @@ struct gpio_rz_config {
const ioport_api_t *fsp_api;
const struct device *int_dev;
uint8_t int_num[GPIO_RZ_MAX_INT_NUM];
#if defined(CONFIG_SOC_SERIES_RZN2L) || defined(CONFIG_SOC_SERIES_RZT2L)
#if defined(CONFIG_RENESAS_RZ_EXT_IRQ)
const struct device *eirq_dev[GPIO_RZ_MAX_INT_NUM];
void (*cb_list[GPIO_RZ_MAX_INT_NUM])(void *arg);
@ -45,7 +45,7 @@ struct gpio_rz_data { @@ -45,7 +45,7 @@ struct gpio_rz_data {
sys_slist_t cb;
ioport_instance_ctrl_t *fsp_ctrl;
struct k_spinlock lock;
#if defined(CONFIG_SOC_SERIES_RZN2L) || defined(CONFIG_SOC_SERIES_RZT2L)
#if defined(CONFIG_RENESAS_RZ_EXT_IRQ)
uint8_t pin[GPIO_RZ_MAX_INT_NUM];
#endif
};
@ -287,18 +287,14 @@ static int gpio_rz_port_toggle_bits(const struct device *dev, gpio_port_pins_t p @@ -287,18 +287,14 @@ static int gpio_rz_port_toggle_bits(const struct device *dev, gpio_port_pins_t p
return 0;
}
#define GPIO_RZ_HAS_INTERRUPT \
DT_HAS_COMPAT_STATUS_OKAY(renesas_rz_gpio_int) | \
DT_HAS_COMPAT_STATUS_OKAY(renesas_rz_ext_irq)
#if GPIO_RZ_HAS_INTERRUPT
#if defined(CONFIG_GPIO_RENESAS_RZ_HAS_GPIO_INTERRUPT) || defined(CONFIG_RENESAS_RZ_EXT_IRQ)
static int gpio_rz_int_disable(const struct device *dev, const struct device *gpio_dev,
uint8_t int_num, gpio_pin_t pin)
{
#if defined(CONFIG_SOC_SERIES_RZG3S)
volatile uint32_t *tssr = &R_INTC_IM33->TSSR0;
volatile uint32_t *titsr = &R_INTC_IM33->TITSR0;
volatile uint32_t *tscr = &R_INTC_IM33->TSCR;
#if defined(CONFIG_GPIO_RENESAS_RZ_HAS_GPIO_INTERRUPT)
volatile uint32_t *tssr = &R_INTC->TSSR0;
volatile uint32_t *titsr = &R_INTC->TITSR0;
volatile uint32_t *tscr = &R_INTC->TSCR;
struct gpio_rz_int_data *data = dev->data;
/* Get register offset base on interrupt number. */
@ -319,14 +315,14 @@ static int gpio_rz_int_disable(const struct device *dev, const struct device *gp @@ -319,14 +315,14 @@ static int gpio_rz_int_disable(const struct device *dev, const struct device *gp
data->gpio_mapping[int_num].gpio_dev = NULL;
data->gpio_mapping[int_num].pin = UINT8_MAX;
#elif defined(CONFIG_SOC_SERIES_RZN2L) || defined(CONFIG_SOC_SERIES_RZT2L)
#elif defined(CONFIG_RENESAS_RZ_EXT_IRQ)
const struct gpio_rz_config *gpio_config = gpio_dev->config;
const struct device *eirq_dev = gpio_config->eirq_dev[pin];
if (device_is_ready(eirq_dev)) {
intc_rz_ext_irq_disable(eirq_dev);
}
#endif /* CONFIG_SOC_SERIES_* */
#endif /* CONFIG_RENESAS_RZ_EXT_IRQ */
return 0;
}
@ -340,9 +336,9 @@ static int gpio_rz_int_enable(const struct device *int_dev, const struct device @@ -340,9 +336,9 @@ static int gpio_rz_int_enable(const struct device *int_dev, const struct device
const struct gpio_rz_config *gpio_config = gpio_dev->config;
#if defined(CONFIG_SOC_SERIES_RZG3S)
volatile uint32_t *tssr = &R_INTC_IM33->TSSR0;
volatile uint32_t *titsr = &R_INTC_IM33->TITSR0;
#if defined(CONFIG_GPIO_RENESAS_RZ_HAS_GPIO_INTERRUPT)
volatile uint32_t *tssr = &R_INTC->TSSR0;
volatile uint32_t *titsr = &R_INTC->TITSR0;
struct gpio_rz_int_data *int_data = int_dev->data;
tssr = &tssr[int_num / 4];
@ -356,12 +352,12 @@ static int gpio_rz_int_enable(const struct device *int_dev, const struct device @@ -356,12 +352,12 @@ static int gpio_rz_int_enable(const struct device *int_dev, const struct device
if (irq_type == GPIO_RZ_INT_EDGE_RISING || irq_type == GPIO_RZ_INT_EDGE_FALLING) {
int_data->irq_set_edge |= BIT(int_num);
/* Clear interrupt status. */
R_INTC_IM33->TSCR &= ~BIT(int_num);
R_INTC->TSCR &= ~BIT(int_num);
}
irq_enable(GPIO_RZ_TINT_IRQ_GET(int_num));
int_data->gpio_mapping[int_num].gpio_dev = gpio_dev;
int_data->gpio_mapping[int_num].pin = pin;
#elif defined(CONFIG_SOC_SERIES_RZN2L) || defined(CONFIG_SOC_SERIES_RZT2L)
#elif defined(CONFIG_RENESAS_RZ_EXT_IRQ)
const struct device *eirq_dev = gpio_config->eirq_dev[pin];
struct gpio_rz_data *gpio_data = gpio_dev->data;
@ -372,7 +368,7 @@ static int gpio_rz_int_enable(const struct device *int_dev, const struct device @@ -372,7 +368,7 @@ static int gpio_rz_int_enable(const struct device *int_dev, const struct device
intc_rz_ext_irq_set_callback(eirq_dev, gpio_config->cb_list[int_num],
(void *)gpio_dev);
}
#endif /* CONFIG_SOC_SERIES_* */
#endif /* CONFIG_GPIO_RENESAS_RZ_HAS_GPIO_INTERRUPT */
return 0;
}
@ -445,10 +441,10 @@ static int gpio_rz_manage_callback(const struct device *dev, struct gpio_callbac @@ -445,10 +441,10 @@ static int gpio_rz_manage_callback(const struct device *dev, struct gpio_callbac
static void gpio_rz_isr(uint16_t irq, void *param)
{
#if defined(CONFIG_SOC_SERIES_RZG3S)
#if defined(CONFIG_GPIO_RENESAS_RZ_HAS_GPIO_INTERRUPT)
const struct device *dev = param;
struct gpio_rz_int_data *int_data = dev->data;
volatile uint32_t *tscr = &R_INTC_IM33->TSCR;
volatile uint32_t *tscr = &R_INTC->TSCR;
if (!(*tscr & BIT(irq))) {
LOG_DEV_DBG(dev, "tint:%u spurious irq, status 0", irq);
@ -464,16 +460,16 @@ static void gpio_rz_isr(uint16_t irq, void *param) @@ -464,16 +460,16 @@ static void gpio_rz_isr(uint16_t irq, void *param)
struct gpio_rz_data *gpio_data = gpio_dev->data;
gpio_fire_callbacks(&gpio_data->cb, gpio_dev, BIT(pin));
#elif defined(CONFIG_SOC_SERIES_RZN2L) || defined(CONFIG_SOC_SERIES_RZT2L)
#elif defined(CONFIG_RENESAS_RZ_EXT_IRQ)
const struct device *gpio_dev = (const struct device *)param;
struct gpio_rz_data *gpio_data = gpio_dev->data;
uint8_t pin = gpio_data->pin[irq];
gpio_fire_callbacks(&gpio_data->cb, gpio_dev, BIT(pin));
#endif /* CONFIG_SOC_SERIES_* */
#endif /* CONFIG_GPIO_RENESAS_RZ_HAS_GPIO_INTERRUPT */
}
#endif /* GPIO_RZ_HAS_INTERRUPT */
#endif /* CONFIG_GPIO_RENESAS_RZ_HAS_GPIO_INTERRUPT || CONFIG_RENESAS_RZ_EXT_IRQ */
static DEVICE_API(gpio, gpio_rz_driver_api) = {
.pin_configure = gpio_rz_pin_configure,
@ -485,7 +481,7 @@ static DEVICE_API(gpio, gpio_rz_driver_api) = { @@ -485,7 +481,7 @@ static DEVICE_API(gpio, gpio_rz_driver_api) = {
.port_set_bits_raw = gpio_rz_port_set_bits_raw,
.port_clear_bits_raw = gpio_rz_port_clear_bits_raw,
.port_toggle_bits = gpio_rz_port_toggle_bits,
#if GPIO_RZ_HAS_INTERRUPT
#if defined(CONFIG_GPIO_RENESAS_RZ_HAS_GPIO_INTERRUPT) || defined(CONFIG_RENESAS_RZ_EXT_IRQ)
.pin_interrupt_configure = gpio_rz_pin_interrupt_configure,
.manage_callback = gpio_rz_manage_callback,
#endif
@ -500,7 +496,8 @@ static DEVICE_API(gpio, gpio_rz_driver_api) = { @@ -500,7 +496,8 @@ static DEVICE_API(gpio, gpio_rz_driver_api) = {
#define GPIO_RZ_ALL_ISR_DEFINE(irq_num) LISTIFY(irq_num, GPIO_RZ_ISR_DEFINE, ())
#if defined(CONFIG_SOC_SERIES_RZG3S)
#if defined(CONFIG_GPIO_RENESAS_RZ_HAS_GPIO_INTERRUPT) || defined(CONFIG_RENESAS_RZ_EXT_IRQ)
#if defined(CONFIG_GPIO_RENESAS_RZ_HAS_GPIO_INTERRUPT)
#define GPIO_RZ_INT_DEFINE(inst) .int_dev = DEVICE_DT_GET_OR_NULL(DT_INST(0, renesas_rz_gpio_int))
@ -537,7 +534,7 @@ static int gpio_rz_int_init(const struct device *dev) @@ -537,7 +534,7 @@ static int gpio_rz_int_init(const struct device *dev)
UTIL_DEC(CONFIG_GPIO_INIT_PRIORITY), NULL);
DT_FOREACH_STATUS_OKAY(renesas_rz_gpio_int, GPIO_RZ_INT_INIT)
#elif defined(CONFIG_SOC_SERIES_RZN2L) || defined(CONFIG_SOC_SERIES_RZT2L) && GPIO_RZ_HAS_INTERRUPT
#elif defined(CONFIG_RENESAS_RZ_EXT_IRQ)
GPIO_RZ_ALL_ISR_DEFINE(GPIO_RZ_MAX_INT_NUM)
@ -558,9 +555,12 @@ GPIO_RZ_ALL_ISR_DEFINE(GPIO_RZ_MAX_INT_NUM) @@ -558,9 +555,12 @@ GPIO_RZ_ALL_ISR_DEFINE(GPIO_RZ_MAX_INT_NUM)
#define GPIO_RZ_INT_DEFINE(inst) \
.eirq_dev = {ALL_EIRQ_DEV_GET(inst)}, \
.cb_list = {LISTIFY(GPIO_RZ_MAX_INT_NUM, EIRQ_CB_GET, (,))}
#endif /* CONFIG_GPIO_RENESAS_RZ_HAS_GPIO_INTERRUPT */
#else
#define GPIO_RZ_INT_DEFINE(inst)
#endif /* CONFIG_SOC_SERIES_* */
#endif /* CONFIG_GPIO_RENESAS_RZ_HAS_GPIO_INTERRUPT || CONFIG_RENESAS_RZ_EXT_IRQ */
#define VALUE_2X(i, _) UTIL_X2(i)
#define PIN_IRQ_GET(idx, inst) \
@ -573,7 +573,7 @@ GPIO_RZ_ALL_ISR_DEFINE(GPIO_RZ_MAX_INT_NUM) @@ -573,7 +573,7 @@ GPIO_RZ_ALL_ISR_DEFINE(GPIO_RZ_MAX_INT_NUM)
FOR_EACH_FIXED_ARG(PIN_IRQ_GET, (), inst, \
LISTIFY(DT_INST_PROP_LEN_OR(inst, irqs, 0), VALUE_2X, (,)))
#define RZG_GPIO_PORT_INIT(inst) \
#define RZ_GPIO_PORT_INIT(inst) \
static ioport_cfg_t g_ioport_##inst##_cfg = { \
.number_of_pins = 0, \
.p_pin_cfg_data = NULL, \
@ -599,4 +599,4 @@ GPIO_RZ_ALL_ISR_DEFINE(GPIO_RZ_MAX_INT_NUM) @@ -599,4 +599,4 @@ GPIO_RZ_ALL_ISR_DEFINE(GPIO_RZ_MAX_INT_NUM)
DEVICE_DT_INST_DEFINE(inst, NULL, NULL, &gpio_rz_##inst##_data, &gpio_rz_##inst##_config, \
POST_KERNEL, CONFIG_GPIO_INIT_PRIORITY, &gpio_rz_driver_api);
DT_INST_FOREACH_STATUS_OKAY(RZG_GPIO_PORT_INIT)
DT_INST_FOREACH_STATUS_OKAY(RZ_GPIO_PORT_INIT)

17
drivers/gpio/gpio_renesas_rz.h

@ -11,12 +11,22 @@ @@ -11,12 +11,22 @@
#define GPIO_RZ_INT_UNSUPPORTED 0xF
#if defined(CONFIG_SOC_SERIES_RZG3S)
#if defined(CONFIG_SOC_SERIES_RZG3S) || defined(CONFIG_SOC_SERIES_RZA3UL)
#include <zephyr/dt-bindings/gpio/renesas-rz-gpio.h>
#if defined(CONFIG_SOC_SERIES_RZG3S)
#define GPIO_RZ_IOPORT_P_REG_BASE_GET (&R_GPIO->P_20)
#define GPIO_RZ_IOPORT_PM_REG_BASE_GET (&R_GPIO->PM_20)
#define GPIO_RZ_IOPORT_PFC_REG_BASE_GET (&R_GPIO->PFC_20)
#define GPIO_RZ_TINT_IRQ_OFFSET 429
#define R_INTC R_INTC_IM33
#elif defined(CONFIG_SOC_SERIES_RZA3UL)
#define GPIO_RZ_IOPORT_P_REG_BASE_GET (&R_GPIO->P10)
#define GPIO_RZ_IOPORT_PM_REG_BASE_GET (&R_GPIO->PM10)
#define GPIO_RZ_IOPORT_PFC_REG_BASE_GET (&R_GPIO->PFC10)
#define GPIO_RZ_TINT_IRQ_OFFSET 476
#define R_INTC R_INTC_IA55
#endif
#define GPIO_RZ_IOPORT_P_REG_GET(port, pin) (&GPIO_RZ_IOPORT_P_REG_BASE_GET[port + (pin / 4)])
#define GPIO_RZ_IOPORT_PM_REG_GET(port, pin) (&GPIO_RZ_IOPORT_PM_REG_BASE_GET[port + (pin / 4)])
@ -33,7 +43,6 @@ @@ -33,7 +43,6 @@
#define GPIO_RZ_MAX_PORT_NUM 19
#define GPIO_RZ_MAX_INT_NUM 32
#define GPIO_RZ_TINT_IRQ_OFFSET 429
#define GPIO_RZ_TINT_IRQ_GET(tint_num) (tint_num + GPIO_RZ_TINT_IRQ_OFFSET)
#define GPIO_RZ_INT_EDGE_RISING 0x0
@ -46,8 +55,8 @@ @@ -46,8 +55,8 @@
#define GPIO_RZ_TSSR_OFFSET(irq) ((irq % 4) * 8)
#define GPIO_RZ_TITSR_OFFSET(irq) ((irq % 16) * 2)
#define GPIO_RZ_PIN_CONFIGURE_GET_FILTER(flag) (((flags >> RZG3S_GPIO_FILTER_SHIFT) & 0x1F) << 19U)
#define GPIO_RZ_PIN_CONFIGURE_GET(flag) (((flag >> RZG3S_GPIO_IOLH_SHIFT) & 0x3) << 10U)
#define GPIO_RZ_PIN_CONFIGURE_GET_FILTER(flag) (((flags >> RZ_GPIO_FILTER_SHIFT) & 0x1F) << 19U)
#define GPIO_RZ_PIN_CONFIGURE_GET(flag) (((flag >> RZ_GPIO_IOLH_SHIFT) & 0x3) << 10U)
#define GPIO_RZ_PIN_CONFIGURE_INT_ENABLE IOPORT_CFG_TINT_ENABLE
#define GPIO_RZ_PIN_CONFIGURE_INT_DISABLE (~(IOPORT_CFG_TINT_ENABLE))

211
dts/arm64/renesas/rz/rza/r9a07g063.dtsi

@ -52,6 +52,217 @@ @@ -52,6 +52,217 @@
compatible = "renesas,rza-pinctrl";
reg = <0x11030000 DT_SIZE_K(64)>;
reg-names = "pinctrl";
gpio: gpio-common {
compatible = "renesas,rz-gpio-int";
interrupts =
<GIC_SPI 444 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 445 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 446 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 447 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 448 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 449 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 450 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 451 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 452 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 453 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 454 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 455 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 456 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 457 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 458 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 459 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 460 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 461 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 462 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 463 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 464 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 465 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 466 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 467 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 468 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 469 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 470 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 471 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 472 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 473 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 474 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 475 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
gpio0: gpio@0 {
compatible = "renesas,rz-gpio";
gpio-controller;
#gpio-cells = <2>;
ngpios = <4>;
reg = <0x0>;
status = "disabled";
};
gpio1: gpio@100 {
compatible = "renesas,rz-gpio";
gpio-controller;
#gpio-cells= <2>;
ngpios = <5>;
reg = <0x100>;
status = "disabled";
};
gpio2: gpio@200 {
compatible = "renesas,rz-gpio";
gpio-controller;
#gpio-cells= <2>;
ngpios = <4>;
reg = <0x200>;
status = "disabled";
};
gpio3: gpio@300 {
compatible = "renesas,rz-gpio";
gpio-controller;
#gpio-cells= <2>;
ngpios = <4>;
reg = <0x300>;
status = "disabled";
};
gpio4: gpio@400 {
compatible = "renesas,rz-gpio";
gpio-controller;
#gpio-cells= <2>;
ngpios = <6>;
reg = <0x400>;
status = "disabled";
};
gpio5: gpio@500 {
compatible = "renesas,rz-gpio";
gpio-controller;
#gpio-cells= <2>;
ngpios = <5>;
reg = <0x500>;
status = "disabled";
};
gpio6: gpio@600 {
compatible = "renesas,rz-gpio";
gpio-controller;
#gpio-cells= <2>;
ngpios = <5>;
reg = <0x600>;
status = "disabled";
};
gpio7: gpio@700 {
compatible = "renesas,rz-gpio";
gpio-controller;
#gpio-cells= <2>;
ngpios = <5>;
reg = <0x700>;
status = "disabled";
};
gpio8: gpio@800 {
compatible = "renesas,rz-gpio";
gpio-controller;
#gpio-cells= <2>;
ngpios = <5>;
reg = <0x800>;
status = "disabled";
};
gpio9: gpio@900 {
compatible = "renesas,rz-gpio";
gpio-controller;
#gpio-cells= <2>;
ngpios = <4>;
reg = <0x900>;
status = "disabled";
};
gpio10: gpio@a00 {
compatible = "renesas,rz-gpio";
gpio-controller;
#gpio-cells= <2>;
ngpios = <5>;
reg = <0xa00>;
status = "disabled";
};
gpio11: gpio@b00 {
compatible = "renesas,rz-gpio";
gpio-controller;
#gpio-cells= <2>;
ngpios = <4>;
reg = <0xb00>;
status = "disabled";
};
gpio12: gpio@c00 {
compatible = "renesas,rz-gpio";
gpio-controller;
#gpio-cells= <2>;
ngpios = <2>;
reg = <0xc00>;
status = "disabled";
};
gpio13: gpio@d00 {
compatible = "renesas,rz-gpio";
gpio-controller;
#gpio-cells= <2>;
ngpios = <5>;
reg = <0xd00>;
status = "disabled";
};
gpio14: gpio@e00 {
compatible = "renesas,rz-gpio";
gpio-controller;
#gpio-cells= <2>;
ngpios = <3>;
reg = <0xe00>;
status = "disabled";
};
gpio15: gpio@f00 {
compatible = "renesas,rz-gpio";
gpio-controller;
#gpio-cells= <2>;
ngpios = <4>;
reg = <0xf00>;
status = "disabled";
};
gpio16: gpio@1000 {
compatible = "renesas,rz-gpio";
gpio-controller;
#gpio-cells= <2>;
ngpios = <2>;
reg = <0x1000>;
status = "disabled";
};
gpio17: gpio@1100 {
compatible = "renesas,rz-gpio";
gpio-controller;
#gpio-cells= <2>;
ngpios = <4>;
reg = <0x1100>;
status = "disabled";
};
gpio18: gpio@1200 {
compatible = "renesas,rz-gpio";
gpio-controller;
#gpio-cells=<2>;
ngpios = <6>;
reg = <0x1200>;
status = "disabled";
};
};
};
scif0: serial@1004b800 {

34
include/zephyr/dt-bindings/gpio/renesas-rz-gpio.h

@ -6,37 +6,37 @@ @@ -6,37 +6,37 @@
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RZ_GPIO_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RZ_GPIO_H_
/*********************************RZG3S*****************************************/
/*********************************RZ/A,G,V**************************************/
/**
* @brief RZ G3S specific GPIO Flags
* @brief RZAGV specific GPIO Flags
* The pin driving ability flags are encoded in the 8 upper bits of @ref gpio_dt_flags_t as
* follows:
* - Bit 9..8: Pin driving ability value
* - Bit 11..10: Digital Noise Filter Clock Selection value
* - Bit 13..12: Digital Noise Filter Number value
* - Bit 14: Digital Noise Filter ON/OFF
* - Bit 8..9: Pin driving ability value
* - Bit 10: Digital Noise Filter ON/OFF
* - Bit 11..12: Digital Noise Filter Number value
* - Bit 13..14: Digital Noise Filter Clock Selection value
* example:
* gpio-consumer {
* out-gpios = <&port8 2 (GPIO_PULL_UP | RZG3S_GPIO_FILTER_SET(1, 3, 3))>;
* out-gpios = <&port8 2 (GPIO_PULL_UP | RZ_GPIO_FILTER_SET(1, 3, 3))>;
* };
* gpio-consumer {
* out-gpios = <&port8 2 (GPIO_PULL_UP | RZG3S_GPIO_IOLH_SET(2))>;
* out-gpios = <&port8 2 (GPIO_PULL_UP | RZ_GPIO_IOLH_SET(2))>;
* };
*/
/* GPIO drive IOLH */
#define RZG3S_GPIO_IOLH_SHIFT 7U
#define RZG3S_GPIO_IOLH_SET(iolh_val) (iolh_val << RZG3S_GPIO_IOLH_SHIFT)
#define RZ_GPIO_IOLH_SHIFT 8U
#define RZ_GPIO_IOLH_SET(iolh_val) (iolh_val << RZ_GPIO_IOLH_SHIFT)
/* GPIO filter */
#define RZG3S_GPIO_FILTER_SHIFT 9U
#define RZG3S_GPIO_FILNUM_SHIFT 1U
#define RZG3S_GPIO_FILCLKSEL_SHIFT 3U
#define RZG3S_GPIO_FILTER_SET(fillonoff, filnum, filclksel) \
(((fillonoff) | ((filnum) << RZG3S_GPIO_FILNUM_SHIFT) | \
((filclksel) << RZG3S_GPIO_FILCLKSEL_SHIFT)) \
<< RZG3S_GPIO_FILTER_SHIFT)
#define RZ_GPIO_FILTER_SHIFT 10U
#define RZ_GPIO_FILNUM_SHIFT 1U
#define RZ_GPIO_FILCLKSEL_SHIFT 3U
#define RZ_GPIO_FILTER_SET(fillonoff, filnum, filclksel) \
(((fillonoff) | ((filnum) << RZ_GPIO_FILNUM_SHIFT) | \
((filclksel) << RZ_GPIO_FILCLKSEL_SHIFT)) \
<< RZ_GPIO_FILTER_SHIFT)
/*******************************************************************************/

26
tests/drivers/gpio/gpio_api_1pin/boards/rza3ul_smarc.overlay

@ -0,0 +1,26 @@ @@ -0,0 +1,26 @@
/*
* Copyright (c) 2025 Renesas Electronics Corporation
* SPDX-License-Identifier: Apache-2.0
*/
/ {
aliases {
led0 = &led_0;
};
gpio-led {
compatible = "gpio-leds";
led_0: led_0 {
gpios = <&gpio1 3 0>;
};
};
};
&gpio {
status = "okay";
};
&gpio1 {
irqs = <3 15>;
status = "okay";
};

1
tests/drivers/gpio/gpio_basic_api/boards/rza3ul_smarc.conf

@ -0,0 +1 @@ @@ -0,0 +1 @@
CONFIG_SKIP_PULL_TEST=y

21
tests/drivers/gpio/gpio_basic_api/boards/rza3ul_smarc.overlay

@ -0,0 +1,21 @@ @@ -0,0 +1,21 @@
/*
* Copyright (c) 2025 Renesas Electronics Corporation
* SPDX-License-Identifier: Apache-2.0
*/
/ {
resources {
compatible = "test-gpio-basic-api";
out-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
in-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
};
};
&gpio {
status = "okay";
};
&gpio1 {
irqs = <4 20>;
status = "okay";
};
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