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Add ULP Coprocessor support for ESP32C6. Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>pull/87487/head
Lucas Tamborrino
6 months ago
committed by
Benjamin Cabé
14 changed files with 642 additions and 66 deletions
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/* |
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* Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd. |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#include <mem.h> |
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#include <freq.h> |
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#include <zephyr/dt-bindings/gpio/gpio.h> |
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#include <zephyr/dt-bindings/interrupt-controller/esp-esp32c6-intmux.h> |
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#include <zephyr/dt-bindings/clock/esp32c6_clock.h> |
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#include <dt-bindings/pinctrl/esp32c6-pinctrl.h> |
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/ { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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cpus { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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cpu0: cpu@0 { |
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device_type = "cpu"; |
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compatible = "espressif,riscv"; |
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riscv,isa = "rv32imac_zicsr_zifencei"; |
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reg = <0>; |
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clock-source = <ESP32_RTC_FAST_CLK_SRC_XTAL_D2>; |
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clock-frequency = <DT_FREQ_M(20)>; |
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xtal-freq = <DT_FREQ_M(40)>; |
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}; |
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}; |
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soc { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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compatible = "simple-bus"; |
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ranges; |
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sramlp: memory@50000000 { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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compatible = "mmio-sram"; |
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reg = <0x50000000 DT_SIZE_K(16)>; |
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shmlp: memory@0 { |
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reg = <0x0 0x10>; |
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}; |
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}; |
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flash: flash-controller@60002000 { |
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compatible = "espressif,esp32-flash-controller"; |
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reg = <0x60002000 0x1000>; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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flash0: flash@0 { |
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compatible = "soc-nv-flash"; |
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erase-block-size = <4096>; |
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write-block-size = <4>; |
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/* Flash size is specified in SOC/SIP dtsi */ |
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}; |
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}; |
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}; |
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}; |
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/* |
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* Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd. |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#include "esp32c6_lpcore.dtsi" |
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/* 4MB flash */ |
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&flash0 { |
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reg = <0x0 DT_SIZE_M(4)>; |
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}; |
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# Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd. |
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# SPDX-License-Identifier: Apache-2.0 |
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menu "Ultra Low Power (ULP) Coprocessor" |
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config ULP_COPROC_ENABLED |
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bool "Ultra Low Power (ULP) Coprocessor" |
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help |
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Enable this feature if you plan to use the ULP Coprocessor. |
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Once this option is enabled, further ULP co-processor configuration will appear in the menu. |
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choice ULP_COPROC_TYPE |
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prompt "ULP Coprocessor type" |
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depends on ULP_COPROC_ENABLED |
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default ULP_COPROC_TYPE_LP_CORE if SOC_SERIES_ESP32C6 |
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help |
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Choose the ULP Coprocessor type: ULP FSM (Finite State Machine) or ULP RISC-V. |
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config ULP_COPROC_TYPE_FSM |
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bool "ULP FSM (Finite State Machine)" |
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depends on SOC_SERIES_ESP32 || SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3 |
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config ULP_COPROC_TYPE_RISCV |
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bool "ULP RISC-V" |
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depends on SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3 |
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config ULP_COPROC_TYPE_LP_CORE |
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bool "LP core RISC-V" |
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depends on SOC_SERIES_ESP32C6 |
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endchoice |
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menu "ULP RISC-V Settings" |
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depends on ULP_COPROC_TYPE_RISCV |
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config ULP_RISCV_INTERRUPT_ENABLE |
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bool "ULP RISC-V interrupts" |
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help |
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Turn on this setting to enabled interrupts on the ULP RISC-V core. |
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endmenu |
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menu "ULP Debugging Options" |
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config ULP_PANIC_OUTPUT_ENABLE |
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bool "Panic handler outputs to LP UART" |
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depends on ULP_COPROC_TYPE_LP_CORE |
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help |
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Set this option to enable panic handler functionality. If this option is |
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enabled then the LP Core will output a panic dump over LP UART, |
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similar to what the main core does. Output depends on LP UART already being |
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initialized and configured. |
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Disabling this option will reduce the LP core binary size by not |
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linking in panic handler functionality. |
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config ULP_HP_UART_CONSOLE_PRINT |
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bool "Route lp_core_printf to the console HP-UART" |
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depends on ULP_COPROC_TYPE_LP_CORE |
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help |
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Set this option to route lp_core_printf to the console HP-UART. |
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This allows you to easily view print outputs from the LP core, without |
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having to connect to the LP-UART. This option comes with the following |
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limitations: |
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1. There is no mutual exclusion between the HP-Core and the LP-Core accessing |
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the HP-UART, which means that if both cores are logging heavily the output |
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strings might get mangled together. |
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2. The HP-UART can only work while the HP-Core is running, which means that |
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if the HP-Core is in deep sleep, the LP-Core will not be able to print to the |
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console HP-UART. |
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Due to these limitations it is only recommended to use this option for easy debugging. |
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For more serious use-cases you should use the LP-UART. |
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config ULP_NORESET_UNDER_DEBUG |
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bool "Avoid resetting LP core when debugger is attached" |
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depends on ULP_COPROC_TYPE_LP_CORE |
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default y |
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help |
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Enable this feature to avoid resetting LP core in sleep mode when debugger is attached, |
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otherwise configured HW breakpoints and dcsr.ebreak* bits will be missed. |
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This is a workaround until it will be fixed in HW. |
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endmenu |
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endmenu # Ultra Low Power (ULP) Coprocessor |
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/* |
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* Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd. |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#include <zephyr/devicetree.h> |
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#include <zephyr/linker/sections.h> |
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#include <zephyr/linker/linker-defs.h> |
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#include <zephyr/linker/linker-tool.h> |
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#include "memory.h" |
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#define ALIGN_DOWN(SIZE, AL) (SIZE & ~(AL - 1)) |
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/* Ensure the end where the shared memory starts is aligned to 8 bytes |
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if updating this also update the same in ulp_lp_core_memory_shared.c |
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*/ |
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#define ALIGNED_COPROC_MEM ALIGN_DOWN(ULP_COPROC_RESERVE_MEM, 0x8) |
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#define RODATA_REGION ram |
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#define RAMABLE_REGION ram |
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#define ROMABLE_REGION ram |
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/* User available memory segments */ |
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_aligned_coproc_mem = ALIGNED_COPROC_MEM; |
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_vector_table_org = LPSRAM_IRAM_START; |
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_vector_table_len = 0x80; |
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_ram_org = _vector_table_org + _vector_table_len; |
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_ram_len = _aligned_coproc_mem - _vector_table_len - ULP_SHARED_MEM; |
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_shared_mem_org = _ram_org + _ram_len; |
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_shared_mem_len = ULP_SHARED_MEM; |
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ENTRY(reset_vector) |
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MEMORY |
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{ |
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/*first 128byte for exception/interrupt vectors*/ |
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vector_table(RX) : ORIGIN = _vector_table_org , LENGTH = _vector_table_len |
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ram(RWX) : ORIGIN = _ram_org, LENGTH = _ram_len |
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shared_mem_ram(RW) : ORIGIN = _shared_mem_org, LENGTH = _shared_mem_len |
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} |
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SECTIONS |
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{ |
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.vector.text : |
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{ |
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__mtvec_base = .; |
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KEEP (*(.init.vector .init.vector.*)) |
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} > vector_table |
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. = ORIGIN(ram); |
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.text ALIGN(4): |
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{ |
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*(.text.vectors) /* Default reset vector must link to offset 0x80 */ |
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__text_region_start = ABSOLUTE(.); |
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*(.text) |
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*(.text*) |
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__text_region_end = ABSOLUTE(.); |
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} >ram |
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#include <zephyr/linker/rel-sections.ld> |
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.rodata ALIGN(4): |
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{ |
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__rodata_region_start = ABSOLUTE(.); |
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*(.rodata .srodata) |
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*(.rodata* .srodata*) |
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__rodata_region_end = .; |
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} > ram |
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#include <zephyr/linker/common-rom/common-rom-kernel-devices.ld> |
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.rodata.end ALIGN(4): |
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{ |
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_rodata_reserved_end = ABSOLUTE(.); |
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} > ram |
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.data ALIGN(4): |
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{ |
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_image_ram_start = ABSOLUTE(.); |
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*(.data) |
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*(.data*) |
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*(.sdata) |
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*(.sdata*) |
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} > ram |
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#include <snippets-data-sections.ld> |
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#include <zephyr/linker/common-ram.ld> |
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#include <snippets-ram-sections.ld> |
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.data.end ALIGN(4): |
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{ |
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_image_ram_end = ABSOLUTE(.); |
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} > ram |
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.data.noinit (NOLOAD): |
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{ |
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. = ALIGN(4); |
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*(.noinit) |
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*(.noinit.*) |
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. = ALIGN(4); |
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} > ram |
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.bss ALIGN(4) : |
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{ |
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*(.bss) |
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*(.bss*) |
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*(.sbss) |
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*(.sbss*) |
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PROVIDE(end = .); |
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_heap_sentry = .; |
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} >ram |
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#include <zephyr/linker/ram-end.ld> |
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__stack_top = ORIGIN(ram) + LENGTH(ram); |
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#include <zephyr/linker/debug-sections.ld> |
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SECTION_PROLOGUE(.riscv.attributes, 0,) |
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{ |
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KEEP(*(.riscv.attributes)) |
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KEEP(*(.gnu.attributes)) |
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} |
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. = ORIGIN(shared_mem_ram); |
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.shared_mem (ALIGN(4)) : |
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{ |
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KEEP(*(.shared_mem)) |
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} > shared_mem_ram |
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} |
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/*
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* Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd. |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#include <zephyr/kernel.h> |
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#include "bootloader_flash_priv.h" |
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#include <zephyr/storage/flash_map.h> |
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#include "ulp_lp_core.h" |
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#include "lp_core_uart.h" |
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#include <zephyr/logging/log.h> |
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LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL); |
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void IRAM_ATTR lp_core_image_init(void) |
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{ |
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const uint32_t lpcore_img_off = FIXED_PARTITION_OFFSET(slot0_lpcore_partition); |
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const uint32_t lpcore_img_size = 0x4000; |
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int ret = 0; |
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LOG_INF("Getting LPU image at %p, size %d", (void *)lpcore_img_off, lpcore_img_size); |
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const uint8_t *data = (const uint8_t *)bootloader_mmap(lpcore_img_off, lpcore_img_size); |
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ret = ulp_lp_core_load_binary(data, lpcore_img_size); |
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if (ret) { |
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LOG_ERR("Failed to load LP core image: %d", ret); |
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} |
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LOG_INF("LP core image loaded"); |
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/* Set LP core wakeup source as the HP CPU */ |
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ulp_lp_core_cfg_t cfg = { |
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.wakeup_source = ULP_LP_CORE_WAKEUP_SOURCE_HP_CPU, |
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}; |
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ret = ulp_lp_core_run(&cfg); |
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if (ret) { |
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LOG_ERR("Failed to start LP core: %d", ret); |
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} |
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} |
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void soc_late_init_hook(void) |
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{ |
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lp_core_image_init(); |
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} |
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/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#include "soc/soc_caps.h" |
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#include "esp_rom_caps.h" |
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#include "rom/ets_sys.h" |
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#include "ulp_lp_core_utils.h" |
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#include "ulp_lp_core_lp_timer_shared.h" |
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#include "ulp_lp_core_memory_shared.h" |
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#include "ulp_lp_core_print.h" |
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#include <soc.h> |
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#include <kernel_internal.h> |
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extern void main(void); |
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/* Initialize lp core related system functions before calling user's main*/ |
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void lp_core_startup(void) |
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{ |
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#if CONFIG_ULP_HP_UART_CONSOLE_PRINT && ESP_ROM_HAS_LP_ROM |
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ets_install_putc1(lp_core_print_char); |
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#endif |
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ulp_lp_core_update_wakeup_cause(); |
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/* Start Zephyr */ |
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z_cstart(); |
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CODE_UNREACHABLE; |
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} |
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@@ -0,0 +1,25 @@
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/* |
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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.section .text.vectors |
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.global reset_vector
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/* The reset vector, jumps to startup code */ |
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reset_vector: |
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/* _vector_table: Only 256-byte aligned addresses are allowed */ |
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la t0, _vector_table |
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csrw mtvec, t0 |
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j __start |
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__start: |
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/* setup the stack pointer */ |
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la sp, __stack_top |
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call lp_core_startup |
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loop: |
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j loop |
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@@ -0,0 +1,22 @@
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/* |
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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.section .init.vector,"ax" |
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.global _vector_table
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.type _vector_table, @function
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_vector_table: |
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.option push
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.option norvc
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.rept 30
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j _panic_handler |
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.endr |
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j _interrupt_handler // All interrupts are routed to mtvec + 4*30, i.e. the 31st entry |
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j _panic_handler |
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.option pop
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.size _vector_table, .-_vector_table |
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@ -0,0 +1,142 @@
@@ -0,0 +1,142 @@
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/* |
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#include "riscv/rvruntime-frames.h" |
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#include <soc/soc_caps.h> |
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.equ SAVE_REGS, 32 |
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.equ CONTEXT_SIZE, (SAVE_REGS * 4) |
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/* Macro which first allocates space on the stack to save general |
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* purpose registers, and then save them. GP register is excluded. |
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* The default size allocated on the stack is CONTEXT_SIZE, but it |
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* can be overridden. */ |
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.macro save_general_regs cxt_size=CONTEXT_SIZE |
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addi sp, sp, -\cxt_size |
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sw ra, RV_STK_RA(sp) |
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sw tp, RV_STK_TP(sp) |
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sw t0, RV_STK_T0(sp) |
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sw t1, RV_STK_T1(sp) |
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sw t2, RV_STK_T2(sp) |
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sw s0, RV_STK_S0(sp) |
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sw s1, RV_STK_S1(sp) |
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sw a0, RV_STK_A0(sp) |
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sw a1, RV_STK_A1(sp) |
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sw a2, RV_STK_A2(sp) |
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sw a3, RV_STK_A3(sp) |
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sw a4, RV_STK_A4(sp) |
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sw a5, RV_STK_A5(sp) |
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sw a6, RV_STK_A6(sp) |
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sw a7, RV_STK_A7(sp) |
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sw s2, RV_STK_S2(sp) |
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sw s3, RV_STK_S3(sp) |
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sw s4, RV_STK_S4(sp) |
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sw s5, RV_STK_S5(sp) |
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sw s6, RV_STK_S6(sp) |
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sw s7, RV_STK_S7(sp) |
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sw s8, RV_STK_S8(sp) |
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sw s9, RV_STK_S9(sp) |
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sw s10, RV_STK_S10(sp) |
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sw s11, RV_STK_S11(sp) |
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sw t3, RV_STK_T3(sp) |
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sw t4, RV_STK_T4(sp) |
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sw t5, RV_STK_T5(sp) |
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sw t6, RV_STK_T6(sp) |
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.endm |
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.macro save_mepc
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csrr t0, mepc |
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sw t0, RV_STK_MEPC(sp) |
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.endm |
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/* Restore the general purpose registers (excluding gp) from the context on |
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* the stack. The context is then deallocated. The default size is CONTEXT_SIZE |
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* but it can be overridden. */ |
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.macro restore_general_regs cxt_size=CONTEXT_SIZE |
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lw ra, RV_STK_RA(sp) |
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lw tp, RV_STK_TP(sp) |
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lw t0, RV_STK_T0(sp) |
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lw t1, RV_STK_T1(sp) |
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lw t2, RV_STK_T2(sp) |
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lw s0, RV_STK_S0(sp) |
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lw s1, RV_STK_S1(sp) |
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lw a0, RV_STK_A0(sp) |
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lw a1, RV_STK_A1(sp) |
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lw a2, RV_STK_A2(sp) |
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lw a3, RV_STK_A3(sp) |
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lw a4, RV_STK_A4(sp) |
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lw a5, RV_STK_A5(sp) |
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lw a6, RV_STK_A6(sp) |
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lw a7, RV_STK_A7(sp) |
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lw s2, RV_STK_S2(sp) |
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lw s3, RV_STK_S3(sp) |
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lw s4, RV_STK_S4(sp) |
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lw s5, RV_STK_S5(sp) |
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lw s6, RV_STK_S6(sp) |
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lw s7, RV_STK_S7(sp) |
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lw s8, RV_STK_S8(sp) |
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lw s9, RV_STK_S9(sp) |
||||
lw s10, RV_STK_S10(sp) |
||||
lw s11, RV_STK_S11(sp) |
||||
lw t3, RV_STK_T3(sp) |
||||
lw t4, RV_STK_T4(sp) |
||||
lw t5, RV_STK_T5(sp) |
||||
lw t6, RV_STK_T6(sp) |
||||
addi sp,sp, \cxt_size |
||||
.endm |
||||
|
||||
.macro restore_mepc
|
||||
lw t0, RV_STK_MEPC(sp) |
||||
csrw mepc, t0 |
||||
.endm |
||||
|
||||
|
||||
/* _panic_handler: handle all exception */ |
||||
.section .text.handlers,"ax" |
||||
.global _panic_handler
|
||||
.type _panic_handler, @function
|
||||
_panic_handler: |
||||
save_general_regs RV_STK_FRMSZ |
||||
save_mepc |
||||
|
||||
addi t0, sp, RV_STK_FRMSZ /* Restore sp with the value when trap happened */ |
||||
|
||||
/* Save CSRs */ |
||||
sw t0, RV_STK_SP(sp) |
||||
csrr t0, mstatus |
||||
sw t0, RV_STK_MSTATUS(sp) |
||||
csrr t0, mcause |
||||
sw t0, RV_STK_MCAUSE(sp) |
||||
csrr t0, mtvec |
||||
sw t0, RV_STK_MTVEC(sp) |
||||
csrr t0, mhartid |
||||
sw t0, RV_STK_MHARTID(sp) |
||||
csrr t0, mtval |
||||
sw t0, RV_STK_MTVAL(sp) |
||||
|
||||
csrr a1, mcause /* Exception cause */ |
||||
|
||||
mv a0, sp /* RvExcFrame *regs */ |
||||
call ulp_lp_core_panic_handler |
||||
_end: |
||||
j _end /* loop forever */ |
||||
|
||||
|
||||
/* _interrupt_handler: handle all interrupt */ |
||||
.section .text.handlers,"ax" |
||||
.global _interrupt_handler
|
||||
.type _interrupt_handler, @function
|
||||
_interrupt_handler: |
||||
/* Save registers & mepc to stack */ |
||||
save_general_regs |
||||
save_mepc |
||||
|
||||
call ulp_lp_core_intr_handler |
||||
|
||||
/* Restore registers & mepc from stack */ |
||||
restore_mepc |
||||
restore_general_regs |
||||
/* Exit, this will also re-enable the interrupts */ |
||||
mret |
||||
Loading…
Reference in new issue