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Update interrupt allocator to use the same driver for both Xtensa and RISCV devices. Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com> Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>pull/87800/merge
Raffael Rostagno
5 months ago
committed by
Benjamin Cabé
14 changed files with 107 additions and 552 deletions
@ -1,21 +0,0 @@
@@ -1,21 +0,0 @@
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# Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd. |
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# SPDX-License-Identifier: Apache-2.0 |
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config INTC_ESP32C3 |
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bool "ESP32C3 interrupt controller driver" |
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depends on SOC_FAMILY_ESPRESSIF_ESP32 |
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depends on SOC_SERIES_ESP32C2 || SOC_SERIES_ESP32C3 || SOC_SERIES_ESP32C6 |
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default y |
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help |
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Enables the esp32c3 interrupt controller driver to handle ISR |
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management at SoC level. |
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config INTC_ESP32C3_DECISIONS_LOG |
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bool "Espressif's interrupt allocator logging" |
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depends on INTC_ESP32C3 |
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select LOG |
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help |
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Enable this option to visualize information on decisions made by the |
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interrupt allocator. This has no impact on the interrupt allocator usage |
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but may be valuable for debugging purposes. When enabled, messages are |
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print to the serial console. |
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@ -1,277 +0,0 @@
@@ -1,277 +0,0 @@
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/*
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* Copyright (c) 2021-2025 Espressif Systems (Shanghai) Co., Ltd. |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#include <stdint.h> |
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <stdbool.h> |
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#include <string.h> |
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#include <soc/periph_defs.h> |
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#include <limits.h> |
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#include <assert.h> |
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#include "soc/soc.h" |
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#include <soc.h> |
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#include <zephyr/kernel.h> |
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#include <zephyr/drivers/interrupt_controller/intc_esp32c3.h> |
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#include <zephyr/sw_isr_table.h> |
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#include <riscv/interrupt.h> |
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#include <zephyr/logging/log.h> |
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LOG_MODULE_REGISTER(intc_esp32, CONFIG_LOG_DEFAULT_LEVEL); |
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/*
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* Define this to debug the choices made when allocating the interrupt. This leads to much debugging |
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* output within a critical region, which can lead to weird effects like e.g. the interrupt watchdog |
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* being triggered, that is why it is separate from the normal LOG* scheme. |
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*/ |
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#ifdef CONFIG_INTC_ESP32C3_DECISIONS_LOG |
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# define INTC_LOG(...) LOG_INF(__VA_ARGS__) |
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#else |
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# define INTC_LOG(...) do {} while (0) |
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#endif |
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#define ESP32_INTC_DEFAULT_PRIORITY 15 |
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#define ESP32_INTC_DEFAULT_THRESHOLD 1 |
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#define ESP32_INTC_DISABLED_SLOT 31 |
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#define ESP32_INTC_SRCS_PER_IRQ 2 |
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/* Define maximum interrupt sources per SoC */ |
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#if defined(CONFIG_SOC_SERIES_ESP32C6) |
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/*
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* Interrupt reserved mask |
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* 0 is reserved |
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* 1 is for Wi-Fi |
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* 3, 4 and 7 are unavailable for PULP CPU as they are bound to Core-Local Interrupts (CLINT) |
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*/ |
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#define RSVD_MASK (BIT(0) | BIT(1) | BIT(3) | BIT(4) | BIT(7)) |
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#define ESP_INTC_AVAILABLE_IRQS 31 |
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#else |
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/*
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* Interrupt reserved mask |
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* 1 is for Wi-Fi |
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*/ |
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#define RSVD_MASK (BIT(0) | BIT(1)) |
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#define ESP_INTC_AVAILABLE_IRQS 30 |
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#endif |
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/* Single array for IRQ allocation */ |
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static uint8_t esp_intr_irq_alloc[ESP_INTC_AVAILABLE_IRQS * ESP32_INTC_SRCS_PER_IRQ]; |
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#define ESP_INTR_IDX(irq, slot) ((irq % ESP_INTC_AVAILABLE_IRQS) * ESP32_INTC_SRCS_PER_IRQ + slot) |
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#define STATUS_MASK_NUM 3 |
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static uint32_t esp_intr_enabled_mask[STATUS_MASK_NUM] = {0, 0, 0}; |
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static uint32_t esp_intr_find_irq_for_source(uint32_t source) |
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{ |
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if (source >= ETS_MAX_INTR_SOURCE) { |
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return IRQ_NA; |
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} |
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uint32_t irq = source / ESP32_INTC_SRCS_PER_IRQ; |
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/* Check if the derived IRQ is usable first */ |
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for (int j = 0; j < ESP32_INTC_SRCS_PER_IRQ; j++) { |
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int idx = ESP_INTR_IDX(irq, j); |
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/* Ensure idx is within a valid range */ |
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if (idx >= ARRAY_SIZE(esp_intr_irq_alloc)) { |
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continue; |
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} |
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/* If source is already assigned, return the IRQ */ |
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if (esp_intr_irq_alloc[idx] == source) { |
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return irq; |
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} |
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/* If slot is free, allocate it */ |
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if (esp_intr_irq_alloc[idx] == IRQ_FREE) { |
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esp_intr_irq_alloc[idx] = source; |
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return irq; |
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} |
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} |
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/* If derived IRQ is full, search for another available IRQ */ |
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for (irq = 0; irq < ESP_INTC_AVAILABLE_IRQS; irq++) { |
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if (RSVD_MASK & (1U << irq)) { |
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continue; |
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} |
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for (int j = 0; j < ESP32_INTC_SRCS_PER_IRQ; j++) { |
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int idx = ESP_INTR_IDX(irq, j); |
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/* Ensure idx is within a valid range */ |
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if (idx >= ARRAY_SIZE(esp_intr_irq_alloc)) { |
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continue; |
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} |
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/* If source is already assigned, return this IRQ */ |
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if (esp_intr_irq_alloc[idx] == source) { |
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return irq; |
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} |
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/* If slot is free, allocate it */ |
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if (esp_intr_irq_alloc[idx] == IRQ_FREE) { |
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esp_intr_irq_alloc[idx] = source; |
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return irq; |
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} |
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} |
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} |
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/* No available slot found */ |
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return IRQ_NA; |
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} |
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void esp_intr_initialize(void) |
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{ |
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for (int i = 0; i < ETS_MAX_INTR_SOURCE; i++) { |
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esp_rom_intr_matrix_set(0, i, ESP32_INTC_DISABLED_SLOT); |
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} |
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for (int irq = 0; irq < ESP_INTC_AVAILABLE_IRQS; irq++) { |
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for (int j = 0; j < ESP32_INTC_SRCS_PER_IRQ; j++) { |
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int idx = ESP_INTR_IDX(irq, j); |
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if (RSVD_MASK & (1U << irq)) { |
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esp_intr_irq_alloc[idx] = IRQ_NA; |
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} else { |
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esp_intr_irq_alloc[idx] = IRQ_FREE; |
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} |
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} |
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} |
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/* set global INTC masking level */ |
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esprv_intc_int_set_threshold(ESP32_INTC_DEFAULT_THRESHOLD); |
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} |
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int esp_intr_alloc(int source, |
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int flags, |
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isr_handler_t handler, |
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void *arg, |
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void **ret_handle) |
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{ |
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ARG_UNUSED(flags); |
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ARG_UNUSED(ret_handle); |
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if (handler == NULL) { |
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return -EINVAL; |
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} |
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if (source < 0 || source >= ETS_MAX_INTR_SOURCE) { |
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return -EINVAL; |
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} |
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uint32_t key = irq_lock(); |
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uint32_t irq = esp_intr_find_irq_for_source(source); |
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if (irq == IRQ_NA) { |
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irq_unlock(key); |
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return -ENOMEM; |
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} |
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irq_connect_dynamic(source, |
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ESP32_INTC_DEFAULT_PRIORITY, |
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handler, |
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arg, |
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0); |
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INTC_LOG("Enabled ISRs -- 0: 0x%X -- 1: 0x%X -- 2: 0x%X", |
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esp_intr_enabled_mask[0], esp_intr_enabled_mask[1], esp_intr_enabled_mask[2]); |
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irq_unlock(key); |
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int ret = esp_intr_enable(source); |
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return ret; |
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} |
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int esp_intr_disable(int source) |
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{ |
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if (source < 0 || source >= ETS_MAX_INTR_SOURCE) { |
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return -EINVAL; |
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} |
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uint32_t key = irq_lock(); |
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esp_rom_intr_matrix_set(0, |
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source, |
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ESP32_INTC_DISABLED_SLOT); |
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for (int i = 0; i < ESP_INTC_AVAILABLE_IRQS; i++) { |
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if (RSVD_MASK & (1U << i)) { |
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continue; |
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} |
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for (int j = 0; j < ESP32_INTC_SRCS_PER_IRQ; j++) { |
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int idx = ESP_INTR_IDX(i, j); |
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if (esp_intr_irq_alloc[idx] == source) { |
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esp_intr_irq_alloc[idx] = IRQ_FREE; |
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} |
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} |
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} |
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if (source < 32) { |
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esp_intr_enabled_mask[0] &= ~(1 << source); |
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} else if (source < 64) { |
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esp_intr_enabled_mask[1] &= ~(1 << (source - 32)); |
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} else if (source < 96) { |
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esp_intr_enabled_mask[2] &= ~(1 << (source - 64)); |
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} |
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INTC_LOG("Enabled ISRs -- 0: 0x%X -- 1: 0x%X -- 2: 0x%X", |
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esp_intr_enabled_mask[0], esp_intr_enabled_mask[1], esp_intr_enabled_mask[2]); |
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irq_unlock(key); |
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return 0; |
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} |
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int esp_intr_enable(int source) |
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{ |
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if (source < 0 || source >= ETS_MAX_INTR_SOURCE) { |
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return -EINVAL; |
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} |
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uint32_t key = irq_lock(); |
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uint32_t irq = esp_intr_find_irq_for_source(source); |
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if (irq == IRQ_NA) { |
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irq_unlock(key); |
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return -ENOMEM; |
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} |
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esp_rom_intr_matrix_set(0, source, irq); |
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if (source < 32) { |
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esp_intr_enabled_mask[0] |= (1 << source); |
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} else if (source < 64) { |
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esp_intr_enabled_mask[1] |= (1 << (source - 32)); |
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} else if (source < 96) { |
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esp_intr_enabled_mask[2] |= (1 << (source - 64)); |
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} |
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INTC_LOG("Enabled ISRs -- 0: 0x%X -- 1: 0x%X -- 2: 0x%X", |
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esp_intr_enabled_mask[0], esp_intr_enabled_mask[1], esp_intr_enabled_mask[2]); |
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esprv_intc_int_set_priority(irq, ESP32_INTC_DEFAULT_PRIORITY); |
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esprv_intc_int_set_type(irq, INTR_TYPE_LEVEL); |
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esprv_intc_int_enable(1 << irq); |
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irq_unlock(key); |
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return 0; |
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} |
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uint32_t esp_intr_get_enabled_intmask(int status_mask_number) |
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{ |
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INTC_LOG("Enabled ISRs -- 0: 0x%X -- 1: 0x%X -- 2: 0x%X", |
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esp_intr_enabled_mask[0], esp_intr_enabled_mask[1], esp_intr_enabled_mask[2]); |
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if (status_mask_number < STATUS_MASK_NUM) { |
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return esp_intr_enabled_mask[status_mask_number]; |
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} |
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return 0; |
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} |
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@ -1,124 +0,0 @@
@@ -1,124 +0,0 @@
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/*
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* Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd. |
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* |
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* SPDX-License-Identifier: Apache-2.0 |
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*/ |
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#ifndef ZEPHYR_INCLUDE_DRIVERS_INTERRUPT_CONTROLLER_INTC_ESP32C3_H_ |
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#define ZEPHYR_INCLUDE_DRIVERS_INTERRUPT_CONTROLLER_INTC_ESP32C3_H_ |
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#include <stdint.h> |
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#include <stdbool.h> |
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#include <soc.h> |
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/*
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* Interrupt allocation flags - These flags can be used to specify |
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* which interrupt qualities the code calling esp_intr_alloc* needs. |
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*/ |
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/* Keep the LEVELx values as they are here; they match up with (1<<level) */ |
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#define ESP_INTR_FLAG_LEVEL1 (1<<1) /* Accept a Level 1 int vector, lowest priority */ |
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#define ESP_INTR_FLAG_LEVEL2 (1<<2) /* Accept a Level 2 int vector */ |
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#define ESP_INTR_FLAG_LEVEL3 (1<<3) /* Accept a Level 3 int vector */ |
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#define ESP_INTR_FLAG_LEVEL4 (1<<4) /* Accept a Level 4 int vector */ |
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#define ESP_INTR_FLAG_LEVEL5 (1<<5) /* Accept a Level 5 int vector */ |
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#define ESP_INTR_FLAG_LEVEL6 (1<<6) /* Accept a Level 6 int vector */ |
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#define ESP_INTR_FLAG_NMI (1<<7) /* Accept a Level 7 int vector, highest priority */ |
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#define ESP_INTR_FLAG_SHARED (1<<8) /* Interrupt can be shared between ISRs */ |
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#define ESP_INTR_FLAG_EDGE (1<<9) /* Edge-triggered interrupt */ |
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#define ESP_INTR_FLAG_IRAM (1<<10) /* ISR can be called if cache is disabled */ |
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#define ESP_INTR_FLAG_INTRDISABLED (1<<11) /* Return with this interrupt disabled */ |
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/* Low and medium prio interrupts. These can be handled in C. */ |
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#define ESP_INTR_FLAG_LOWMED (ESP_INTR_FLAG_LEVEL1|ESP_INTR_FLAG_LEVEL2|ESP_INTR_FLAG_LEVEL3) |
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/* High level interrupts. Need to be handled in assembly. */ |
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#define ESP_INTR_FLAG_HIGH (ESP_INTR_FLAG_LEVEL4|ESP_INTR_FLAG_LEVEL5|ESP_INTR_FLAG_LEVEL6| \ |
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ESP_INTR_FLAG_NMI) |
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/* Mask for all level flags */ |
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#define ESP_INTR_FLAG_LEVELMASK (ESP_INTR_FLAG_LEVEL1|ESP_INTR_FLAG_LEVEL2|ESP_INTR_FLAG_LEVEL3| \ |
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ESP_INTR_FLAG_LEVEL4|ESP_INTR_FLAG_LEVEL5|ESP_INTR_FLAG_LEVEL6| \ |
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ESP_INTR_FLAG_NMI) |
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#define IRQ_NA 0xFF /* IRQ not available */ |
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#define IRQ_FREE 0xFE /* IRQ available for use */ |
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/*
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* Get the interrupt flags from the supplied priority. |
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*/ |
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#define ESP_PRIO_TO_FLAGS(priority) \ |
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((priority) > 0 ? ((1 << (priority)) & ESP_INTR_FLAG_LEVELMASK) : 0) |
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/*
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* Check interrupt flags from input and filter unallowed values. |
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*/ |
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#define ESP_INT_FLAGS_CHECK(int_flags) ((int_flags) & ESP_INTR_FLAG_SHARED) |
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/* Function prototype for interrupt handler function */ |
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typedef void (*isr_handler_t)(const void *arg); |
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/**
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* @brief Initializes interrupt table to its defaults |
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*/ |
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void esp_intr_initialize(void); |
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/**
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* @brief Allocate an interrupt with the given parameters. |
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* |
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* This finds an interrupt that matches the restrictions as given in the flags |
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* parameter, maps the given interrupt source to it and hooks up the given |
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* interrupt handler (with optional argument) as well. If needed, it can return |
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* a handle for the interrupt as well. |
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* |
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* @param source The interrupt source. |
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* @param flags An ORred mask of the ESP_INTR_FLAG_* defines. These restrict the |
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* choice of interrupts that this routine can choose from. If this value |
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* is 0, it will default to allocating a non-shared interrupt of level |
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* 1, 2 or 3. If this is ESP_INTR_FLAG_SHARED, it will allocate a shared |
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* interrupt of level 1. Setting ESP_INTR_FLAG_INTRDISABLED will return |
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* from this function with the interrupt disabled. |
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* @param handler The interrupt handler. |
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* @param arg Optional argument for passed to the interrupt handler |
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* @param ret_handle Pointer to a struct intr_handle_data_t pointer to store a handle that can |
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* later be used to request details or free the interrupt. Can be NULL if no handle |
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* is required. |
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* |
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* @return -EINVAL if the combination of arguments is invalid. |
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* -ENODEV No free interrupt found with the specified flags |
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* 0 otherwise |
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*/ |
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int esp_intr_alloc(int source, |
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int flags, |
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isr_handler_t handler, |
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void *arg, |
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void **ret_handle); |
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/**
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* @brief Disable the interrupt associated with the source |
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* |
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* @param source The interrupt source |
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* |
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* @return -EINVAL if the combination of arguments is invalid. |
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* 0 otherwise |
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*/ |
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int esp_intr_disable(int source); |
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/**
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* @brief Enable the interrupt associated with the source |
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* |
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* @param source The interrupt source |
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* @return -EINVAL if the combination of arguments is invalid. |
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* 0 otherwise |
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*/ |
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int esp_intr_enable(int source); |
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/**
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* @brief Gets the current enabled interrupts |
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* |
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* @param status_mask_number the status mask can be 0 or 1 |
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* @return bitmask of enabled interrupt sources |
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*/ |
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uint32_t esp_intr_get_enabled_intmask(int status_mask_number); |
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#endif /* ZEPHYR_INCLUDE_DRIVERS_INTERRUPT_CONTROLLER_INTC_ESP32C3_H_ */ |
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