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211 lines
10 KiB
211 lines
10 KiB
/* |
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* NT99141 register definitions. |
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*/ |
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#ifndef __NT99141_REG_REGS_H__ |
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#define __NT99141_REG_REGS_H__ |
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/* system control registers */ |
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#define SYSTEM_CTROL0 0x3021 // Bit[7]: Software reset |
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// Bit[6]: Software power down |
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// Bit[5]: Reserved |
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// Bit[4]: SRB clock SYNC enable |
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// Bit[3]: Isolation suspend select |
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// Bit[2:0]: Not used |
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/* output format control registers */ |
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#define FORMAT_CTRL 0x501F // Format select |
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// Bit[2:0]: |
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// 000: YUV422 |
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// 001: RGB |
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// 010: Dither |
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// 011: RAW after DPC |
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// 101: RAW after CIP |
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/* format control registers */ |
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#define FORMAT_CTRL00 0x4300 |
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/* frame control registers */ |
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#define FRAME_CTRL01 0x4201 // Control Passed Frame Number When both ON and OFF number set to 0x00,frame control is in bypass mode |
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// Bit[7:4]: Not used |
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// Bit[3:0]: Frame ON number |
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#define FRAME_CTRL02 0x4202 // Control Masked Frame Number When both ON and OFF number set to 0x00,frame control is in bypass mode |
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// Bit[7:4]: Not used |
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// BIT[3:0]: Frame OFF number |
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/* ISP top control registers */ |
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#define PRE_ISP_TEST_SETTING_1 0x3025 // Bit[7]: Test enable |
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// 0: Test disable |
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// 1: Color bar enable |
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// Bit[6]: Rolling |
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// Bit[5]: Transparent |
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// Bit[4]: Square black and white |
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// Bit[3:2]: Color bar style |
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// 00: Standard 8 color bar |
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// 01: Gradual change at vertical mode 1 |
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// 10: Gradual change at horizontal |
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// 11: Gradual change at vertical mode 2 |
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// Bit[1:0]: Test select |
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// 00: Color bar |
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// 01: Random data |
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// 10: Square data |
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// 11: Black image |
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//exposure = {0x3500[3:0], 0x3501[7:0], 0x3502[7:0]} / 16 × tROW |
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/* AEC/AGC control functions */ |
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#define AEC_PK_MANUAL 0x3201 // AEC Manual Mode Control |
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// Bit[7:6]: Reserved |
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// Bit[5]: Gain delay option |
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// Valid when 0x3503[4]=1’b0 |
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// 0: Delay one frame latch |
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// 1: One frame latch |
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// Bit[4:2]: Reserved |
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// Bit[1]: AGC manual |
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// 0: Auto enable |
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// 1: Manual enable |
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// Bit[0]: AEC manual |
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// 0: Auto enable |
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// 1: Manual enable |
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//gain = {0x350A[1:0], 0x350B[7:0]} / 16 |
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/* mirror and flip registers */ |
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#define TIMING_TC_REG20 0x3022 // Timing Control Register |
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// Bit[2:1]: Vertical flip enable |
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// 00: Normal |
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// 11: Vertical flip |
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// Bit[0]: Vertical binning enable |
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#define TIMING_TC_REG21 0x3022 // Timing Control Register |
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// Bit[5]: Compression Enable |
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// Bit[2:1]: Horizontal mirror enable |
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// 00: Normal |
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// 11: Horizontal mirror |
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// Bit[0]: Horizontal binning enable |
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#define CLOCK_POL_CONTROL 0x3024// Bit[5]: PCLK polarity 0: active low |
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// 1: active high |
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// Bit[3]: Gate PCLK under VSYNC |
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// Bit[2]: Gate PCLK under HREF |
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// Bit[1]: HREF polarity |
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// 0: active low |
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// 1: active high |
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// Bit[0] VSYNC polarity |
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// 0: active low |
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// 1: active high |
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#define DRIVE_CAPABILITY 0x306a // Bit[7:6]: |
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// 00: 1x |
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// 01: 2x |
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// 10: 3x |
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// 11: 4x |
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#define X_ADDR_ST_H 0x3800 //Bit[3:0]: X address start[11:8] |
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#define X_ADDR_ST_L 0x3801 //Bit[7:0]: X address start[7:0] |
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#define Y_ADDR_ST_H 0x3802 //Bit[2:0]: Y address start[10:8] |
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#define Y_ADDR_ST_L 0x3803 //Bit[7:0]: Y address start[7:0] |
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#define X_ADDR_END_H 0x3804 //Bit[3:0]: X address end[11:8] |
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#define X_ADDR_END_L 0x3805 //Bit[7:0]: |
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#define Y_ADDR_END_H 0x3806 //Bit[2:0]: Y address end[10:8] |
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#define Y_ADDR_END_L 0x3807 //Bit[7:0]: |
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// Size after scaling |
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#define X_OUTPUT_SIZE_H 0x3808 //Bit[3:0]: DVP output horizontal width[11:8] |
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#define X_OUTPUT_SIZE_L 0x3809 //Bit[7:0]: |
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#define Y_OUTPUT_SIZE_H 0x380a //Bit[2:0]: DVP output vertical height[10:8] |
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#define Y_OUTPUT_SIZE_L 0x380b //Bit[7:0]: |
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#define X_TOTAL_SIZE_H 0x380c //Bit[3:0]: Total horizontal size[11:8] |
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#define X_TOTAL_SIZE_L 0x380d //Bit[7:0]: |
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#define Y_TOTAL_SIZE_H 0x380e //Bit[7:0]: Total vertical size[15:8] |
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#define Y_TOTAL_SIZE_L 0x380f //Bit[7:0]: |
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#define X_OFFSET_H 0x3810 //Bit[3:0]: ISP horizontal offset[11:8] |
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#define X_OFFSET_L 0x3811 //Bit[7:0]: |
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#define Y_OFFSET_H 0x3812 //Bit[2:0]: ISP vertical offset[10:8] |
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#define Y_OFFSET_L 0x3813 //Bit[7:0]: |
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#define X_INCREMENT 0x3814 //Bit[7:4]: Horizontal odd subsample increment |
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//Bit[3:0]: Horizontal even subsample increment |
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#define Y_INCREMENT 0x3815 //Bit[7:4]: Vertical odd subsample increment |
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//Bit[3:0]: Vertical even subsample increment |
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// Size before scaling |
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//#define X_INPUT_SIZE (X_ADDR_END - X_ADDR_ST + 1 - (2 * X_OFFSET)) |
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//#define Y_INPUT_SIZE (Y_ADDR_END - Y_ADDR_ST + 1 - (2 * Y_OFFSET)) |
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#define ISP_CONTROL_01 0x3021 // Bit[5]: Scale enable |
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// 0: Disable |
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// 1: Enable |
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#define SCALE_CTRL_1 0x5601 // Bit[6:4]: HDIV RW |
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// DCW scale times |
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// 000: DCW 1 time |
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// 001: DCW 2 times |
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// 010: DCW 4 times |
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// 100: DCW 8 times |
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// 101: DCW 16 times |
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// Others: DCW 16 times |
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// Bit[2:0]: VDIV RW |
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// DCW scale times |
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// 000: DCW 1 time |
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// 001: DCW 2 times |
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// 010: DCW 4 times |
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// 100: DCW 8 times |
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// 101: DCW 16 times |
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// Others: DCW 16 times |
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#define SCALE_CTRL_2 0x5602 // X_SCALE High Bits |
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#define SCALE_CTRL_3 0x5603 // X_SCALE Low Bits |
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#define SCALE_CTRL_4 0x5604 // Y_SCALE High Bits |
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#define SCALE_CTRL_5 0x5605 // Y_SCALE Low Bits |
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#define SCALE_CTRL_6 0x5606 // Bit[3:0]: V Offset |
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#define PCLK_RATIO 0x3824 // Bit[4:0]: PCLK ratio manual |
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#define VFIFO_CTRL0C 0x460C // Bit[1]: PCLK manual enable |
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// 0: Auto |
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// 1: Manual by PCLK_RATIO |
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#define VFIFO_X_SIZE_H 0x4602 |
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#define VFIFO_X_SIZE_L 0x4603 |
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#define VFIFO_Y_SIZE_H 0x4604 |
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#define VFIFO_Y_SIZE_L 0x4605 |
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#define SC_PLLS_CTRL0 0x303a // Bit[7]: PLLS bypass |
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#define SC_PLLS_CTRL1 0x303b // Bit[4:0]: PLLS multiplier |
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#define SC_PLLS_CTRL2 0x303c // Bit[6:4]: PLLS charge pump control |
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// Bit[3:0]: PLLS system divider |
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#define SC_PLLS_CTRL3 0x303d // Bit[5:4]: PLLS pre-divider |
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// 00: 1 |
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// 01: 1.5 |
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// 10: 2 |
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// 11: 3 |
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// Bit[2]: PLLS root-divider - 1 |
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// Bit[1:0]: PLLS seld5 |
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// 00: 1 |
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// 01: 1 |
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// 10: 2 |
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// 11: 2.5 |
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#define COMPRESSION_CTRL00 0x4400 // |
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#define COMPRESSION_CTRL01 0x4401 // |
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#define COMPRESSION_CTRL02 0x4402 // |
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#define COMPRESSION_CTRL03 0x4403 // |
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#define COMPRESSION_CTRL04 0x4404 // |
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#define COMPRESSION_CTRL05 0x4405 // |
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#define COMPRESSION_CTRL06 0x4406 // |
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#define COMPRESSION_CTRL07 0x3401 // Bit[5:0]: QS |
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#define COMPRESSION_ISI_CTRL 0x4408 // |
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#define COMPRESSION_CTRL09 0x4409 // |
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#define COMPRESSION_CTRL0a 0x440a // |
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#define COMPRESSION_CTRL0b 0x440b // |
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#define COMPRESSION_CTRL0c 0x440c // |
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#define COMPRESSION_CTRL0d 0x440d // |
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#define COMPRESSION_CTRL0E 0x440e // |
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/** |
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* @brief register value |
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*/ |
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#define TEST_COLOR_BAR 0x02 /* Enable Color Bar roling Test */ |
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#define AEC_PK_MANUAL_AGC_MANUALEN 0x02 /* Enable AGC Manual enable */ |
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#define AEC_PK_MANUAL_AEC_MANUALEN 0x01 /* Enable AEC Manual enable */ |
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#define TIMING_TC_REG20_VFLIP 0x01 /* Vertical flip enable */ |
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#define TIMING_TC_REG21_HMIRROR 0x02 /* Horizontal mirror enable */ |
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#endif // __NT99141_REG_REGS_H__
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