Me No Dev
5 years ago
committed by
GitHub
20 changed files with 2185 additions and 235 deletions
@ -1,17 +1,28 @@
@@ -1,17 +1,28 @@
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#include "sensor.h" |
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const int resolution[][2] = { |
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{ 96, 96 }, /* 96x96 */ |
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{ 160, 120 }, /* QQVGA */ |
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{ 128, 160 }, /* QQVGA2*/ |
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{ 176, 144 }, /* QCIF */ |
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{ 240, 176 }, /* HQVGA */ |
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{ 240, 240 }, /* 240x240 */ |
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{ 320, 240 }, /* QVGA */ |
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{ 400, 296 }, /* CIF */ |
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{ 640, 480 }, /* VGA */ |
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{ 800, 600 }, /* SVGA */ |
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{ 1024, 768 }, /* XGA */ |
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{ 1280, 1024 }, /* SXGA */ |
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{ 1600, 1200 }, /* UXGA */ |
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{ 2048, 1536 }, /* QXGA */ |
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const resolution_info_t resolution[FRAMESIZE_INVALID] = { |
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{ 96, 96, ASPECT_RATIO_1X1 }, /* 96x96 */ |
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{ 160, 120, ASPECT_RATIO_4X3 }, /* QQVGA */ |
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{ 176, 144, ASPECT_RATIO_5X4 }, /* QCIF */ |
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{ 240, 176, ASPECT_RATIO_4X3 }, /* HQVGA */ |
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{ 240, 240, ASPECT_RATIO_1X1 }, /* 240x240 */ |
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{ 320, 240, ASPECT_RATIO_4X3 }, /* QVGA */ |
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{ 400, 296, ASPECT_RATIO_4X3 }, /* CIF */ |
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{ 480, 320, ASPECT_RATIO_3X2 }, /* HVGA */ |
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{ 640, 480, ASPECT_RATIO_4X3 }, /* VGA */ |
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{ 800, 600, ASPECT_RATIO_4X3 }, /* SVGA */ |
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{ 1024, 768, ASPECT_RATIO_4X3 }, /* XGA */ |
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{ 1280, 720, ASPECT_RATIO_16X9 }, /* HD */ |
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{ 1280, 1024, ASPECT_RATIO_5X4 }, /* SXGA */ |
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{ 1600, 1200, ASPECT_RATIO_4X3 }, /* UXGA */ |
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// 3MP Sensors
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{ 1920, 1080, ASPECT_RATIO_16X9 }, /* FHD */ |
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{ 720, 1280, ASPECT_RATIO_9X16 }, /* Portrait HD */ |
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{ 864, 1536, ASPECT_RATIO_9X16 }, /* Portrait 3MP */ |
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{ 2048, 1536, ASPECT_RATIO_4X3 }, /* QXGA */ |
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// 5MP Sensors
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{ 2560, 1440, ASPECT_RATIO_16X9 }, /* QHD */ |
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{ 2560, 1600, ASPECT_RATIO_16X10 }, /* WQXGA */ |
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{ 1088, 1920, ASPECT_RATIO_9X16 }, /* Portrait FHD */ |
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{ 2560, 1920, ASPECT_RATIO_4X3 }, /* QSXGA */ |
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}; |
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@ -0,0 +1,9 @@
@@ -0,0 +1,9 @@
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#ifndef __OV5640_H__ |
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#define __OV5640_H__ |
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#include "sensor.h" |
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int ov5640_init(sensor_t *sensor); |
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#endif // __OV5640_H__
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@ -0,0 +1,213 @@
@@ -0,0 +1,213 @@
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/*
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* OV5640 register definitions. |
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*/ |
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#ifndef __OV5640_REG_REGS_H__ |
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#define __OV5640_REG_REGS_H__ |
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/* system control registers */ |
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#define SYSTEM_CTROL0 0x3008 // Bit[7]: Software reset
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// Bit[6]: Software power down
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// Bit[5]: Reserved
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// Bit[4]: SRB clock SYNC enable
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// Bit[3]: Isolation suspend select
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// Bit[2:0]: Not used
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#define DRIVE_CAPABILITY 0x302c // Bit[7:6]:
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// 00: 1x
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// 01: 2x
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// 10: 3x
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// 11: 4x
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#define SC_PLLS_CTRL0 0x303a // Bit[7]: PLLS bypass
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#define SC_PLLS_CTRL1 0x303b // Bit[4:0]: PLLS multiplier
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#define SC_PLLS_CTRL2 0x303c // Bit[6:4]: PLLS charge pump control
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// Bit[3:0]: PLLS system divider
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#define SC_PLLS_CTRL3 0x303d // Bit[5:4]: PLLS pre-divider
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// 00: 1
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// 01: 1.5
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// 10: 2
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// 11: 3
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// Bit[2]: PLLS root-divider - 1
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// Bit[1:0]: PLLS seld5
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// 00: 1
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// 01: 1
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// 10: 2
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// 11: 2.5
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/* AEC/AGC control functions */ |
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#define AEC_PK_MANUAL 0x3503 // AEC Manual Mode Control
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// Bit[7:6]: Reserved
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// Bit[5]: Gain delay option
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// Valid when 0x3503[4]=1’b0
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// 0: Delay one frame latch
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// 1: One frame latch
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// Bit[4:2]: Reserved
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// Bit[1]: AGC manual
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// 0: Auto enable
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// 1: Manual enable
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// Bit[0]: AEC manual
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// 0: Auto enable
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// 1: Manual enable
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//gain = {0x350A[1:0], 0x350B[7:0]} / 16
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#define X_ADDR_ST_H 0x3800 //Bit[3:0]: X address start[11:8]
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#define X_ADDR_ST_L 0x3801 //Bit[7:0]: X address start[7:0]
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#define Y_ADDR_ST_H 0x3802 //Bit[2:0]: Y address start[10:8]
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#define Y_ADDR_ST_L 0x3803 //Bit[7:0]: Y address start[7:0]
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#define X_ADDR_END_H 0x3804 //Bit[3:0]: X address end[11:8]
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#define X_ADDR_END_L 0x3805 //Bit[7:0]:
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#define Y_ADDR_END_H 0x3806 //Bit[2:0]: Y address end[10:8]
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#define Y_ADDR_END_L 0x3807 //Bit[7:0]:
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// Size after scaling
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#define X_OUTPUT_SIZE_H 0x3808 //Bit[3:0]: DVP output horizontal width[11:8]
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#define X_OUTPUT_SIZE_L 0x3809 //Bit[7:0]:
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#define Y_OUTPUT_SIZE_H 0x380a //Bit[2:0]: DVP output vertical height[10:8]
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#define Y_OUTPUT_SIZE_L 0x380b //Bit[7:0]:
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#define X_TOTAL_SIZE_H 0x380c //Bit[3:0]: Total horizontal size[11:8]
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#define X_TOTAL_SIZE_L 0x380d //Bit[7:0]:
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#define Y_TOTAL_SIZE_H 0x380e //Bit[7:0]: Total vertical size[15:8]
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#define Y_TOTAL_SIZE_L 0x380f //Bit[7:0]:
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#define X_OFFSET_H 0x3810 //Bit[3:0]: ISP horizontal offset[11:8]
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#define X_OFFSET_L 0x3811 //Bit[7:0]:
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#define Y_OFFSET_H 0x3812 //Bit[2:0]: ISP vertical offset[10:8]
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#define Y_OFFSET_L 0x3813 //Bit[7:0]:
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#define X_INCREMENT 0x3814 //Bit[7:4]: Horizontal odd subsample increment
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//Bit[3:0]: Horizontal even subsample increment
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#define Y_INCREMENT 0x3815 //Bit[7:4]: Vertical odd subsample increment
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//Bit[3:0]: Vertical even subsample increment
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// Size before scaling
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//#define X_INPUT_SIZE (X_ADDR_END - X_ADDR_ST + 1 - (2 * X_OFFSET))
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//#define Y_INPUT_SIZE (Y_ADDR_END - Y_ADDR_ST + 1 - (2 * Y_OFFSET))
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/* mirror and flip registers */ |
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#define TIMING_TC_REG20 0x3820 // Timing Control Register
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// Bit[2:1]: Vertical flip enable
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// 00: Normal
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// 11: Vertical flip
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// Bit[0]: Vertical binning enable
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#define TIMING_TC_REG21 0x3821 // Timing Control Register
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// Bit[5]: Compression Enable
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// Bit[2:1]: Horizontal mirror enable
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// 00: Normal
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// 11: Horizontal mirror
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// Bit[0]: Horizontal binning enable
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#define PCLK_RATIO 0x3824 // Bit[4:0]: PCLK ratio manual
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/* frame control registers */ |
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#define FRAME_CTRL01 0x4201 // Control Passed Frame Number When both ON and OFF number set to 0x00,frame control is in bypass mode
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// Bit[7:4]: Not used
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// Bit[3:0]: Frame ON number
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#define FRAME_CTRL02 0x4202 // Control Masked Frame Number When both ON and OFF number set to 0x00,frame control is in bypass mode
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// Bit[7:4]: Not used
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// BIT[3:0]: Frame OFF number
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/* format control registers */ |
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#define FORMAT_CTRL00 0x4300 |
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#define CLOCK_POL_CONTROL 0x4740// Bit[5]: PCLK polarity 0: active low
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// 1: active high
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// Bit[3]: Gate PCLK under VSYNC
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// Bit[2]: Gate PCLK under HREF
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// Bit[1]: HREF polarity
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// 0: active low
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// 1: active high
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// Bit[0] VSYNC polarity
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// 0: active low
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// 1: active high
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#define ISP_CONTROL_01 0x5001 // Bit[5]: Scale enable
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// 0: Disable
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// 1: Enable
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/* output format control registers */ |
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#define FORMAT_CTRL 0x501F // Format select
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// Bit[2:0]:
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// 000: YUV422
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// 001: RGB
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// 010: Dither
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// 011: RAW after DPC
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// 101: RAW after CIP
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/* ISP top control registers */ |
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#define PRE_ISP_TEST_SETTING_1 0x503D // Bit[7]: Test enable
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// 0: Test disable
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// 1: Color bar enable
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// Bit[6]: Rolling
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// Bit[5]: Transparent
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// Bit[4]: Square black and white
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// Bit[3:2]: Color bar style
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// 00: Standard 8 color bar
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// 01: Gradual change at vertical mode 1
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// 10: Gradual change at horizontal
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// 11: Gradual change at vertical mode 2
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// Bit[1:0]: Test select
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// 00: Color bar
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// 01: Random data
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// 10: Square data
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// 11: Black image
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//exposure = {0x3500[3:0], 0x3501[7:0], 0x3502[7:0]} / 16 × tROW
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#define SCALE_CTRL_1 0x5601 // Bit[6:4]: HDIV RW
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// DCW scale times
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// 000: DCW 1 time
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// 001: DCW 2 times
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// 010: DCW 4 times
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// 100: DCW 8 times
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// 101: DCW 16 times
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// Others: DCW 16 times
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// Bit[2:0]: VDIV RW
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// DCW scale times
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// 000: DCW 1 time
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// 001: DCW 2 times
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// 010: DCW 4 times
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// 100: DCW 8 times
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// 101: DCW 16 times
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// Others: DCW 16 times
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#define SCALE_CTRL_2 0x5602 // X_SCALE High Bits
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#define SCALE_CTRL_3 0x5603 // X_SCALE Low Bits
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#define SCALE_CTRL_4 0x5604 // Y_SCALE High Bits
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#define SCALE_CTRL_5 0x5605 // Y_SCALE Low Bits
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#define SCALE_CTRL_6 0x5606 // Bit[3:0]: V Offset
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#define VFIFO_CTRL0C 0x460C // Bit[1]: PCLK manual enable
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// 0: Auto
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// 1: Manual by PCLK_RATIO
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#define VFIFO_X_SIZE_H 0x4602 |
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#define VFIFO_X_SIZE_L 0x4603 |
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#define VFIFO_Y_SIZE_H 0x4604 |
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#define VFIFO_Y_SIZE_L 0x4605 |
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#define COMPRESSION_CTRL00 0x4400 //
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#define COMPRESSION_CTRL01 0x4401 //
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#define COMPRESSION_CTRL02 0x4402 //
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#define COMPRESSION_CTRL03 0x4403 //
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#define COMPRESSION_CTRL04 0x4404 //
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#define COMPRESSION_CTRL05 0x4405 //
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#define COMPRESSION_CTRL06 0x4406 //
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#define COMPRESSION_CTRL07 0x4407 // Bit[5:0]: QS
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#define COMPRESSION_ISI_CTRL 0x4408 //
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#define COMPRESSION_CTRL09 0x4409 //
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#define COMPRESSION_CTRL0a 0x440a //
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#define COMPRESSION_CTRL0b 0x440b //
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#define COMPRESSION_CTRL0c 0x440c //
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#define COMPRESSION_CTRL0d 0x440d //
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#define COMPRESSION_CTRL0E 0x440e //
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/**
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* @brief register value |
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*/ |
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#define TEST_COLOR_BAR 0xC0 /* Enable Color Bar roling Test */ |
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#define AEC_PK_MANUAL_AGC_MANUALEN 0x02 /* Enable AGC Manual enable */ |
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#define AEC_PK_MANUAL_AEC_MANUALEN 0x01 /* Enable AEC Manual enable */ |
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#define TIMING_TC_REG20_VFLIP 0x06 /* Vertical flip enable */ |
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#define TIMING_TC_REG21_HMIRROR 0x06 /* Horizontal mirror enable */ |
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#endif // __OV3660_REG_REGS_H__
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@ -0,0 +1,334 @@
@@ -0,0 +1,334 @@
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#ifndef _OV5640_SETTINGS_H_ |
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#define _OV5640_SETTINGS_H_ |
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#include <stdint.h> |
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#include <stdbool.h> |
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#include "esp_attr.h" |
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#include "ov5640_regs.h" |
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static const ratio_settings_t ratio_table[] = { |
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// mw, mh, sx, sy, ex, ey, ox, oy, tx, ty
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{ 2560, 1920, 0, 0, 2623, 1951, 32, 16, 2844, 1968 }, //4x3
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{ 2560, 1704, 0, 110, 2623, 1843, 32, 16, 2844, 1752 }, //3x2
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{ 2560, 1600, 0, 160, 2623, 1791, 32, 16, 2844, 1648 }, //16x10
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{ 2560, 1536, 0, 192, 2623, 1759, 32, 16, 2844, 1584 }, //5x3
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{ 2560, 1440, 0, 240, 2623, 1711, 32, 16, 2844, 1488 }, //16x9
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{ 2560, 1080, 0, 420, 2623, 1531, 32, 16, 2844, 1128 }, //21x9
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{ 2400, 1920, 80, 0, 2543, 1951, 32, 16, 2684, 1968 }, //5x4
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{ 1920, 1920, 320, 0, 2543, 1951, 32, 16, 2684, 1968 }, //1x1
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{ 1088, 1920, 736, 0, 1887, 1951, 32, 16, 1884, 1968 } //9x16
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}; |
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#define REG_DLY 0xffff |
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#define REGLIST_TAIL 0x0000 |
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static const DRAM_ATTR uint16_t sensor_default_regs[][2] = { |
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{SYSTEM_CTROL0, 0x82}, // software reset
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{REG_DLY, 10}, // delay 10ms
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{SYSTEM_CTROL0, 0x42}, // power down
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//enable pll
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{0x3103, 0x13}, |
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//io direction
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{0x3017, 0xff}, |
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{0x3018, 0xff}, |
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{DRIVE_CAPABILITY, 0xc3}, |
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{CLOCK_POL_CONTROL, 0x21}, |
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{0x4713, 0x02},//jpg mode select
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{ISP_CONTROL_01, 0x83}, // turn color matrix, awb and SDE
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//sys reset
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{0x3000, 0x00}, |
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{0x3002, 0x1c}, |
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//clock enable
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{0x3004, 0xff}, |
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{0x3006, 0xc3}, |
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//isp control
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{0x5000, 0xa7}, |
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{ISP_CONTROL_01, 0xa3},//+scaling?
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{0x5003, 0x08},//special_effect
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//unknown
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{0x370c, 0x02},//!!IMPORTANT
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{0x3634, 0x40},//!!IMPORTANT
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//AEC/AGC
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{0x3a02, 0x03}, |
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{0x3a03, 0xd8}, |
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{0x3a08, 0x01}, |
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{0x3a09, 0x27}, |
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{0x3a0a, 0x00}, |
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{0x3a0b, 0xf6}, |
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{0x3a0d, 0x04}, |
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{0x3a0e, 0x03}, |
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{0x3a0f, 0x30},//ae_level
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{0x3a10, 0x28},//ae_level
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{0x3a11, 0x60},//ae_level
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{0x3a13, 0x43}, |
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{0x3a14, 0x03}, |
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{0x3a15, 0xd8}, |
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{0x3a18, 0x00},//gainceiling
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{0x3a19, 0xf8},//gainceiling
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{0x3a1b, 0x30},//ae_level
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{0x3a1e, 0x26},//ae_level
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{0x3a1f, 0x14},//ae_level
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//vcm debug
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{0x3600, 0x08}, |
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{0x3601, 0x33}, |
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//50/60Hz
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{0x3c01, 0xa4}, |
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{0x3c04, 0x28}, |
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{0x3c05, 0x98}, |
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{0x3c06, 0x00}, |
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{0x3c07, 0x08}, |
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{0x3c08, 0x00}, |
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{0x3c09, 0x1c}, |
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{0x3c0a, 0x9c}, |
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{0x3c0b, 0x40}, |
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{0x460c, 0x22},//disable jpeg footer
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//BLC
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{0x4001, 0x02}, |
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{0x4004, 0x02}, |
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//AWB
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{0x5180, 0xff}, |
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{0x5181, 0xf2}, |
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{0x5182, 0x00}, |
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{0x5183, 0x14}, |
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{0x5184, 0x25}, |
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{0x5185, 0x24}, |
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{0x5186, 0x09}, |
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{0x5187, 0x09}, |
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{0x5188, 0x09}, |
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{0x5189, 0x75}, |
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{0x518a, 0x54}, |
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{0x518b, 0xe0}, |
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{0x518c, 0xb2}, |
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{0x518d, 0x42}, |
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{0x518e, 0x3d}, |
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{0x518f, 0x56}, |
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{0x5190, 0x46}, |
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{0x5191, 0xf8}, |
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{0x5192, 0x04}, |
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{0x5193, 0x70}, |
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{0x5194, 0xf0}, |
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{0x5195, 0xf0}, |
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{0x5196, 0x03}, |
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{0x5197, 0x01}, |
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{0x5198, 0x04}, |
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{0x5199, 0x12}, |
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{0x519a, 0x04}, |
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{0x519b, 0x00}, |
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{0x519c, 0x06}, |
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{0x519d, 0x82}, |
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{0x519e, 0x38}, |
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//color matrix (Saturation)
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{0x5381, 0x1e}, |
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{0x5382, 0x5b}, |
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{0x5383, 0x08}, |
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{0x5384, 0x0a}, |
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{0x5385, 0x7e}, |
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{0x5386, 0x88}, |
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{0x5387, 0x7c}, |
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{0x5388, 0x6c}, |
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{0x5389, 0x10}, |
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{0x538a, 0x01}, |
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{0x538b, 0x98}, |
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//CIP control (Sharpness)
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{0x5300, 0x10},//sharpness
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{0x5301, 0x10},//sharpness
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{0x5302, 0x18},//sharpness
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{0x5303, 0x19},//sharpness
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{0x5304, 0x10}, |
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{0x5305, 0x10}, |
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{0x5306, 0x08},//denoise
|
||||
{0x5307, 0x16}, |
||||
{0x5308, 0x40}, |
||||
{0x5309, 0x10},//sharpness
|
||||
{0x530a, 0x10},//sharpness
|
||||
{0x530b, 0x04},//sharpness
|
||||
{0x530c, 0x06},//sharpness
|
||||
|
||||
//GAMMA
|
||||
{0x5480, 0x01}, |
||||
{0x5481, 0x00}, |
||||
{0x5482, 0x1e}, |
||||
{0x5483, 0x3b}, |
||||
{0x5484, 0x58}, |
||||
{0x5485, 0x66}, |
||||
{0x5486, 0x71}, |
||||
{0x5487, 0x7d}, |
||||
{0x5488, 0x83}, |
||||
{0x5489, 0x8f}, |
||||
{0x548a, 0x98}, |
||||
{0x548b, 0xa6}, |
||||
{0x548c, 0xb8}, |
||||
{0x548d, 0xca}, |
||||
{0x548e, 0xd7}, |
||||
{0x548f, 0xe3}, |
||||
{0x5490, 0x1d}, |
||||
|
||||
//Special Digital Effects (SDE) (UV adjust)
|
||||
{0x5580, 0x06},//enable brightness and contrast
|
||||
{0x5583, 0x40},//special_effect
|
||||
{0x5584, 0x10},//special_effect
|
||||
{0x5586, 0x20},//contrast
|
||||
{0x5587, 0x00},//brightness
|
||||
{0x5588, 0x00},//brightness
|
||||
{0x5589, 0x10}, |
||||
{0x558a, 0x00}, |
||||
{0x558b, 0xf8}, |
||||
{0x501d, 0x40},// enable manual offset of contrast
|
||||
|
||||
//power on
|
||||
{0x3008, 0x02}, |
||||
|
||||
//50Hz
|
||||
{0x3c00, 0x04}, |
||||
|
||||
{REG_DLY, 300}, |
||||
{REGLIST_TAIL, 0x00}, // tail
|
||||
}; |
||||
|
||||
static const DRAM_ATTR uint16_t sensor_fmt_jpeg[][2] = { |
||||
{FORMAT_CTRL, 0x00}, // YUV422
|
||||
{FORMAT_CTRL00, 0x30}, // YUYV
|
||||
{0x3002, 0x00},//0x1c to 0x00 !!!
|
||||
{0x3006, 0xff},//0xc3 to 0xff !!!
|
||||
{0x471c, 0x50},//0xd0 to 0x50 !!!
|
||||
{REGLIST_TAIL, 0x00}, // tail
|
||||
}; |
||||
|
||||
static const DRAM_ATTR uint16_t sensor_fmt_raw[][2] = { |
||||
{FORMAT_CTRL, 0x03}, // RAW (DPC)
|
||||
{FORMAT_CTRL00, 0x00}, // RAW
|
||||
{REGLIST_TAIL, 0x00} |
||||
}; |
||||
|
||||
static const DRAM_ATTR uint16_t sensor_fmt_grayscale[][2] = { |
||||
{FORMAT_CTRL, 0x00}, // YUV422
|
||||
{FORMAT_CTRL00, 0x10}, // Y8
|
||||
{REGLIST_TAIL, 0x00} |
||||
}; |
||||
|
||||
static const DRAM_ATTR uint16_t sensor_fmt_yuv422[][2] = { |
||||
{FORMAT_CTRL, 0x00}, // YUV422
|
||||
{FORMAT_CTRL00, 0x30}, // YUYV
|
||||
{REGLIST_TAIL, 0x00} |
||||
}; |
||||
|
||||
static const DRAM_ATTR uint16_t sensor_fmt_rgb565[][2] = { |
||||
{FORMAT_CTRL, 0x01}, // RGB
|
||||
{FORMAT_CTRL00, 0x61}, // RGB565 (BGR)
|
||||
{REGLIST_TAIL, 0x00} |
||||
}; |
||||
|
||||
static const DRAM_ATTR uint8_t sensor_saturation_levels[9][11] = { |
||||
{0x1d, 0x60, 0x03, 0x07, 0x48, 0x4f, 0x4b, 0x40, 0x0b, 0x01, 0x98},//-4
|
||||
{0x1d, 0x60, 0x03, 0x08, 0x54, 0x5c, 0x58, 0x4b, 0x0d, 0x01, 0x98},//-3
|
||||
{0x1d, 0x60, 0x03, 0x0a, 0x60, 0x6a, 0x64, 0x56, 0x0e, 0x01, 0x98},//-2
|
||||
{0x1d, 0x60, 0x03, 0x0b, 0x6c, 0x77, 0x70, 0x60, 0x10, 0x01, 0x98},//-1
|
||||
{0x1d, 0x60, 0x03, 0x0c, 0x78, 0x84, 0x7d, 0x6b, 0x12, 0x01, 0x98},//0
|
||||
{0x1d, 0x60, 0x03, 0x0d, 0x84, 0x91, 0x8a, 0x76, 0x14, 0x01, 0x98},//+1
|
||||
{0x1d, 0x60, 0x03, 0x0e, 0x90, 0x9e, 0x96, 0x80, 0x16, 0x01, 0x98},//+2
|
||||
{0x1d, 0x60, 0x03, 0x10, 0x9c, 0xac, 0xa2, 0x8b, 0x17, 0x01, 0x98},//+3
|
||||
{0x1d, 0x60, 0x03, 0x11, 0xa8, 0xb9, 0xaf, 0x96, 0x19, 0x01, 0x98},//+4
|
||||
}; |
||||
|
||||
static const DRAM_ATTR uint8_t sensor_special_effects[7][4] = { |
||||
{0x06, 0x40, 0x2c, 0x08},//Normal
|
||||
{0x46, 0x40, 0x28, 0x08},//Negative
|
||||
{0x1e, 0x80, 0x80, 0x08},//Grayscale
|
||||
{0x1e, 0x80, 0xc0, 0x08},//Red Tint
|
||||
{0x1e, 0x60, 0x60, 0x08},//Green Tint
|
||||
{0x1e, 0xa0, 0x40, 0x08},//Blue Tint
|
||||
{0x1e, 0x40, 0xa0, 0x08},//Sepia
|
||||
}; |
||||
|
||||
static const DRAM_ATTR uint16_t sensor_regs_gamma0[][2] = { |
||||
{0x5480, 0x01}, |
||||
{0x5481, 0x08}, |
||||
{0x5482, 0x14}, |
||||
{0x5483, 0x28}, |
||||
{0x5484, 0x51}, |
||||
{0x5485, 0x65}, |
||||
{0x5486, 0x71}, |
||||
{0x5487, 0x7d}, |
||||
{0x5488, 0x87}, |
||||
{0x5489, 0x91}, |
||||
{0x548a, 0x9a}, |
||||
{0x548b, 0xaa}, |
||||
{0x548c, 0xb8}, |
||||
{0x548d, 0xcd}, |
||||
{0x548e, 0xdd}, |
||||
{0x548f, 0xea}, |
||||
{0x5490, 0x1d} |
||||
}; |
||||
|
||||
static const DRAM_ATTR uint16_t sensor_regs_gamma1[][2] = { |
||||
{0x5480, 0x1}, |
||||
{0x5481, 0x0}, |
||||
{0x5482, 0x1e}, |
||||
{0x5483, 0x3b}, |
||||
{0x5484, 0x58}, |
||||
{0x5485, 0x66}, |
||||
{0x5486, 0x71}, |
||||
{0x5487, 0x7d}, |
||||
{0x5488, 0x83}, |
||||
{0x5489, 0x8f}, |
||||
{0x548a, 0x98}, |
||||
{0x548b, 0xa6}, |
||||
{0x548c, 0xb8}, |
||||
{0x548d, 0xca}, |
||||
{0x548e, 0xd7}, |
||||
{0x548f, 0xe3}, |
||||
{0x5490, 0x1d} |
||||
}; |
||||
|
||||
static const DRAM_ATTR uint16_t sensor_regs_awb0[][2] = { |
||||
{0x5180, 0xff}, |
||||
{0x5181, 0xf2}, |
||||
{0x5182, 0x00}, |
||||
{0x5183, 0x14}, |
||||
{0x5184, 0x25}, |
||||
{0x5185, 0x24}, |
||||
{0x5186, 0x09}, |
||||
{0x5187, 0x09}, |
||||
{0x5188, 0x09}, |
||||
{0x5189, 0x75}, |
||||
{0x518a, 0x54}, |
||||
{0x518b, 0xe0}, |
||||
{0x518c, 0xb2}, |
||||
{0x518d, 0x42}, |
||||
{0x518e, 0x3d}, |
||||
{0x518f, 0x56}, |
||||
{0x5190, 0x46}, |
||||
{0x5191, 0xf8}, |
||||
{0x5192, 0x04}, |
||||
{0x5193, 0x70}, |
||||
{0x5194, 0xf0}, |
||||
{0x5195, 0xf0}, |
||||
{0x5196, 0x03}, |
||||
{0x5197, 0x01}, |
||||
{0x5198, 0x04}, |
||||
{0x5199, 0x12}, |
||||
{0x519a, 0x04}, |
||||
{0x519b, 0x00}, |
||||
{0x519c, 0x06}, |
||||
{0x519d, 0x82}, |
||||
{0x519e, 0x38} |
||||
}; |
||||
|
||||
#endif |
||||
Loading…
Reference in new issue