Merge pull request #2 from wonderfullook/main

add a led demo

README.md

@@ -1,6 +1,15 @@
 # TangNano-9K-example
 TangNano-9K-example project
 
+### note
+When you meet error code `PR2017`. Do what is shown below.
+![PR2017](.assets/ERROR%20CODE%20PR2017.png "PR2017")
+
+
+## led
+Demo project for drive LED and on board led.
+The related LED tutorial can be found at <https://wiki.sipeed.com/hardware/zh/tang/Tang-Nano/Tang-nano-9k.html>
+
 ## lcd_led
 Demo project for drive RGB LCD and on board led.
 

led/9K_LED_project.gprj

@@ -0,0 +1,11 @@
+<?xml version="1" encoding="UTF-8"?>
+<!DOCTYPE gowin-fpga-project>
+<Project>
+    <Template>FPGA</Template>
+    <Version>5</Version>
+    <Device name="GW1NR-9C" pn="GW1NR-LV9QN88PC6/I5">gw1nr9c-004</Device>
+    <FileList>
+        <File path="src/LED.v" type="file.verilog" enable="1"/>
+        <File path="src/9K_LED_project.cst" type="file.cst" enable="1"/>
+    </FileList>
+</Project>

led/impl/project_process_config.json

@@ -0,0 +1,80 @@
+{
+ "Allow_Duplicate_Modules" : false,
+ "Annotated_Properties_for_Analyst" : true,
+ "BACKGROUND_PROGRAMMING" : "off",
+ "COMPRESS" : false,
+ "CRC_CHECK" : true,
+ "Clock_Conversion" : true,
+ "DONE" : true,
+ "DOWNLOAD_SPEED" : "default",
+ "Default_Enum_Encoding" : "default",
+ "Disable_Insert_Pad" : false,
+ "ENCRYPTION_KEY" : false,
+ "ENCRYPTION_KEY_TEXT" : "00000000000000000000000000000000",
+ "FORMAT" : "binary",
+ "FSM Compiler" : true,
+ "Fanout_Guide" : 10000,
+ "Frequency" : "Auto",
+ "Generate_Constraint_File_of_Ports" : false,
+ "Generate_IBIS_File" : false,
+ "Generate_Plain_Text_Timing_Report" : false,
+ "Generate_Post_PNR_Simulation_Model_File" : false,
+ "Generate_Post_Place_File" : false,
+ "Generate_SDF_File" : false,
+ "GwSyn_Loop_Limit" : 2000,
+ "HOTBOOT" : false,
+ "I2C" : false,
+ "I2C_SLAVE_ADDR" : "00",
+ "Implicit_Initial_Value_Support" : false,
+ "IncludePath" : [
+
+ ],
+ "Incremental_Compile" : "",
+ "Initialize_Primitives" : false,
+ "JTAG" : false,
+ "MODE_IO" : false,
+ "MSPI" : false,
+ "Multiple_File_Compilation_Unit" : true,
+ "Number_of_Critical_Paths" : "",
+ "Number_of_Start/End_Points" : "",
+ "OUTPUT_BASE_NAME" : "9K_LED_project",
+ "POWER_ON_RESET" : false,
+ "PRINT_BSRAM_VALUE" : true,
+ "PROGRAM_DONE_BYPASS" : false,
+ "Pipelining" : true,
+ "PlaceInRegToIob" : true,
+ "PlaceIoRegToIob" : true,
+ "PlaceOutRegToIob" : true,
+ "Place_Option" : "0",
+ "Process_Configuration_Verion" : "1.0",
+ "Promote_Physical_Constraint_Warning_to_Error" : true,
+ "Push_Tristates" : true,
+ "READY" : false,
+ "RECONFIG_N" : false,
+ "Ram_RW_Check" : true,
+ "Report_Auto-Placed_Io_Information" : false,
+ "Resolve_Mixed_Drivers" : false,
+ "Resource_Sharing" : true,
+ "Retiming" : false,
+ "Route_Option" : "0",
+ "Run_Timing_Driven" : true,
+ "SECURE_MODE" : false,
+ "SECURITY_BIT" : true,
+ "SPI_FLASH_ADDR" : "00000000",
+ "SSPI" : false,
+ "Show_All_Warnings" : false,
+ "Synthesis On/Off Implemented as Translate On/Off" : false,
+ "Synthesize_tool" : "GowinSyn",
+ "TopModule" : "",
+ "USERCODE" : "default",
+ "Unused_Pin" : "As_input_tri_stated_with_pull_up",
+ "Update_Compile_Point_Timing_Data" : false,
+ "Use_Clock_Period_for_Unconstrainted IO" : false,
+ "Use_SCF" : false,
+ "VHDL_Standard" : "VHDL_Std_1993",
+ "Verilog_Standard" : "Vlg_Std_2001",
+ "WAKE_UP" : "0",
+ "Write_Vendor_Constraint_File" : true,
+ "dsp_balance" : false,
+ "show_all_warnings" : false
+}

led/src/9K_LED_project.cst

@@ -0,0 +1,24 @@
+//Copyright (C)2014-2021 Gowin Semiconductor Corporation.
+//All rights reserved. 
+//File Title: Physical Constraints file
+//GOWIN Version: 1.9.8.01
+//Part Number: GW1NR-LV9QN88PC6/I5
+//Device: GW1NR-9C
+//Created Time: Thu 03 03 19:24:24 2022
+
+IO_LOC "led[5]" 16;
+IO_PORT "led[5]" PULL_MODE=UP DRIVE=8;
+IO_LOC "led[4]" 15;
+IO_PORT "led[4]" PULL_MODE=UP DRIVE=8;
+IO_LOC "led[3]" 14;
+IO_PORT "led[3]" PULL_MODE=UP DRIVE=8;
+IO_LOC "led[2]" 13;
+IO_PORT "led[2]" PULL_MODE=UP DRIVE=8;
+IO_LOC "led[1]" 11;
+IO_PORT "led[1]" PULL_MODE=UP DRIVE=8;
+IO_LOC "led[0]" 10;
+IO_PORT "led[0]" PULL_MODE=UP DRIVE=8;
+IO_LOC "sys_rst_n" 4;
+IO_PORT "sys_rst_n" PULL_MODE=UP;
+IO_LOC "sys_clk" 52;
+IO_PORT "sys_clk" IO_TYPE=LVCMOS33 PULL_MODE=UP;

led/src/LED.v

@@ -0,0 +1,27 @@
+module led (
+    input sys_clk,          // clk input
+    input sys_rst_n,        // reset input
+    output reg [5:0] led    // 6 LEDS pin
+);
+
+reg [23:0] counter;
+
+always @(posedge sys_clk or negedge sys_rst_n) begin
+    if (!sys_rst_n)
+        counter <= 24'd0;
+    else if (counter < 24'd1349_9999)       // 0.5s delay
+        counter <= counter + 1'd1;
+    else
+        counter <= 24'd0;
+end
+
+always @(posedge sys_clk or negedge sys_rst_n) begin
+    if (!sys_rst_n)
+        led <= 6'b111110;
+    else if (counter == 24'd1349_9999)       // 0.5s delay
+        led[5:0] <= {led[4:0],led[5]};
+    else
+        led <= led;
+end
+
+endmodule