Merge pull request #9 from wonderfullook/main

add spi_lcd

README.md

@@ -1,22 +1,39 @@
 # TangNano-9K-example
-TangNano-9K-example project
 
-### note
-When you meet error code `PR2017`. Do what is shown below.
-![PR2017](.assets/ERROR%20CODE%20PR2017.png "PR2017")
+## note
+
+When you meet error code `PR2017`. Do what is shown below.(Just enable corresponding IO as regular IO)
 
+![PR2017](.assets/ERROR%20CODE%20PR2017.png "PR2017")
 
 ## led
+
 Demo project for drive LED and on board led.
-The related LED tutorial can be found at <https://wiki.sipeed.com/hardware/zh/tang/Tang-Nano/Tang-nano-9k.html>
+The related LED tutorial can be found at <https://wiki.sipeed.com/hardware/en/tang/Tang-Nano-Doc/examples.html>
+
+<img src="./.assets/blink.gif" alt="led">
 
 ## lcd_led
+
 Demo project for drive RGB LCD and on board led.
 
+![lcd](./.assets/lcd_led.jpg)
+
 ## picotiny
+
 A PicoRV32-based SoC example with HDMI terminal from SimpleVout, SPI Flash XIP from picosoc, and custom UART ISP for flash programming. UART baudrate default at `115200`.
 
-See [README.md](picotiny/README.md) for detailed description
+See [README.md](picotiny/README.md) for detailed description. 
+
+- Visit https://wiki.sipeed.com/hardware/en/tang/Tang-Nano-9K/examples/picorv/picorv.html to quick run this example
+- 中文访问 https://wiki.sipeed.com/hardware/zh/tang/Tang-Nano-9K/examples/picorv/picorv.html 来快速使用
+
+![picorv](./.assets/picorv.jpg)
+
+## spi_lcd
+
+This is an example to drive the 1.14 inch lcd screen which can connect with this board.
 
-![picorv](picorv.jpg)
+Be sure match board with screen in the same order
 
+![spi_lcd](./.assets/spi_lcd.jpg)

led/9K_LED_project.gprj.user

@@ -0,0 +1,13 @@
+<?xml version="1" encoding="UTF-8"?>
+<!DOCTYPE ProjectUserData>
+<UserConfig>
+    <Version>1.0</Version>
+    <FlowState>
+        <Process ID="Synthesis" State="0"/>
+        <Process ID="Pnr" State="0"/>
+        <Process ID="Gao" State="0"/>
+        <Process ID="Rtl_Gao" State="0"/>
+    </FlowState>
+    <ResultFileList/>
+    <Ui>000000ff00000001fd000000020000000000000100000001a8fc0200000001fc00000039000001a80000000000fffffffaffffffff0200000003fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000000000000000fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000000000000000fb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff000000000000000000000003000003fc000000bbfc0100000001fc00000000000003fc0000000000fffffffaffffffff0100000002fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000000000000000fb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff0000000000000000000002f8000001a800000004000000040000000800000008fc000000010000000200000003000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e00450064006900740100000099ffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c00730100000153ffffffff0000000000000000</Ui>
+</UserConfig>

spi_lcd/impl/project_process_config.json

@@ -0,0 +1,80 @@
+{
+ "Allow_Duplicate_Modules" : false,
+ "Annotated_Properties_for_Analyst" : true,
+ "BACKGROUND_PROGRAMMING" : "off",
+ "COMPRESS" : false,
+ "CRC_CHECK" : true,
+ "Clock_Conversion" : true,
+ "DONE" : false,
+ "DOWNLOAD_SPEED" : "default",
+ "Default_Enum_Encoding" : "default",
+ "Disable_Insert_Pad" : false,
+ "ENCRYPTION_KEY" : false,
+ "ENCRYPTION_KEY_TEXT" : "00000000000000000000000000000000",
+ "FORMAT" : "binary",
+ "FSM Compiler" : true,
+ "Fanout_Guide" : 10000,
+ "Frequency" : "Auto",
+ "Generate_Constraint_File_of_Ports" : false,
+ "Generate_IBIS_File" : false,
+ "Generate_Plain_Text_Timing_Report" : false,
+ "Generate_Post_PNR_Simulation_Model_File" : false,
+ "Generate_Post_Place_File" : false,
+ "Generate_SDF_File" : false,
+ "GwSyn_Loop_Limit" : 2000,
+ "HOTBOOT" : false,
+ "I2C" : false,
+ "I2C_SLAVE_ADDR" : "00",
+ "Implicit_Initial_Value_Support" : false,
+ "IncludePath" : [
+
+ ],
+ "Incremental_Compile" : "",
+ "Initialize_Primitives" : false,
+ "JTAG" : false,
+ "MODE_IO" : false,
+ "MSPI" : false,
+ "Multiple_File_Compilation_Unit" : true,
+ "Number_of_Critical_Paths" : "",
+ "Number_of_Start/End_Points" : "",
+ "OUTPUT_BASE_NAME" : "lcd114_test",
+ "POWER_ON_RESET" : false,
+ "PRINT_BSRAM_VALUE" : true,
+ "PROGRAM_DONE_BYPASS" : false,
+ "Pipelining" : true,
+ "PlaceInRegToIob" : true,
+ "PlaceIoRegToIob" : true,
+ "PlaceOutRegToIob" : true,
+ "Place_Option" : "0",
+ "Process_Configuration_Verion" : "1.0",
+ "Promote_Physical_Constraint_Warning_to_Error" : true,
+ "Push_Tristates" : true,
+ "READY" : false,
+ "RECONFIG_N" : false,
+ "Ram_RW_Check" : true,
+ "Report_Auto-Placed_Io_Information" : false,
+ "Resolve_Mixed_Drivers" : false,
+ "Resource_Sharing" : true,
+ "Retiming" : false,
+ "Route_Option" : "0",
+ "Run_Timing_Driven" : true,
+ "SECURE_MODE" : false,
+ "SECURITY_BIT" : true,
+ "SPI_FLASH_ADDR" : "00000000",
+ "SSPI" : false,
+ "Show_All_Warnings" : false,
+ "Synthesis On/Off Implemented as Translate On/Off" : false,
+ "Synthesize_tool" : "GowinSyn",
+ "TopModule" : "",
+ "USERCODE" : "default",
+ "Unused_Pin" : "As_input_tri_stated_with_pull_up",
+ "Update_Compile_Point_Timing_Data" : false,
+ "Use_Clock_Period_for_Unconstrainted IO" : false,
+ "Use_SCF" : false,
+ "VHDL_Standard" : "VHDL_Std_1993",
+ "Verilog_Standard" : "Vlg_Std_2001",
+ "WAKE_UP" : "0",
+ "Write_Vendor_Constraint_File" : true,
+ "dsp_balance" : false,
+ "show_all_warnings" : false
+}

spi_lcd/impl/temp/rtl_parser.result

@@ -0,0 +1,10 @@
+[
+ {
+  "InstFile" : "Z:/lcd/Spi_lcd/spi_lcd/src/top.v",
+  "InstLine" : 7,
+  "InstName" : "lcd114_test",
+  "ModuleFile" : "Z:/lcd/Spi_lcd/spi_lcd/src/top.v",
+  "ModuleLine" : 7,
+  "ModuleName" : "lcd114_test"
+ }
+]

spi_lcd/impl/temp/rtl_parser_arg.json

@@ -0,0 +1,16 @@
+{
+ "Files" : [
+  {
+   "Path" : "Z:/lcd/Spi_lcd/spi_lcd/src/top.v",
+   "Type" : "verilog"
+  }
+ ],
+ "IncludePath" : [
+
+ ],
+ "LoopLimit" : 2000,
+ "ResultFile" : "Z:/lcd/Spi_lcd/spi_lcd/impl/temp/rtl_parser.result",
+ "Top" : "",
+ "VerilogStd" : "verilog_2001",
+ "VhdlStd" : "vhdl_93"
+}

spi_lcd/lcd114_test.gprj

@@ -0,0 +1,11 @@
+<?xml version="1" encoding="UTF-8"?>
+<!DOCTYPE gowin-fpga-project>
+<Project>
+    <Template>FPGA</Template>
+    <Version>5</Version>
+    <Device name="GW1NR-9C" pn="GW1NR-LV9QN88PC6/I5">gw1nr9c-004</Device>
+    <FileList>
+        <File path="src/top.v" type="file.verilog" enable="1"/>
+        <File path="src/lcd114_test.cst" type="file.cst" enable="1"/>
+    </FileList>
+</Project>

spi_lcd/sim/lcd114.cr.mti

@@ -0,0 +1,8 @@
+D:/workspace/gowin/lcd114_test/sim/tb_lcd141.v {1 {vlog -work work -vopt -stats=none D:/workspace/gowin/lcd114_test/sim/tb_lcd141.v
+Model Technology ModelSim SE-64 vlog 2019.2 Compiler 2019.04 Apr 17 2019
+-- Compiling module _tb_lcd114_test
+
+Top level modules:
+	_tb_lcd114_test
+
+} {} {}}

spi_lcd/sim/tb_lcd141.v

@@ -0,0 +1,41 @@
+`timescale 1ps/1ps
+
+module _tb_lcd114_test();
+
+reg clk;
+reg resetn;
+
+initial
+begin
+	clk = 0;
+	forever #1 clk = ~clk;
+end
+
+initial begin
+	resetn = 1;
+	#10
+	resetn = 0;
+	#10
+	resetn = 1;
+	#2000
+	resetn = 0;
+	#10
+	resetn = 1;
+	#2000 $stop;
+end
+
+lcd114_test u_lcd114_test(
+	.clk(clk),
+	.resetn(resetn),
+
+	.ser_tx(),
+	.ser_rx(),
+
+	.lcd_resetn(),
+	.lcd_clk(),
+	.lcd_cs(),
+	.lcd_rs(),
+	.lcd_data()
+);
+
+endmodule

spi_lcd/src/lcd114_test.cst

@@ -0,0 +1,26 @@
+//Copyright (C)2014-2022 Gowin Semiconductor Corporation.
+//All rights reserved. 
+//File Title: Physical Constraints file
+//GOWIN Version: 1.9.8.05
+//Part Number: GW1NR-LV9QN88PC6/I5
+//Device: GW1NR-9C
+//Created Time: Mon 06 27 15:31:24 2022
+
+IO_LOC "lcd_data" 77;
+IO_PORT "lcd_data" PULL_MODE=UP DRIVE=8;
+IO_LOC "lcd_rs" 49;
+IO_PORT "lcd_rs" PULL_MODE=UP DRIVE=8;
+IO_LOC "lcd_cs" 48;
+IO_PORT "lcd_cs" PULL_MODE=UP DRIVE=8;
+IO_LOC "lcd_clk" 76;
+IO_PORT "lcd_clk" PULL_MODE=UP DRIVE=8;
+IO_LOC "lcd_resetn" 47;
+IO_PORT "lcd_resetn" PULL_MODE=UP DRIVE=8;
+IO_LOC "ser_tx" 17;
+IO_PORT "ser_tx" PULL_MODE=UP DRIVE=8;
+IO_LOC "clk" 52;
+IO_PORT "clk" PULL_MODE=UP;
+IO_LOC "ser_rx" 18;
+IO_PORT "ser_rx" PULL_MODE=UP;
+IO_LOC "resetn" 4;
+IO_PORT "resetn" PULL_MODE=UP;

spi_lcd/src/top.v

@@ -0,0 +1,267 @@
+// 1.14 inch 240x135 SPI LCD TEST for TANG NANO 9K
+// by fanoble, QQ:87430545
+// 27/6/2022
+
+`timescale 1ps/1ps
+
+module lcd114_test(
+	input clk, // 27M
+	input resetn,
+
+	output ser_tx,
+	input ser_rx,
+
+	output lcd_resetn,
+	output lcd_clk,
+	output lcd_cs,
+	output lcd_rs,
+	output lcd_data
+);
+
+localparam MAX_CMDS = 69;
+
+wire [8:0] init_cmd[MAX_CMDS:0];
+
+assign init_cmd[ 0] = 9'h036;
+assign init_cmd[ 1] = 9'h170;
+assign init_cmd[ 2] = 9'h03A;
+assign init_cmd[ 3] = 9'h105;
+assign init_cmd[ 4] = 9'h0B2;
+assign init_cmd[ 5] = 9'h10C;
+assign init_cmd[ 6] = 9'h10C;
+assign init_cmd[ 7] = 9'h100;
+assign init_cmd[ 8] = 9'h133;
+assign init_cmd[ 9] = 9'h133;
+assign init_cmd[10] = 9'h0B7;
+assign init_cmd[11] = 9'h135;
+assign init_cmd[12] = 9'h0BB;
+assign init_cmd[13] = 9'h119;
+assign init_cmd[14] = 9'h0C0;
+assign init_cmd[15] = 9'h12C;
+assign init_cmd[16] = 9'h0C2;
+assign init_cmd[17] = 9'h101;
+assign init_cmd[18] = 9'h0C3;
+assign init_cmd[19] = 9'h112;
+assign init_cmd[20] = 9'h0C4;
+assign init_cmd[21] = 9'h120;
+assign init_cmd[22] = 9'h0C6;
+assign init_cmd[23] = 9'h10F;
+assign init_cmd[24] = 9'h0D0;
+assign init_cmd[25] = 9'h1A4;
+assign init_cmd[26] = 9'h1A1;
+assign init_cmd[27] = 9'h0E0;
+assign init_cmd[28] = 9'h1D0;
+assign init_cmd[29] = 9'h104;
+assign init_cmd[30] = 9'h10D;
+assign init_cmd[31] = 9'h111;
+assign init_cmd[32] = 9'h113;
+assign init_cmd[33] = 9'h12B;
+assign init_cmd[34] = 9'h13F;
+assign init_cmd[35] = 9'h154;
+assign init_cmd[36] = 9'h14C;
+assign init_cmd[37] = 9'h118;
+assign init_cmd[38] = 9'h10D;
+assign init_cmd[39] = 9'h10B;
+assign init_cmd[40] = 9'h11F;
+assign init_cmd[41] = 9'h123;
+assign init_cmd[42] = 9'h0E1;
+assign init_cmd[43] = 9'h1D0;
+assign init_cmd[44] = 9'h104;
+assign init_cmd[45] = 9'h10C;
+assign init_cmd[46] = 9'h111;
+assign init_cmd[47] = 9'h113;
+assign init_cmd[48] = 9'h12C;
+assign init_cmd[49] = 9'h13F;
+assign init_cmd[50] = 9'h144;
+assign init_cmd[51] = 9'h151;
+assign init_cmd[52] = 9'h12F;
+assign init_cmd[53] = 9'h11F;
+assign init_cmd[54] = 9'h11F;
+assign init_cmd[55] = 9'h120;
+assign init_cmd[56] = 9'h123;
+assign init_cmd[57] = 9'h021;
+assign init_cmd[58] = 9'h029;
+
+assign init_cmd[59] = 9'h02A; // column
+assign init_cmd[60] = 9'h100;
+assign init_cmd[61] = 9'h128;
+assign init_cmd[62] = 9'h101;
+assign init_cmd[63] = 9'h117;
+assign init_cmd[64] = 9'h02B; // row
+assign init_cmd[65] = 9'h100;
+assign init_cmd[66] = 9'h135;
+assign init_cmd[67] = 9'h100;
+assign init_cmd[68] = 9'h1BB;
+assign init_cmd[69] = 9'h02C; // start
+
+localparam INIT_RESET   = 4'b0000; // delay 100ms while reset
+localparam INIT_PREPARE = 4'b0001; // delay 200ms after reset
+localparam INIT_WAKEUP  = 4'b0010; // write cmd 0x11 MIPI_DCS_EXIT_SLEEP_MODE
+localparam INIT_SNOOZE  = 4'b0011; // delay 120ms after wakeup
+localparam INIT_WORKING = 4'b0100; // write command & data
+localparam INIT_DONE    = 4'b0101; // all done
+
+`ifdef MODELTECH
+
+localparam CNT_100MS = 32'd2700000;
+localparam CNT_120MS = 32'd3240000;
+localparam CNT_200MS = 32'd5400000;
+
+`else
+
+// speedup for simulation
+localparam CNT_100MS = 32'd27;
+localparam CNT_120MS = 32'd32;
+localparam CNT_200MS = 32'd54;
+
+`endif
+
+
+reg [ 3:0] init_state;
+reg [ 6:0] cmd_index;
+reg [31:0] clk_cnt;
+reg [ 4:0] bit_loop;
+
+reg [15:0] pixel_cnt;
+
+reg lcd_cs_r;
+reg lcd_rs_r;
+reg lcd_reset_r;
+
+reg [7:0] spi_data;
+
+assign lcd_resetn = lcd_reset_r;
+assign lcd_clk    = ~clk;
+assign lcd_cs     = lcd_cs_r;
+assign lcd_rs     = lcd_rs_r;
+assign lcd_data   = spi_data[7]; // MSB
+
+// gen color bar
+wire [15:0] pixel = (pixel_cnt >= 21600) ? 16'hF800 :
+					(pixel_cnt >= 10800) ? 16'h07E0 : 16'h001F;
+
+always@(posedge clk or negedge resetn) begin
+	if (~resetn) begin
+		clk_cnt <= 0;
+		cmd_index <= 0;
+		init_state <= INIT_RESET;
+
+		lcd_cs_r <= 1;
+		lcd_rs_r <= 1;
+		lcd_reset_r <= 0;
+		spi_data <= 8'hFF;
+		bit_loop <= 0;
+
+		pixel_cnt <= 0;
+	end else begin
+
+		case (init_state)
+
+			INIT_RESET : begin
+				if (clk_cnt == CNT_100MS) begin
+					clk_cnt <= 0;
+					init_state <= INIT_PREPARE;
+					lcd_reset_r <= 1;
+				end else begin
+					clk_cnt <= clk_cnt + 1;
+				end
+			end
+
+			INIT_PREPARE : begin
+				if (clk_cnt == CNT_200MS) begin
+					clk_cnt <= 0;
+					init_state <= INIT_WAKEUP;
+				end else begin
+					clk_cnt <= clk_cnt + 1;
+				end
+			end
+
+			INIT_WAKEUP : begin
+				if (bit_loop == 0) begin
+					// start
+					lcd_cs_r <= 0;
+					lcd_rs_r <= 0;
+					spi_data <= 8'h11; // exit sleep
+					bit_loop <= bit_loop + 1;
+				end else if (bit_loop == 8) begin
+					// end
+					lcd_cs_r <= 1;
+					lcd_rs_r <= 1;
+					bit_loop <= 0;
+					init_state <= INIT_SNOOZE;
+				end else begin
+					// loop
+					spi_data <= { spi_data[6:0], 1'b1 };
+					bit_loop <= bit_loop + 1;
+				end
+			end
+
+			INIT_SNOOZE : begin
+				if (clk_cnt == CNT_120MS) begin
+					clk_cnt <= 0;
+					init_state <= INIT_WORKING;
+				end else begin
+					clk_cnt <= clk_cnt + 1;
+				end
+			end
+
+			INIT_WORKING : begin
+				if (cmd_index == MAX_CMDS + 1) begin
+					init_state <= INIT_DONE;
+				end else begin
+					if (bit_loop == 0) begin
+						// start
+						lcd_cs_r <= 0;
+						lcd_rs_r <= init_cmd[cmd_index][8];
+						spi_data <= init_cmd[cmd_index][7:0];
+						bit_loop <= bit_loop + 1;
+					end else if (bit_loop == 8) begin
+						// end
+						lcd_cs_r <= 1;
+						lcd_rs_r <= 1;
+						bit_loop <= 0;
+						cmd_index <= cmd_index + 1; // next command
+					end else begin
+						// loop
+						spi_data <= { spi_data[6:0], 1'b1 };
+						bit_loop <= bit_loop + 1;
+					end
+				end
+			end
+
+			INIT_DONE : begin
+				if (pixel_cnt == 32400) begin
+					; // stop
+				end else begin
+					if (bit_loop == 0) begin
+						// start
+						lcd_cs_r <= 0;
+						lcd_rs_r <= 1;
+//						spi_data <= 8'hF8; // RED
+						spi_data <= pixel[15:8];
+						bit_loop <= bit_loop + 1;
+					end else if (bit_loop == 8) begin
+						// next byte
+//						spi_data <= 8'h00; // RED
+						spi_data <= pixel[7:0];
+						bit_loop <= bit_loop + 1;
+					end else if (bit_loop == 16) begin
+						// end
+						lcd_cs_r <= 1;
+						lcd_rs_r <= 1;
+						bit_loop <= 0;
+						pixel_cnt <= pixel_cnt + 1; // next pixel
+					end else begin
+						// loop
+						spi_data <= { spi_data[6:0], 1'b1 };
+						bit_loop <= bit_loop + 1;
+					end
+				end
+			end
+
+		endcase
+
+	end
+end
+
+endmodule