Timing Messages

Report Title Gowin Timing Analysis Report
Design File E:\FPGA\Tang_nano_9K_LCD\impl\gwsynthesis\Tang_nano_9K_LCD.vg
Physical Constraints File E:\FPGA\Tang_nano_9K_LCD\src\Tang_nano_9K_LCD.cst
Timing Constraint File E:\FPGA\Tang_nano_9K_LCD\src\Tang_nano_9K_LCD.sdc
GOWIN version V1.9.6.02Beta
Part Number GW1NR-LV9QN88PC6/I5
Created Time Mon Jan 10 14:33:50 2022
Legal Announcement Copyright (C)2014-2020 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 1.14V 85C
Hold Delay Model Fast 1.26V 0C
Numbers of Paths Analyzed 347
Numbers of Endpoints Analyzed 158
Numbers of Falling Endpoints 0
Numbers of Setup Violated Endpoints 0
Numbers of Hold Violated Endpoints 0

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
XTAL Base 37.037 27.000 0.000 18.518 XTAL_IN
LCD_CLK Base 30.030 33.300 0.000 15.015 LCD_CLK
chip_pll/rpll_inst/CLKOUT.default_gen_clk Generated 7.716 129.600 0.000 3.858 XTAL_IN_ibuf/I XTAL chip_pll/rpll_inst/CLKOUT
chip_pll/rpll_inst/CLKOUTP.default_gen_clk Generated 7.716 129.600 0.000 3.858 XTAL_IN_ibuf/I XTAL chip_pll/rpll_inst/CLKOUTP
chip_pll/rpll_inst/CLKOUTD.default_gen_clk Generated 30.864 32.400 0.000 15.432 XTAL_IN_ibuf/I XTAL chip_pll/rpll_inst/CLKOUTD
chip_pll/rpll_inst/CLKOUTD3.default_gen_clk Generated 23.148 43.200 0.000 11.574 XTAL_IN_ibuf/I XTAL chip_pll/rpll_inst/CLKOUTD3

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 XTAL 27.000(MHz) 122.420(MHz) 5 TOP
2 chip_pll/rpll_inst/CLKOUTD.default_gen_clk 32.400(MHz) 108.675(MHz) 5 TOP

No timing paths to get frequency of LCD_CLK!

No timing paths to get frequency of chip_pll/rpll_inst/CLKOUT.default_gen_clk!

No timing paths to get frequency of chip_pll/rpll_inst/CLKOUTP.default_gen_clk!

No timing paths to get frequency of chip_pll/rpll_inst/CLKOUTD3.default_gen_clk!

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
XTAL Setup 0.000 0
XTAL Hold 0.000 0
LCD_CLK Setup 0.000 0
LCD_CLK Hold 0.000 0
chip_pll/rpll_inst/CLKOUT.default_gen_clk Setup 0.000 0
chip_pll/rpll_inst/CLKOUT.default_gen_clk Hold 0.000 0
chip_pll/rpll_inst/CLKOUTP.default_gen_clk Setup 0.000 0
chip_pll/rpll_inst/CLKOUTP.default_gen_clk Hold 0.000 0
chip_pll/rpll_inst/CLKOUTD.default_gen_clk Setup 0.000 0
chip_pll/rpll_inst/CLKOUTD.default_gen_clk Hold 0.000 0
chip_pll/rpll_inst/CLKOUTD3.default_gen_clk Setup 0.000 0
chip_pll/rpll_inst/CLKOUTD3.default_gen_clk Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 21.662 D1/PixelCount_1_s0/Q D1/PixelCount_4_s0/D chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] 30.864 0.000 8.767
2 21.680 D1/PixelCount_1_s0/Q D1/PixelCount_1_s0/D chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] 30.864 0.000 8.749
3 21.868 D1/PixelCount_1_s0/Q D1/PixelCount_3_s0/D chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] 30.864 0.000 8.561
4 21.868 D1/PixelCount_1_s0/Q D1/PixelCount_10_s0/D chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] 30.864 0.000 8.561
5 21.905 D1/PixelCount_1_s0/Q D1/PixelCount_0_s0/D chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] 30.864 0.000 8.524
6 21.905 D1/PixelCount_1_s0/Q D1/PixelCount_6_s0/D chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] 30.864 0.000 8.524
7 22.198 D1/PixelCount_1_s0/Q D1/PixelCount_5_s0/D chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] 30.864 0.000 8.231
8 22.724 D1/PixelCount_1_s0/Q D1/PixelCount_2_s0/D chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] 30.864 0.000 7.705
9 22.759 D1/PixelCount_1_s0/Q D1/PixelCount_8_s0/D chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] 30.864 0.000 7.670
10 22.759 D1/PixelCount_1_s0/Q D1/PixelCount_9_s0/D chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] 30.864 0.000 7.670
11 23.169 D1/PixelCount_1_s0/Q D1/PixelCount_7_s0/D chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] 30.864 0.000 7.260
12 23.435 D1/PixelCount_1_s0/Q D1/LineCount_3_s1/CE chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] 30.864 0.000 7.351
13 23.435 D1/PixelCount_1_s0/Q D1/LineCount_7_s1/CE chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] 30.864 0.000 7.351
14 23.435 D1/PixelCount_1_s0/Q D1/LineCount_0_s1/CE chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] 30.864 0.000 7.351
15 23.435 D1/PixelCount_1_s0/Q D1/LineCount_2_s1/CE chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] 30.864 0.000 7.351
16 23.531 D1/PixelCount_1_s0/Q D1/LineCount_3_s1/D chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] 30.864 0.000 6.899
17 23.775 D1/PixelCount_1_s0/Q D1/LineCount_6_s1/CE chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] 30.864 0.000 7.011
18 23.775 D1/PixelCount_1_s0/Q D1/LineCount_12_s1/CE chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] 30.864 0.000 7.011
19 23.775 D1/PixelCount_1_s0/Q D1/LineCount_13_s1/CE chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] 30.864 0.000 7.011
20 23.775 D1/PixelCount_1_s0/Q D1/LineCount_15_s1/CE chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] 30.864 0.000 7.011
21 23.775 D1/PixelCount_1_s0/Q D1/LineCount_14_s1/CE chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] 30.864 0.000 7.011
22 23.838 D1/PixelCount_1_s0/Q D1/LineCount_2_s1/D chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] 30.864 0.000 6.591
23 23.913 D1/PixelCount_1_s0/Q D1/LineCount_0_s1/D chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] 30.864 0.000 6.516
24 23.913 D1/PixelCount_1_s0/Q D1/LineCount_7_s1/D chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] 30.864 0.000 6.516
25 24.011 D1/PixelCount_1_s0/Q D1/LineCount_10_s1/D chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] 30.864 0.000 6.419

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.571 LED_4_s1/Q LED_5_s2/D XTAL:[R] XTAL:[R] 0.000 0.000 0.571
2 0.571 LED_0_s1/Q LED_1_s1/D XTAL:[R] XTAL:[R] 0.000 0.000 0.571
3 0.571 LED_1_s1/Q LED_2_s1/D XTAL:[R] XTAL:[R] 0.000 0.000 0.571
4 0.571 LED_2_s1/Q LED_3_s1/D XTAL:[R] XTAL:[R] 0.000 0.000 0.571
5 0.709 D1/LineCount_1_s1/Q D1/LineCount_1_s1/D chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] 0.000 0.000 0.709
6 0.709 counter_4_s0/Q counter_4_s0/D XTAL:[R] XTAL:[R] 0.000 0.000 0.709
7 0.709 counter_12_s0/Q counter_12_s0/D XTAL:[R] XTAL:[R] 0.000 0.000 0.709
8 0.710 D1/LineCount_8_s1/Q D1/LineCount_8_s1/D chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] 0.000 0.000 0.710
9 0.710 D1/LineCount_6_s1/Q D1/LineCount_6_s1/D chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] 0.000 0.000 0.710
10 0.710 D1/PixelCount_10_s0/Q D1/PixelCount_10_s0/D chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] 0.000 0.000 0.710
11 0.710 D1/LineCount_10_s1/Q D1/LineCount_10_s1/D chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] 0.000 0.000 0.710
12 0.710 D1/LineCount_9_s1/Q D1/LineCount_9_s1/D chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] 0.000 0.000 0.710
13 0.710 counter_18_s0/Q counter_18_s0/D XTAL:[R] XTAL:[R] 0.000 0.000 0.710
14 0.710 counter_1_s0/Q counter_1_s0/D XTAL:[R] XTAL:[R] 0.000 0.000 0.710
15 0.710 counter_13_s0/Q counter_13_s0/D XTAL:[R] XTAL:[R] 0.000 0.000 0.710
16 0.711 D1/LineCount_4_s1/Q D1/LineCount_4_s1/D chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] 0.000 0.000 0.711
17 0.711 counter_11_s0/Q counter_11_s0/D XTAL:[R] XTAL:[R] 0.000 0.000 0.711
18 0.711 counter_17_s0/Q counter_17_s0/D XTAL:[R] XTAL:[R] 0.000 0.000 0.711
19 0.714 D1/PixelCount_8_s0/Q D1/PixelCount_8_s0/D chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] 0.000 0.000 0.714
20 0.715 D1/PixelCount_3_s0/Q D1/PixelCount_3_s0/D chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] 0.000 0.000 0.715
21 0.722 D1/PixelCount_1_s0/Q D1/PixelCount_1_s0/D chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] 0.000 0.000 0.722
22 0.835 LED_5_s2/Q LED_0_s1/D XTAL:[R] XTAL:[R] 0.000 0.000 0.835
23 0.835 LED_3_s1/Q LED_4_s1/D XTAL:[R] XTAL:[R] 0.000 0.000 0.835
24 0.892 counter_21_s0/Q counter_21_s0/D XTAL:[R] XTAL:[R] 0.000 0.000 0.892
25 0.893 D1/LineCount_2_s1/Q D1/LineCount_2_s1/D chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R] 0.000 0.000 0.893

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Nothing to report!

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Nothing to report!

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 14.104 15.354 1.250 Low Pulse Width chip_pll/rpll_inst/CLKOUTD.default_gen_clk D1/PixelCount_10_s0
2 14.104 15.354 1.250 Low Pulse Width chip_pll/rpll_inst/CLKOUTD.default_gen_clk D1/PixelCount_9_s0
3 14.104 15.354 1.250 Low Pulse Width chip_pll/rpll_inst/CLKOUTD.default_gen_clk D1/PixelCount_8_s0
4 14.104 15.354 1.250 Low Pulse Width chip_pll/rpll_inst/CLKOUTD.default_gen_clk D1/LineCount_6_s1
5 14.104 15.354 1.250 Low Pulse Width chip_pll/rpll_inst/CLKOUTD.default_gen_clk D1/LineCount_2_s1
6 14.104 15.354 1.250 Low Pulse Width chip_pll/rpll_inst/CLKOUTD.default_gen_clk D1/LineCount_0_s1
7 14.104 15.354 1.250 Low Pulse Width chip_pll/rpll_inst/CLKOUTD.default_gen_clk D1/LineCount_15_s1
8 14.104 15.354 1.250 Low Pulse Width chip_pll/rpll_inst/CLKOUTD.default_gen_clk D1/LineCount_1_s1
9 14.104 15.354 1.250 Low Pulse Width chip_pll/rpll_inst/CLKOUTD.default_gen_clk D1/LineCount_5_s1
10 14.104 15.354 1.250 Low Pulse Width chip_pll/rpll_inst/CLKOUTD.default_gen_clk D1/LineCount_4_s1

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 21.662
Data Arrival Time 9.011
Data Required Time 30.673
From D1/PixelCount_1_s0
To D1/PixelCount_4_s0
Launch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
0.000 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
0.244 0.244 tNET RR 1 R12C21[0][A] D1/PixelCount_1_s0/CLK
0.702 0.458 tC2Q RF 23 R12C21[0][A] D1/PixelCount_1_s0/Q
2.208 1.505 tNET FF 1 R13C16[3][A] D1/LineCount_14_s10/I1
3.269 1.061 tINS FR 2 R13C16[3][A] D1/LineCount_14_s10/F
3.689 0.421 tNET RR 1 R13C15[1][B] D1/LineCount_14_s7/I2
4.788 1.099 tINS RF 17 R13C15[1][B] D1/LineCount_14_s7/F
5.642 0.853 tNET FF 1 R14C14[0][B] D1/LineCount_14_s3/I3
6.464 0.822 tINS FF 27 R14C14[0][B] D1/LineCount_14_s3/F
7.979 1.515 tNET FF 1 R13C19[0][B] D1/n94_s1/I0
9.011 1.032 tINS FF 1 R13C19[0][B] D1/n94_s1/F
9.011 0.000 tNET FF 1 R13C19[0][B] D1/PixelCount_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
30.864 30.864 active clock edge time
30.864 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
30.864 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
31.108 0.244 tNET RR 1 R13C19[0][B] D1/PixelCount_4_s0/CLK
31.078 -0.030 tUnc D1/PixelCount_4_s0
30.678 -0.400 tSu 1 R13C19[0][B] D1/PixelCount_4_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 30.864
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay cell: 4.014, 45.787%; route: 4.294, 48.985%; tC2Q: 0.458, 5.228%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.244, 100.000%

Path2

Path Summary:

Slack 21.680
Data Arrival Time 8.993
Data Required Time 30.673
From D1/PixelCount_1_s0
To D1/PixelCount_1_s0
Launch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
0.000 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
0.244 0.244 tNET RR 1 R12C21[0][A] D1/PixelCount_1_s0/CLK
0.702 0.458 tC2Q RF 23 R12C21[0][A] D1/PixelCount_1_s0/Q
2.208 1.505 tNET FF 1 R13C16[3][A] D1/LineCount_14_s10/I1
3.269 1.061 tINS FR 2 R13C16[3][A] D1/LineCount_14_s10/F
3.689 0.421 tNET RR 1 R13C15[1][B] D1/LineCount_14_s7/I2
4.788 1.099 tINS RF 17 R13C15[1][B] D1/LineCount_14_s7/F
5.642 0.853 tNET FF 1 R14C14[0][B] D1/LineCount_14_s3/I3
6.464 0.822 tINS FF 27 R14C14[0][B] D1/LineCount_14_s3/F
7.961 1.497 tNET FF 1 R12C21[0][A] D1/n97_s1/I0
8.993 1.032 tINS FF 1 R12C21[0][A] D1/n97_s1/F
8.993 0.000 tNET FF 1 R12C21[0][A] D1/PixelCount_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
30.864 30.864 active clock edge time
30.864 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
30.864 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
31.108 0.244 tNET RR 1 R12C21[0][A] D1/PixelCount_1_s0/CLK
31.078 -0.030 tUnc D1/PixelCount_1_s0
30.678 -0.400 tSu 1 R12C21[0][A] D1/PixelCount_1_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 30.864
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay cell: 4.014, 45.878%; route: 4.277, 48.884%; tC2Q: 0.458, 5.239%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.244, 100.000%

Path3

Path Summary:

Slack 21.868
Data Arrival Time 8.805
Data Required Time 30.673
From D1/PixelCount_1_s0
To D1/PixelCount_3_s0
Launch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
0.000 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
0.244 0.244 tNET RR 1 R12C21[0][A] D1/PixelCount_1_s0/CLK
0.702 0.458 tC2Q RF 23 R12C21[0][A] D1/PixelCount_1_s0/Q
2.208 1.505 tNET FF 1 R13C16[3][A] D1/LineCount_14_s10/I1
3.269 1.061 tINS FR 2 R13C16[3][A] D1/LineCount_14_s10/F
3.689 0.421 tNET RR 1 R13C15[1][B] D1/LineCount_14_s7/I2
4.788 1.099 tINS RF 17 R13C15[1][B] D1/LineCount_14_s7/F
5.642 0.853 tNET FF 1 R14C14[0][B] D1/LineCount_14_s3/I3
6.464 0.822 tINS FF 27 R14C14[0][B] D1/LineCount_14_s3/F
7.983 1.519 tNET FF 1 R13C19[0][A] D1/n95_s1/I0
8.805 0.822 tINS FF 1 R13C19[0][A] D1/n95_s1/F
8.805 0.000 tNET FF 1 R13C19[0][A] D1/PixelCount_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
30.864 30.864 active clock edge time
30.864 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
30.864 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
31.108 0.244 tNET RR 1 R13C19[0][A] D1/PixelCount_3_s0/CLK
31.078 -0.030 tUnc D1/PixelCount_3_s0
30.678 -0.400 tSu 1 R13C19[0][A] D1/PixelCount_3_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 30.864
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay cell: 3.804, 44.433%; route: 4.299, 50.214%; tC2Q: 0.458, 5.354%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.244, 100.000%

Path4

Path Summary:

Slack 21.868
Data Arrival Time 8.805
Data Required Time 30.673
From D1/PixelCount_1_s0
To D1/PixelCount_10_s0
Launch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
0.000 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
0.244 0.244 tNET RR 1 R12C21[0][A] D1/PixelCount_1_s0/CLK
0.702 0.458 tC2Q RF 23 R12C21[0][A] D1/PixelCount_1_s0/Q
2.208 1.505 tNET FF 1 R13C16[3][A] D1/LineCount_14_s10/I1
3.269 1.061 tINS FR 2 R13C16[3][A] D1/LineCount_14_s10/F
3.689 0.421 tNET RR 1 R13C15[1][B] D1/LineCount_14_s7/I2
4.788 1.099 tINS RF 17 R13C15[1][B] D1/LineCount_14_s7/F
5.642 0.853 tNET FF 1 R14C14[0][B] D1/LineCount_14_s3/I3
6.464 0.822 tINS FF 27 R14C14[0][B] D1/LineCount_14_s3/F
7.983 1.519 tNET FF 1 R13C19[1][A] D1/n88_s1/I2
8.805 0.822 tINS FF 1 R13C19[1][A] D1/n88_s1/F
8.805 0.000 tNET FF 1 R13C19[1][A] D1/PixelCount_10_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
30.864 30.864 active clock edge time
30.864 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
30.864 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
31.108 0.244 tNET RR 1 R13C19[1][A] D1/PixelCount_10_s0/CLK
31.078 -0.030 tUnc D1/PixelCount_10_s0
30.678 -0.400 tSu 1 R13C19[1][A] D1/PixelCount_10_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 30.864
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay cell: 3.804, 44.433%; route: 4.299, 50.214%; tC2Q: 0.458, 5.354%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.244, 100.000%

Path5

Path Summary:

Slack 21.905
Data Arrival Time 8.768
Data Required Time 30.673
From D1/PixelCount_1_s0
To D1/PixelCount_0_s0
Launch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
0.000 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
0.244 0.244 tNET RR 1 R12C21[0][A] D1/PixelCount_1_s0/CLK
0.702 0.458 tC2Q RF 23 R12C21[0][A] D1/PixelCount_1_s0/Q
2.208 1.505 tNET FF 1 R13C16[3][A] D1/LineCount_14_s10/I1
3.269 1.061 tINS FR 2 R13C16[3][A] D1/LineCount_14_s10/F
3.689 0.421 tNET RR 1 R13C15[1][B] D1/LineCount_14_s7/I2
4.788 1.099 tINS RF 17 R13C15[1][B] D1/LineCount_14_s7/F
5.642 0.853 tNET FF 1 R14C14[0][B] D1/LineCount_14_s3/I3
6.464 0.822 tINS FF 27 R14C14[0][B] D1/LineCount_14_s3/F
8.142 1.678 tNET FF 1 R15C20[2][B] D1/n98_s1/I1
8.768 0.626 tINS FF 1 R15C20[2][B] D1/n98_s1/F
8.768 0.000 tNET FF 1 R15C20[2][B] D1/PixelCount_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
30.864 30.864 active clock edge time
30.864 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
30.864 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
31.108 0.244 tNET RR 1 R15C20[2][B] D1/PixelCount_0_s0/CLK
31.078 -0.030 tUnc D1/PixelCount_0_s0
30.678 -0.400 tSu 1 R15C20[2][B] D1/PixelCount_0_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 30.864
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay cell: 3.608, 42.326%; route: 4.458, 52.297%; tC2Q: 0.458, 5.377%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.244, 100.000%

Path6

Path Summary:

Slack 21.905
Data Arrival Time 8.768
Data Required Time 30.673
From D1/PixelCount_1_s0
To D1/PixelCount_6_s0
Launch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
0.000 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
0.244 0.244 tNET RR 1 R12C21[0][A] D1/PixelCount_1_s0/CLK
0.702 0.458 tC2Q RF 23 R12C21[0][A] D1/PixelCount_1_s0/Q
2.208 1.505 tNET FF 1 R13C16[3][A] D1/LineCount_14_s10/I1
3.269 1.061 tINS FR 2 R13C16[3][A] D1/LineCount_14_s10/F
3.689 0.421 tNET RR 1 R13C15[1][B] D1/LineCount_14_s7/I2
4.788 1.099 tINS RF 17 R13C15[1][B] D1/LineCount_14_s7/F
5.642 0.853 tNET FF 1 R14C14[0][B] D1/LineCount_14_s3/I3
6.464 0.822 tINS FF 27 R14C14[0][B] D1/LineCount_14_s3/F
8.142 1.678 tNET FF 1 R15C20[2][A] D1/n92_s1/I0
8.768 0.626 tINS FF 1 R15C20[2][A] D1/n92_s1/F
8.768 0.000 tNET FF 1 R15C20[2][A] D1/PixelCount_6_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
30.864 30.864 active clock edge time
30.864 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
30.864 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
31.108 0.244 tNET RR 1 R15C20[2][A] D1/PixelCount_6_s0/CLK
31.078 -0.030 tUnc D1/PixelCount_6_s0
30.678 -0.400 tSu 1 R15C20[2][A] D1/PixelCount_6_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 30.864
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay cell: 3.608, 42.326%; route: 4.458, 52.297%; tC2Q: 0.458, 5.377%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.244, 100.000%

Path7

Path Summary:

Slack 22.198
Data Arrival Time 8.475
Data Required Time 30.673
From D1/PixelCount_1_s0
To D1/PixelCount_5_s0
Launch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
0.000 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
0.244 0.244 tNET RR 1 R12C21[0][A] D1/PixelCount_1_s0/CLK
0.702 0.458 tC2Q RF 23 R12C21[0][A] D1/PixelCount_1_s0/Q
2.208 1.505 tNET FF 1 R13C16[3][A] D1/LineCount_14_s10/I1
3.269 1.061 tINS FR 2 R13C16[3][A] D1/LineCount_14_s10/F
3.689 0.421 tNET RR 1 R13C15[1][B] D1/LineCount_14_s7/I2
4.788 1.099 tINS RF 17 R13C15[1][B] D1/LineCount_14_s7/F
5.642 0.853 tNET FF 1 R14C14[0][B] D1/LineCount_14_s3/I3
6.464 0.822 tINS FF 27 R14C14[0][B] D1/LineCount_14_s3/F
7.653 1.189 tNET FF 1 R13C18[2][B] D1/n93_s1/I2
8.475 0.822 tINS FF 1 R13C18[2][B] D1/n93_s1/F
8.475 0.000 tNET FF 1 R13C18[2][B] D1/PixelCount_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
30.864 30.864 active clock edge time
30.864 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
30.864 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
31.108 0.244 tNET RR 1 R13C18[2][B] D1/PixelCount_5_s0/CLK
31.078 -0.030 tUnc D1/PixelCount_5_s0
30.678 -0.400 tSu 1 R13C18[2][B] D1/PixelCount_5_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 30.864
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay cell: 3.804, 46.215%; route: 3.969, 48.217%; tC2Q: 0.458, 5.568%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.244, 100.000%

Path8

Path Summary:

Slack 22.724
Data Arrival Time 7.949
Data Required Time 30.673
From D1/PixelCount_1_s0
To D1/PixelCount_2_s0
Launch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
0.000 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
0.244 0.244 tNET RR 1 R12C21[0][A] D1/PixelCount_1_s0/CLK
0.702 0.458 tC2Q RF 23 R12C21[0][A] D1/PixelCount_1_s0/Q
2.208 1.505 tNET FF 1 R13C16[3][A] D1/LineCount_14_s10/I1
3.269 1.061 tINS FR 2 R13C16[3][A] D1/LineCount_14_s10/F
3.689 0.421 tNET RR 1 R13C15[1][B] D1/LineCount_14_s7/I2
4.788 1.099 tINS RF 17 R13C15[1][B] D1/LineCount_14_s7/F
5.642 0.853 tNET FF 1 R14C14[0][B] D1/LineCount_14_s3/I3
6.464 0.822 tINS FF 27 R14C14[0][B] D1/LineCount_14_s3/F
7.323 0.860 tNET FF 1 R13C15[0][B] D1/n96_s1/I2
7.949 0.626 tINS FF 1 R13C15[0][B] D1/n96_s1/F
7.949 0.000 tNET FF 1 R13C15[0][B] D1/PixelCount_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
30.864 30.864 active clock edge time
30.864 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
30.864 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
31.108 0.244 tNET RR 1 R13C15[0][B] D1/PixelCount_2_s0/CLK
31.078 -0.030 tUnc D1/PixelCount_2_s0
30.678 -0.400 tSu 1 R13C15[0][B] D1/PixelCount_2_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 30.864
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay cell: 3.608, 46.824%; route: 3.639, 47.228%; tC2Q: 0.458, 5.948%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.244, 100.000%

Path9

Path Summary:

Slack 22.759
Data Arrival Time 7.914
Data Required Time 30.673
From D1/PixelCount_1_s0
To D1/PixelCount_8_s0
Launch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
0.000 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
0.244 0.244 tNET RR 1 R12C21[0][A] D1/PixelCount_1_s0/CLK
0.702 0.458 tC2Q RF 23 R12C21[0][A] D1/PixelCount_1_s0/Q
2.208 1.505 tNET FF 1 R13C16[3][A] D1/LineCount_14_s10/I1
3.269 1.061 tINS FR 2 R13C16[3][A] D1/LineCount_14_s10/F
3.689 0.421 tNET RR 1 R13C15[1][B] D1/LineCount_14_s7/I2
4.788 1.099 tINS RF 17 R13C15[1][B] D1/LineCount_14_s7/F
5.642 0.853 tNET FF 1 R14C14[0][B] D1/LineCount_14_s3/I3
6.444 0.802 tINS FR 27 R14C14[0][B] D1/LineCount_14_s3/F
6.882 0.438 tNET RR 1 R14C15[0][A] D1/n90_s1/I2
7.914 1.032 tINS RF 1 R14C15[0][A] D1/n90_s1/F
7.914 0.000 tNET FF 1 R14C15[0][A] D1/PixelCount_8_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
30.864 30.864 active clock edge time
30.864 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
30.864 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
31.108 0.244 tNET RR 1 R14C15[0][A] D1/PixelCount_8_s0/CLK
31.078 -0.030 tUnc D1/PixelCount_8_s0
30.678 -0.400 tSu 1 R14C15[0][A] D1/PixelCount_8_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 30.864
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay cell: 3.994, 52.071%; route: 3.218, 41.954%; tC2Q: 0.458, 5.975%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.244, 100.000%

Path10

Path Summary:

Slack 22.759
Data Arrival Time 7.914
Data Required Time 30.673
From D1/PixelCount_1_s0
To D1/PixelCount_9_s0
Launch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
0.000 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
0.244 0.244 tNET RR 1 R12C21[0][A] D1/PixelCount_1_s0/CLK
0.702 0.458 tC2Q RF 23 R12C21[0][A] D1/PixelCount_1_s0/Q
2.208 1.505 tNET FF 1 R13C16[3][A] D1/LineCount_14_s10/I1
3.269 1.061 tINS FR 2 R13C16[3][A] D1/LineCount_14_s10/F
3.689 0.421 tNET RR 1 R13C15[1][B] D1/LineCount_14_s7/I2
4.788 1.099 tINS RF 17 R13C15[1][B] D1/LineCount_14_s7/F
5.642 0.853 tNET FF 1 R14C14[0][B] D1/LineCount_14_s3/I3
6.444 0.802 tINS FR 27 R14C14[0][B] D1/LineCount_14_s3/F
6.882 0.438 tNET RR 1 R14C15[0][B] D1/n89_s1/I2
7.914 1.032 tINS RF 1 R14C15[0][B] D1/n89_s1/F
7.914 0.000 tNET FF 1 R14C15[0][B] D1/PixelCount_9_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
30.864 30.864 active clock edge time
30.864 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
30.864 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
31.108 0.244 tNET RR 1 R14C15[0][B] D1/PixelCount_9_s0/CLK
31.078 -0.030 tUnc D1/PixelCount_9_s0
30.678 -0.400 tSu 1 R14C15[0][B] D1/PixelCount_9_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 30.864
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay cell: 3.994, 52.071%; route: 3.218, 41.954%; tC2Q: 0.458, 5.975%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.244, 100.000%

Path11

Path Summary:

Slack 23.169
Data Arrival Time 7.504
Data Required Time 30.673
From D1/PixelCount_1_s0
To D1/PixelCount_7_s0
Launch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
0.000 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
0.244 0.244 tNET RR 1 R12C21[0][A] D1/PixelCount_1_s0/CLK
0.702 0.458 tC2Q RF 23 R12C21[0][A] D1/PixelCount_1_s0/Q
2.208 1.505 tNET FF 1 R13C16[3][A] D1/LineCount_14_s10/I1
3.269 1.061 tINS FR 2 R13C16[3][A] D1/LineCount_14_s10/F
3.689 0.421 tNET RR 1 R13C15[1][B] D1/LineCount_14_s7/I2
4.788 1.099 tINS RF 17 R13C15[1][B] D1/LineCount_14_s7/F
5.642 0.853 tNET FF 1 R14C14[0][B] D1/LineCount_14_s3/I3
6.444 0.802 tINS FR 27 R14C14[0][B] D1/LineCount_14_s3/F
6.878 0.434 tNET RR 1 R14C15[1][B] D1/n91_s1/I2
7.504 0.626 tINS RF 1 R14C15[1][B] D1/n91_s1/F
7.504 0.000 tNET FF 1 R14C15[1][B] D1/PixelCount_7_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
30.864 30.864 active clock edge time
30.864 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
30.864 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
31.108 0.244 tNET RR 1 R14C15[1][B] D1/PixelCount_7_s0/CLK
31.078 -0.030 tUnc D1/PixelCount_7_s0
30.678 -0.400 tSu 1 R14C15[1][B] D1/PixelCount_7_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 30.864
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay cell: 3.588, 49.419%; route: 3.214, 44.268%; tC2Q: 0.458, 6.313%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.244, 100.000%

Path12

Path Summary:

Slack 23.435
Data Arrival Time 7.595
Data Required Time 31.030
From D1/PixelCount_1_s0
To D1/LineCount_3_s1
Launch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
0.000 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
0.244 0.244 tNET RR 1 R12C21[0][A] D1/PixelCount_1_s0/CLK
0.702 0.458 tC2Q RF 23 R12C21[0][A] D1/PixelCount_1_s0/Q
2.208 1.505 tNET FF 1 R13C16[3][A] D1/LineCount_14_s10/I1
3.269 1.061 tINS FR 2 R13C16[3][A] D1/LineCount_14_s10/F
3.689 0.421 tNET RR 1 R13C15[1][B] D1/LineCount_14_s7/I2
4.788 1.099 tINS RF 17 R13C15[1][B] D1/LineCount_14_s7/F
5.642 0.853 tNET FF 1 R14C14[0][B] D1/LineCount_14_s3/I3
6.444 0.802 tINS FR 27 R14C14[0][B] D1/LineCount_14_s3/F
7.595 1.151 tNET RR 1 R15C13[1][A] D1/LineCount_3_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
30.864 30.864 active clock edge time
30.864 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
30.864 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
31.108 0.244 tNET RR 1 R15C13[1][A] D1/LineCount_3_s1/CLK
31.078 -0.030 tUnc D1/LineCount_3_s1
31.035 -0.043 tSu 1 R15C13[1][A] D1/LineCount_3_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 30.864
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay cell: 2.962, 40.294%; route: 3.931, 53.471%; tC2Q: 0.458, 6.235%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.244, 100.000%

Path13

Path Summary:

Slack 23.435
Data Arrival Time 7.595
Data Required Time 31.030
From D1/PixelCount_1_s0
To D1/LineCount_7_s1
Launch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
0.000 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
0.244 0.244 tNET RR 1 R12C21[0][A] D1/PixelCount_1_s0/CLK
0.702 0.458 tC2Q RF 23 R12C21[0][A] D1/PixelCount_1_s0/Q
2.208 1.505 tNET FF 1 R13C16[3][A] D1/LineCount_14_s10/I1
3.269 1.061 tINS FR 2 R13C16[3][A] D1/LineCount_14_s10/F
3.689 0.421 tNET RR 1 R13C15[1][B] D1/LineCount_14_s7/I2
4.788 1.099 tINS RF 17 R13C15[1][B] D1/LineCount_14_s7/F
5.642 0.853 tNET FF 1 R14C14[0][B] D1/LineCount_14_s3/I3
6.444 0.802 tINS FR 27 R14C14[0][B] D1/LineCount_14_s3/F
7.595 1.151 tNET RR 1 R15C13[2][B] D1/LineCount_7_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
30.864 30.864 active clock edge time
30.864 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
30.864 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
31.108 0.244 tNET RR 1 R15C13[2][B] D1/LineCount_7_s1/CLK
31.078 -0.030 tUnc D1/LineCount_7_s1
31.035 -0.043 tSu 1 R15C13[2][B] D1/LineCount_7_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 30.864
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay cell: 2.962, 40.294%; route: 3.931, 53.471%; tC2Q: 0.458, 6.235%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.244, 100.000%

Path14

Path Summary:

Slack 23.435
Data Arrival Time 7.595
Data Required Time 31.030
From D1/PixelCount_1_s0
To D1/LineCount_0_s1
Launch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
0.000 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
0.244 0.244 tNET RR 1 R12C21[0][A] D1/PixelCount_1_s0/CLK
0.702 0.458 tC2Q RF 23 R12C21[0][A] D1/PixelCount_1_s0/Q
2.208 1.505 tNET FF 1 R13C16[3][A] D1/LineCount_14_s10/I1
3.269 1.061 tINS FR 2 R13C16[3][A] D1/LineCount_14_s10/F
3.689 0.421 tNET RR 1 R13C15[1][B] D1/LineCount_14_s7/I2
4.788 1.099 tINS RF 17 R13C15[1][B] D1/LineCount_14_s7/F
5.642 0.853 tNET FF 1 R14C14[0][B] D1/LineCount_14_s3/I3
6.444 0.802 tINS FR 27 R14C14[0][B] D1/LineCount_14_s3/F
7.595 1.151 tNET RR 1 R15C13[0][B] D1/LineCount_0_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
30.864 30.864 active clock edge time
30.864 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
30.864 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
31.108 0.244 tNET RR 1 R15C13[0][B] D1/LineCount_0_s1/CLK
31.078 -0.030 tUnc D1/LineCount_0_s1
31.035 -0.043 tSu 1 R15C13[0][B] D1/LineCount_0_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 30.864
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay cell: 2.962, 40.294%; route: 3.931, 53.471%; tC2Q: 0.458, 6.235%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.244, 100.000%

Path15

Path Summary:

Slack 23.435
Data Arrival Time 7.595
Data Required Time 31.030
From D1/PixelCount_1_s0
To D1/LineCount_2_s1
Launch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
0.000 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
0.244 0.244 tNET RR 1 R12C21[0][A] D1/PixelCount_1_s0/CLK
0.702 0.458 tC2Q RF 23 R12C21[0][A] D1/PixelCount_1_s0/Q
2.208 1.505 tNET FF 1 R13C16[3][A] D1/LineCount_14_s10/I1
3.269 1.061 tINS FR 2 R13C16[3][A] D1/LineCount_14_s10/F
3.689 0.421 tNET RR 1 R13C15[1][B] D1/LineCount_14_s7/I2
4.788 1.099 tINS RF 17 R13C15[1][B] D1/LineCount_14_s7/F
5.642 0.853 tNET FF 1 R14C14[0][B] D1/LineCount_14_s3/I3
6.444 0.802 tINS FR 27 R14C14[0][B] D1/LineCount_14_s3/F
7.595 1.151 tNET RR 1 R15C13[2][A] D1/LineCount_2_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
30.864 30.864 active clock edge time
30.864 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
30.864 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
31.108 0.244 tNET RR 1 R15C13[2][A] D1/LineCount_2_s1/CLK
31.078 -0.030 tUnc D1/LineCount_2_s1
31.035 -0.043 tSu 1 R15C13[2][A] D1/LineCount_2_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 30.864
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay cell: 2.962, 40.294%; route: 3.931, 53.471%; tC2Q: 0.458, 6.235%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.244, 100.000%

Path16

Path Summary:

Slack 23.531
Data Arrival Time 7.143
Data Required Time 30.673
From D1/PixelCount_1_s0
To D1/LineCount_3_s1
Launch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
0.000 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
0.244 0.244 tNET RR 1 R12C21[0][A] D1/PixelCount_1_s0/CLK
0.702 0.458 tC2Q RF 23 R12C21[0][A] D1/PixelCount_1_s0/Q
2.208 1.505 tNET FF 1 R13C16[3][A] D1/LineCount_14_s10/I1
3.269 1.061 tINS FR 2 R13C16[3][A] D1/LineCount_14_s10/F
3.689 0.421 tNET RR 1 R13C15[1][B] D1/LineCount_14_s7/I2
4.788 1.099 tINS RF 17 R13C15[1][B] D1/LineCount_14_s7/F
6.111 1.322 tNET FF 1 R15C13[1][A] D1/n63_s1/I3
7.143 1.032 tINS FF 1 R15C13[1][A] D1/n63_s1/F
7.143 0.000 tNET FF 1 R15C13[1][A] D1/LineCount_3_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
30.864 30.864 active clock edge time
30.864 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
30.864 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
31.108 0.244 tNET RR 1 R15C13[1][A] D1/LineCount_3_s1/CLK
31.078 -0.030 tUnc D1/LineCount_3_s1
30.678 -0.400 tSu 1 R15C13[1][A] D1/LineCount_3_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 30.864
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay cell: 3.192, 46.270%; route: 3.248, 47.086%; tC2Q: 0.458, 6.644%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.244, 100.000%

Path17

Path Summary:

Slack 23.775
Data Arrival Time 7.255
Data Required Time 31.030
From D1/PixelCount_1_s0
To D1/LineCount_6_s1
Launch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
0.000 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
0.244 0.244 tNET RR 1 R12C21[0][A] D1/PixelCount_1_s0/CLK
0.702 0.458 tC2Q RF 23 R12C21[0][A] D1/PixelCount_1_s0/Q
2.208 1.505 tNET FF 1 R13C16[3][A] D1/LineCount_14_s10/I1
3.269 1.061 tINS FR 2 R13C16[3][A] D1/LineCount_14_s10/F
3.689 0.421 tNET RR 1 R13C15[1][B] D1/LineCount_14_s7/I2
4.788 1.099 tINS RF 17 R13C15[1][B] D1/LineCount_14_s7/F
5.642 0.853 tNET FF 1 R14C14[0][B] D1/LineCount_14_s3/I3
6.444 0.802 tINS FR 27 R14C14[0][B] D1/LineCount_14_s3/F
7.255 0.811 tNET RR 1 R13C13[1][A] D1/LineCount_6_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
30.864 30.864 active clock edge time
30.864 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
30.864 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
31.108 0.244 tNET RR 1 R13C13[1][A] D1/LineCount_6_s1/CLK
31.078 -0.030 tUnc D1/LineCount_6_s1
31.035 -0.043 tSu 1 R13C13[1][A] D1/LineCount_6_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 30.864
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay cell: 2.962, 42.247%; route: 3.591, 51.215%; tC2Q: 0.458, 6.537%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.244, 100.000%

Path18

Path Summary:

Slack 23.775
Data Arrival Time 7.255
Data Required Time 31.030
From D1/PixelCount_1_s0
To D1/LineCount_12_s1
Launch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
0.000 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
0.244 0.244 tNET RR 1 R12C21[0][A] D1/PixelCount_1_s0/CLK
0.702 0.458 tC2Q RF 23 R12C21[0][A] D1/PixelCount_1_s0/Q
2.208 1.505 tNET FF 1 R13C16[3][A] D1/LineCount_14_s10/I1
3.269 1.061 tINS FR 2 R13C16[3][A] D1/LineCount_14_s10/F
3.689 0.421 tNET RR 1 R13C15[1][B] D1/LineCount_14_s7/I2
4.788 1.099 tINS RF 17 R13C15[1][B] D1/LineCount_14_s7/F
5.642 0.853 tNET FF 1 R14C14[0][B] D1/LineCount_14_s3/I3
6.444 0.802 tINS FR 27 R14C14[0][B] D1/LineCount_14_s3/F
7.255 0.811 tNET RR 1 R13C13[1][B] D1/LineCount_12_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
30.864 30.864 active clock edge time
30.864 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
30.864 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
31.108 0.244 tNET RR 1 R13C13[1][B] D1/LineCount_12_s1/CLK
31.078 -0.030 tUnc D1/LineCount_12_s1
31.035 -0.043 tSu 1 R13C13[1][B] D1/LineCount_12_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 30.864
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay cell: 2.962, 42.247%; route: 3.591, 51.215%; tC2Q: 0.458, 6.537%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.244, 100.000%

Path19

Path Summary:

Slack 23.775
Data Arrival Time 7.255
Data Required Time 31.030
From D1/PixelCount_1_s0
To D1/LineCount_13_s1
Launch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
0.000 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
0.244 0.244 tNET RR 1 R12C21[0][A] D1/PixelCount_1_s0/CLK
0.702 0.458 tC2Q RF 23 R12C21[0][A] D1/PixelCount_1_s0/Q
2.208 1.505 tNET FF 1 R13C16[3][A] D1/LineCount_14_s10/I1
3.269 1.061 tINS FR 2 R13C16[3][A] D1/LineCount_14_s10/F
3.689 0.421 tNET RR 1 R13C15[1][B] D1/LineCount_14_s7/I2
4.788 1.099 tINS RF 17 R13C15[1][B] D1/LineCount_14_s7/F
5.642 0.853 tNET FF 1 R14C14[0][B] D1/LineCount_14_s3/I3
6.444 0.802 tINS FR 27 R14C14[0][B] D1/LineCount_14_s3/F
7.255 0.811 tNET RR 1 R13C13[2][A] D1/LineCount_13_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
30.864 30.864 active clock edge time
30.864 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
30.864 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
31.108 0.244 tNET RR 1 R13C13[2][A] D1/LineCount_13_s1/CLK
31.078 -0.030 tUnc D1/LineCount_13_s1
31.035 -0.043 tSu 1 R13C13[2][A] D1/LineCount_13_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 30.864
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay cell: 2.962, 42.247%; route: 3.591, 51.215%; tC2Q: 0.458, 6.537%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.244, 100.000%

Path20

Path Summary:

Slack 23.775
Data Arrival Time 7.255
Data Required Time 31.030
From D1/PixelCount_1_s0
To D1/LineCount_15_s1
Launch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
0.000 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
0.244 0.244 tNET RR 1 R12C21[0][A] D1/PixelCount_1_s0/CLK
0.702 0.458 tC2Q RF 23 R12C21[0][A] D1/PixelCount_1_s0/Q
2.208 1.505 tNET FF 1 R13C16[3][A] D1/LineCount_14_s10/I1
3.269 1.061 tINS FR 2 R13C16[3][A] D1/LineCount_14_s10/F
3.689 0.421 tNET RR 1 R13C15[1][B] D1/LineCount_14_s7/I2
4.788 1.099 tINS RF 17 R13C15[1][B] D1/LineCount_14_s7/F
5.642 0.853 tNET FF 1 R14C14[0][B] D1/LineCount_14_s3/I3
6.444 0.802 tINS FR 27 R14C14[0][B] D1/LineCount_14_s3/F
7.255 0.811 tNET RR 1 R13C13[2][B] D1/LineCount_15_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
30.864 30.864 active clock edge time
30.864 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
30.864 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
31.108 0.244 tNET RR 1 R13C13[2][B] D1/LineCount_15_s1/CLK
31.078 -0.030 tUnc D1/LineCount_15_s1
31.035 -0.043 tSu 1 R13C13[2][B] D1/LineCount_15_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 30.864
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay cell: 2.962, 42.247%; route: 3.591, 51.215%; tC2Q: 0.458, 6.537%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.244, 100.000%

Path21

Path Summary:

Slack 23.775
Data Arrival Time 7.255
Data Required Time 31.030
From D1/PixelCount_1_s0
To D1/LineCount_14_s1
Launch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
0.000 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
0.244 0.244 tNET RR 1 R12C21[0][A] D1/PixelCount_1_s0/CLK
0.702 0.458 tC2Q RF 23 R12C21[0][A] D1/PixelCount_1_s0/Q
2.208 1.505 tNET FF 1 R13C16[3][A] D1/LineCount_14_s10/I1
3.269 1.061 tINS FR 2 R13C16[3][A] D1/LineCount_14_s10/F
3.689 0.421 tNET RR 1 R13C15[1][B] D1/LineCount_14_s7/I2
4.788 1.099 tINS RF 17 R13C15[1][B] D1/LineCount_14_s7/F
5.642 0.853 tNET FF 1 R14C14[0][B] D1/LineCount_14_s3/I3
6.444 0.802 tINS FR 27 R14C14[0][B] D1/LineCount_14_s3/F
7.255 0.811 tNET RR 1 R13C13[0][B] D1/LineCount_14_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
30.864 30.864 active clock edge time
30.864 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
30.864 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
31.108 0.244 tNET RR 1 R13C13[0][B] D1/LineCount_14_s1/CLK
31.078 -0.030 tUnc D1/LineCount_14_s1
31.035 -0.043 tSu 1 R13C13[0][B] D1/LineCount_14_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 30.864
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay cell: 2.962, 42.247%; route: 3.591, 51.215%; tC2Q: 0.458, 6.537%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.244, 100.000%

Path22

Path Summary:

Slack 23.838
Data Arrival Time 6.835
Data Required Time 30.673
From D1/PixelCount_1_s0
To D1/LineCount_2_s1
Launch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
0.000 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
0.244 0.244 tNET RR 1 R12C21[0][A] D1/PixelCount_1_s0/CLK
0.702 0.458 tC2Q RF 23 R12C21[0][A] D1/PixelCount_1_s0/Q
2.208 1.505 tNET FF 1 R13C16[3][A] D1/LineCount_14_s10/I1
3.269 1.061 tINS FR 2 R13C16[3][A] D1/LineCount_14_s10/F
3.689 0.421 tNET RR 1 R13C15[1][B] D1/LineCount_14_s7/I2
4.788 1.099 tINS RF 17 R13C15[1][B] D1/LineCount_14_s7/F
5.803 1.015 tNET FF 1 R15C13[2][A] D1/n64_s3/I3
6.835 1.032 tINS FF 1 R15C13[2][A] D1/n64_s3/F
6.835 0.000 tNET FF 1 R15C13[2][A] D1/LineCount_2_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
30.864 30.864 active clock edge time
30.864 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
30.864 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
31.108 0.244 tNET RR 1 R15C13[2][A] D1/LineCount_2_s1/CLK
31.078 -0.030 tUnc D1/LineCount_2_s1
30.678 -0.400 tSu 1 R15C13[2][A] D1/LineCount_2_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 30.864
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay cell: 3.192, 48.428%; route: 2.941, 44.619%; tC2Q: 0.458, 6.954%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.244, 100.000%

Path23

Path Summary:

Slack 23.913
Data Arrival Time 6.760
Data Required Time 30.673
From D1/PixelCount_1_s0
To D1/LineCount_0_s1
Launch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
0.000 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
0.244 0.244 tNET RR 1 R12C21[0][A] D1/PixelCount_1_s0/CLK
0.702 0.458 tC2Q RF 23 R12C21[0][A] D1/PixelCount_1_s0/Q
2.208 1.505 tNET FF 1 R13C16[3][A] D1/LineCount_14_s10/I1
3.269 1.061 tINS FR 2 R13C16[3][A] D1/LineCount_14_s10/F
3.689 0.421 tNET RR 1 R13C15[1][B] D1/LineCount_14_s7/I2
4.788 1.099 tINS RF 17 R13C15[1][B] D1/LineCount_14_s7/F
6.134 1.346 tNET FF 1 R15C13[0][B] D1/n66_s1/I1
6.760 0.626 tINS FF 1 R15C13[0][B] D1/n66_s1/F
6.760 0.000 tNET FF 1 R15C13[0][B] D1/LineCount_0_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
30.864 30.864 active clock edge time
30.864 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
30.864 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
31.108 0.244 tNET RR 1 R15C13[0][B] D1/LineCount_0_s1/CLK
31.078 -0.030 tUnc D1/LineCount_0_s1
30.678 -0.400 tSu 1 R15C13[0][B] D1/LineCount_0_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 30.864
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay cell: 2.786, 42.756%; route: 3.272, 50.210%; tC2Q: 0.458, 7.034%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.244, 100.000%

Path24

Path Summary:

Slack 23.913
Data Arrival Time 6.760
Data Required Time 30.673
From D1/PixelCount_1_s0
To D1/LineCount_7_s1
Launch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
0.000 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
0.244 0.244 tNET RR 1 R12C21[0][A] D1/PixelCount_1_s0/CLK
0.702 0.458 tC2Q RF 23 R12C21[0][A] D1/PixelCount_1_s0/Q
2.208 1.505 tNET FF 1 R13C16[3][A] D1/LineCount_14_s10/I1
3.269 1.061 tINS FR 2 R13C16[3][A] D1/LineCount_14_s10/F
3.689 0.421 tNET RR 1 R13C15[1][B] D1/LineCount_14_s7/I2
4.788 1.099 tINS RF 17 R13C15[1][B] D1/LineCount_14_s7/F
6.134 1.346 tNET FF 1 R15C13[2][B] D1/n59_s1/I3
6.760 0.626 tINS FF 1 R15C13[2][B] D1/n59_s1/F
6.760 0.000 tNET FF 1 R15C13[2][B] D1/LineCount_7_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
30.864 30.864 active clock edge time
30.864 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
30.864 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
31.108 0.244 tNET RR 1 R15C13[2][B] D1/LineCount_7_s1/CLK
31.078 -0.030 tUnc D1/LineCount_7_s1
30.678 -0.400 tSu 1 R15C13[2][B] D1/LineCount_7_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 30.864
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay cell: 2.786, 42.756%; route: 3.272, 50.210%; tC2Q: 0.458, 7.034%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.244, 100.000%

Path25

Path Summary:

Slack 24.011
Data Arrival Time 6.663
Data Required Time 30.673
From D1/PixelCount_1_s0
To D1/LineCount_10_s1
Launch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
0.000 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
0.244 0.244 tNET RR 1 R12C21[0][A] D1/PixelCount_1_s0/CLK
0.702 0.458 tC2Q RF 23 R12C21[0][A] D1/PixelCount_1_s0/Q
2.208 1.505 tNET FF 1 R13C16[3][A] D1/LineCount_14_s10/I1
3.269 1.061 tINS FR 2 R13C16[3][A] D1/LineCount_14_s10/F
3.689 0.421 tNET RR 1 R13C15[1][B] D1/LineCount_14_s7/I2
4.788 1.099 tINS RF 17 R13C15[1][B] D1/LineCount_14_s7/F
5.631 0.842 tNET FF 1 R14C13[1][A] D1/n56_s1/I2
6.663 1.032 tINS FF 1 R14C13[1][A] D1/n56_s1/F
6.663 0.000 tNET FF 1 R14C13[1][A] D1/LineCount_10_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
30.864 30.864 active clock edge time
30.864 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
30.864 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
31.108 0.244 tNET RR 1 R14C13[1][A] D1/LineCount_10_s1/CLK
31.078 -0.030 tUnc D1/LineCount_10_s1
30.678 -0.400 tSu 1 R14C13[1][A] D1/LineCount_10_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 30.864
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.244, 100.000%
Arrival Data Path Delay cell: 3.192, 49.730%; route: 2.768, 43.129%; tC2Q: 0.458, 7.141%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.244, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.571
Data Arrival Time 1.600
Data Required Time 1.029
From LED_4_s1
To LED_5_s2
Launch Clk XTAL:[R]
Latch Clk XTAL:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 XTAL
0.000 0.000 tCL RR 1 IOR17[A] XTAL_IN_ibuf/I
0.844 0.844 tINS RR 29 IOR17[A] XTAL_IN_ibuf/O
1.029 0.185 tNET RR 1 R14C30[0][B] LED_4_s1/CLK
1.362 0.333 tC2Q RR 2 R14C30[0][B] LED_4_s1/Q
1.600 0.238 tNET RR 1 R14C30[0][A] LED_5_s2/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 XTAL
0.000 0.000 tCL RR 1 IOR17[A] XTAL_IN_ibuf/I
0.844 0.844 tINS RR 29 IOR17[A] XTAL_IN_ibuf/O
1.029 0.185 tNET RR 1 R14C30[0][A] LED_5_s2/CLK
1.059 0.030 tUnc LED_5_s2
1.059 0.000 tHld 1 R14C30[0][A] LED_5_s2

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.844, 82.061%; route: 0.185, 17.939%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.238, 41.613%; tC2Q: 0.333, 58.387%
Required Clock Path Delay cell: 0.844, 82.061%; route: 0.185, 17.939%

Path2

Path Summary:

Slack 0.571
Data Arrival Time 1.600
Data Required Time 1.029
From LED_0_s1
To LED_1_s1
Launch Clk XTAL:[R]
Latch Clk XTAL:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 XTAL
0.000 0.000 tCL RR 1 IOR17[A] XTAL_IN_ibuf/I
0.844 0.844 tINS RR 29 IOR17[A] XTAL_IN_ibuf/O
1.029 0.185 tNET RR 1 R14C29[2][B] LED_0_s1/CLK
1.362 0.333 tC2Q RR 2 R14C29[2][B] LED_0_s1/Q
1.600 0.238 tNET RR 1 R14C29[2][A] LED_1_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 XTAL
0.000 0.000 tCL RR 1 IOR17[A] XTAL_IN_ibuf/I
0.844 0.844 tINS RR 29 IOR17[A] XTAL_IN_ibuf/O
1.029 0.185 tNET RR 1 R14C29[2][A] LED_1_s1/CLK
1.059 0.030 tUnc LED_1_s1
1.059 0.000 tHld 1 R14C29[2][A] LED_1_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.844, 82.061%; route: 0.185, 17.939%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.238, 41.613%; tC2Q: 0.333, 58.387%
Required Clock Path Delay cell: 0.844, 82.061%; route: 0.185, 17.939%

Path3

Path Summary:

Slack 0.571
Data Arrival Time 1.600
Data Required Time 1.029
From LED_1_s1
To LED_2_s1
Launch Clk XTAL:[R]
Latch Clk XTAL:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 XTAL
0.000 0.000 tCL RR 1 IOR17[A] XTAL_IN_ibuf/I
0.844 0.844 tINS RR 29 IOR17[A] XTAL_IN_ibuf/O
1.029 0.185 tNET RR 1 R14C29[2][A] LED_1_s1/CLK
1.362 0.333 tC2Q RR 2 R14C29[2][A] LED_1_s1/Q
1.600 0.238 tNET RR 1 R14C29[0][B] LED_2_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 XTAL
0.000 0.000 tCL RR 1 IOR17[A] XTAL_IN_ibuf/I
0.844 0.844 tINS RR 29 IOR17[A] XTAL_IN_ibuf/O
1.029 0.185 tNET RR 1 R14C29[0][B] LED_2_s1/CLK
1.059 0.030 tUnc LED_2_s1
1.059 0.000 tHld 1 R14C29[0][B] LED_2_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.844, 82.061%; route: 0.185, 17.939%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.238, 41.613%; tC2Q: 0.333, 58.387%
Required Clock Path Delay cell: 0.844, 82.061%; route: 0.185, 17.939%

Path4

Path Summary:

Slack 0.571
Data Arrival Time 1.600
Data Required Time 1.029
From LED_2_s1
To LED_3_s1
Launch Clk XTAL:[R]
Latch Clk XTAL:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 XTAL
0.000 0.000 tCL RR 1 IOR17[A] XTAL_IN_ibuf/I
0.844 0.844 tINS RR 29 IOR17[A] XTAL_IN_ibuf/O
1.029 0.185 tNET RR 1 R14C29[0][B] LED_2_s1/CLK
1.362 0.333 tC2Q RR 2 R14C29[0][B] LED_2_s1/Q
1.600 0.238 tNET RR 1 R14C29[0][A] LED_3_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 XTAL
0.000 0.000 tCL RR 1 IOR17[A] XTAL_IN_ibuf/I
0.844 0.844 tINS RR 29 IOR17[A] XTAL_IN_ibuf/O
1.029 0.185 tNET RR 1 R14C29[0][A] LED_3_s1/CLK
1.059 0.030 tUnc LED_3_s1
1.059 0.000 tHld 1 R14C29[0][A] LED_3_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.844, 82.061%; route: 0.185, 17.939%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.238, 41.613%; tC2Q: 0.333, 58.387%
Required Clock Path Delay cell: 0.844, 82.061%; route: 0.185, 17.939%

Path5

Path Summary:

Slack 0.709
Data Arrival Time 0.893
Data Required Time 0.185
From D1/LineCount_1_s1
To D1/LineCount_1_s1
Launch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
0.000 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
0.185 0.185 tNET RR 1 R14C14[0][A] D1/LineCount_1_s1/CLK
0.518 0.333 tC2Q RR 7 R14C14[0][A] D1/LineCount_1_s1/Q
0.521 0.004 tNET RR 1 R14C14[0][A] D1/n65_s1/I1
0.893 0.372 tINS RF 1 R14C14[0][A] D1/n65_s1/F
0.893 0.000 tNET FF 1 R14C14[0][A] D1/LineCount_1_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
0.000 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
0.185 0.185 tNET RR 1 R14C14[0][A] D1/LineCount_1_s1/CLK
0.215 0.030 tUnc D1/LineCount_1_s1
0.215 0.000 tHld 1 R14C14[0][A] D1/LineCount_1_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.185, 100.000%

Path6

Path Summary:

Slack 0.709
Data Arrival Time 1.738
Data Required Time 1.029
From counter_4_s0
To counter_4_s0
Launch Clk XTAL:[R]
Latch Clk XTAL:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 XTAL
0.000 0.000 tCL RR 1 IOR17[A] XTAL_IN_ibuf/I
0.844 0.844 tINS RR 29 IOR17[A] XTAL_IN_ibuf/O
1.029 0.185 tNET RR 1 R13C29[1][A] counter_4_s0/CLK
1.362 0.333 tC2Q RR 4 R13C29[1][A] counter_4_s0/Q
1.366 0.004 tNET RR 1 R13C29[1][A] n90_s1/I1
1.738 0.372 tINS RF 1 R13C29[1][A] n90_s1/F
1.738 0.000 tNET FF 1 R13C29[1][A] counter_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 XTAL
0.000 0.000 tCL RR 1 IOR17[A] XTAL_IN_ibuf/I
0.844 0.844 tINS RR 29 IOR17[A] XTAL_IN_ibuf/O
1.029 0.185 tNET RR 1 R13C29[1][A] counter_4_s0/CLK
1.059 0.030 tUnc counter_4_s0
1.059 0.000 tHld 1 R13C29[1][A] counter_4_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.844, 82.061%; route: 0.185, 17.939%
Arrival Data Path Delay cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay cell: 0.844, 82.061%; route: 0.185, 17.939%

Path7

Path Summary:

Slack 0.709
Data Arrival Time 1.738
Data Required Time 1.029
From counter_12_s0
To counter_12_s0
Launch Clk XTAL:[R]
Latch Clk XTAL:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 XTAL
0.000 0.000 tCL RR 1 IOR17[A] XTAL_IN_ibuf/I
0.844 0.844 tINS RR 29 IOR17[A] XTAL_IN_ibuf/O
1.029 0.185 tNET RR 1 R13C30[1][A] counter_12_s0/CLK
1.362 0.333 tC2Q RR 3 R13C30[1][A] counter_12_s0/Q
1.366 0.004 tNET RR 1 R13C30[1][A] n82_s1/I2
1.738 0.372 tINS RF 1 R13C30[1][A] n82_s1/F
1.738 0.000 tNET FF 1 R13C30[1][A] counter_12_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 XTAL
0.000 0.000 tCL RR 1 IOR17[A] XTAL_IN_ibuf/I
0.844 0.844 tINS RR 29 IOR17[A] XTAL_IN_ibuf/O
1.029 0.185 tNET RR 1 R13C30[1][A] counter_12_s0/CLK
1.059 0.030 tUnc counter_12_s0
1.059 0.000 tHld 1 R13C30[1][A] counter_12_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.844, 82.061%; route: 0.185, 17.939%
Arrival Data Path Delay cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay cell: 0.844, 82.061%; route: 0.185, 17.939%

Path8

Path Summary:

Slack 0.710
Data Arrival Time 0.895
Data Required Time 0.185
From D1/LineCount_8_s1
To D1/LineCount_8_s1
Launch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
0.000 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
0.185 0.185 tNET RR 1 R15C14[0][A] D1/LineCount_8_s1/CLK
0.518 0.333 tC2Q RR 4 R15C14[0][A] D1/LineCount_8_s1/Q
0.523 0.005 tNET RR 1 R15C14[0][A] D1/n58_s1/I2
0.895 0.372 tINS RF 1 R15C14[0][A] D1/n58_s1/F
0.895 0.000 tNET FF 1 R15C14[0][A] D1/LineCount_8_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
0.000 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
0.185 0.185 tNET RR 1 R15C14[0][A] D1/LineCount_8_s1/CLK
0.215 0.030 tUnc D1/LineCount_8_s1
0.215 0.000 tHld 1 R15C14[0][A] D1/LineCount_8_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.185, 100.000%

Path9

Path Summary:

Slack 0.710
Data Arrival Time 0.895
Data Required Time 0.185
From D1/LineCount_6_s1
To D1/LineCount_6_s1
Launch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
0.000 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
0.185 0.185 tNET RR 1 R13C13[1][A] D1/LineCount_6_s1/CLK
0.518 0.333 tC2Q RR 5 R13C13[1][A] D1/LineCount_6_s1/Q
0.523 0.005 tNET RR 1 R13C13[1][A] D1/n60_s1/I0
0.895 0.372 tINS RF 1 R13C13[1][A] D1/n60_s1/F
0.895 0.000 tNET FF 1 R13C13[1][A] D1/LineCount_6_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
0.000 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
0.185 0.185 tNET RR 1 R13C13[1][A] D1/LineCount_6_s1/CLK
0.215 0.030 tUnc D1/LineCount_6_s1
0.215 0.000 tHld 1 R13C13[1][A] D1/LineCount_6_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.185, 100.000%

Path10

Path Summary:

Slack 0.710
Data Arrival Time 0.895
Data Required Time 0.185
From D1/PixelCount_10_s0
To D1/PixelCount_10_s0
Launch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
0.000 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
0.185 0.185 tNET RR 1 R13C19[1][A] D1/PixelCount_10_s0/CLK
0.518 0.333 tC2Q RR 23 R13C19[1][A] D1/PixelCount_10_s0/Q
0.523 0.005 tNET RR 1 R13C19[1][A] D1/n88_s1/I3
0.895 0.372 tINS RF 1 R13C19[1][A] D1/n88_s1/F
0.895 0.000 tNET FF 1 R13C19[1][A] D1/PixelCount_10_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
0.000 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
0.185 0.185 tNET RR 1 R13C19[1][A] D1/PixelCount_10_s0/CLK
0.215 0.030 tUnc D1/PixelCount_10_s0
0.215 0.000 tHld 1 R13C19[1][A] D1/PixelCount_10_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.185, 100.000%

Path11

Path Summary:

Slack 0.710
Data Arrival Time 0.895
Data Required Time 0.185
From D1/LineCount_10_s1
To D1/LineCount_10_s1
Launch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
0.000 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
0.185 0.185 tNET RR 1 R14C13[1][A] D1/LineCount_10_s1/CLK
0.518 0.333 tC2Q RR 7 R14C13[1][A] D1/LineCount_10_s1/Q
0.523 0.005 tNET RR 1 R14C13[1][A] D1/n56_s1/I0
0.895 0.372 tINS RF 1 R14C13[1][A] D1/n56_s1/F
0.895 0.000 tNET FF 1 R14C13[1][A] D1/LineCount_10_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
0.000 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
0.185 0.185 tNET RR 1 R14C13[1][A] D1/LineCount_10_s1/CLK
0.215 0.030 tUnc D1/LineCount_10_s1
0.215 0.000 tHld 1 R14C13[1][A] D1/LineCount_10_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.185, 100.000%

Path12

Path Summary:

Slack 0.710
Data Arrival Time 0.895
Data Required Time 0.185
From D1/LineCount_9_s1
To D1/LineCount_9_s1
Launch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
0.000 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
0.185 0.185 tNET RR 1 R14C14[1][A] D1/LineCount_9_s1/CLK
0.518 0.333 tC2Q RR 5 R14C14[1][A] D1/LineCount_9_s1/Q
0.523 0.005 tNET RR 1 R14C14[1][A] D1/n57_s1/I0
0.895 0.372 tINS RF 1 R14C14[1][A] D1/n57_s1/F
0.895 0.000 tNET FF 1 R14C14[1][A] D1/LineCount_9_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
0.000 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
0.185 0.185 tNET RR 1 R14C14[1][A] D1/LineCount_9_s1/CLK
0.215 0.030 tUnc D1/LineCount_9_s1
0.215 0.000 tHld 1 R14C14[1][A] D1/LineCount_9_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.185, 100.000%

Path13

Path Summary:

Slack 0.710
Data Arrival Time 1.739
Data Required Time 1.029
From counter_18_s0
To counter_18_s0
Launch Clk XTAL:[R]
Latch Clk XTAL:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 XTAL
0.000 0.000 tCL RR 1 IOR17[A] XTAL_IN_ibuf/I
0.844 0.844 tINS RR 29 IOR17[A] XTAL_IN_ibuf/O
1.029 0.185 tNET RR 1 R14C32[0][A] counter_18_s0/CLK
1.362 0.333 tC2Q RR 5 R14C32[0][A] counter_18_s0/Q
1.367 0.005 tNET RR 1 R14C32[0][A] n76_s1/I2
1.739 0.372 tINS RF 1 R14C32[0][A] n76_s1/F
1.739 0.000 tNET FF 1 R14C32[0][A] counter_18_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 XTAL
0.000 0.000 tCL RR 1 IOR17[A] XTAL_IN_ibuf/I
0.844 0.844 tINS RR 29 IOR17[A] XTAL_IN_ibuf/O
1.029 0.185 tNET RR 1 R14C32[0][A] counter_18_s0/CLK
1.059 0.030 tUnc counter_18_s0
1.059 0.000 tHld 1 R14C32[0][A] counter_18_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.844, 82.061%; route: 0.185, 17.939%
Arrival Data Path Delay cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945%
Required Clock Path Delay cell: 0.844, 82.061%; route: 0.185, 17.939%

Path14

Path Summary:

Slack 0.710
Data Arrival Time 1.739
Data Required Time 1.029
From counter_1_s0
To counter_1_s0
Launch Clk XTAL:[R]
Latch Clk XTAL:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 XTAL
0.000 0.000 tCL RR 1 IOR17[A] XTAL_IN_ibuf/I
0.844 0.844 tINS RR 29 IOR17[A] XTAL_IN_ibuf/O
1.029 0.185 tNET RR 1 R13C29[0][A] counter_1_s0/CLK
1.362 0.333 tC2Q RR 5 R13C29[0][A] counter_1_s0/Q
1.367 0.005 tNET RR 1 R13C29[0][A] n93_s1/I2
1.739 0.372 tINS RF 1 R13C29[0][A] n93_s1/F
1.739 0.000 tNET FF 1 R13C29[0][A] counter_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 XTAL
0.000 0.000 tCL RR 1 IOR17[A] XTAL_IN_ibuf/I
0.844 0.844 tINS RR 29 IOR17[A] XTAL_IN_ibuf/O
1.029 0.185 tNET RR 1 R13C29[0][A] counter_1_s0/CLK
1.059 0.030 tUnc counter_1_s0
1.059 0.000 tHld 1 R13C29[0][A] counter_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.844, 82.061%; route: 0.185, 17.939%
Arrival Data Path Delay cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945%
Required Clock Path Delay cell: 0.844, 82.061%; route: 0.185, 17.939%

Path15

Path Summary:

Slack 0.710
Data Arrival Time 1.739
Data Required Time 1.029
From counter_13_s0
To counter_13_s0
Launch Clk XTAL:[R]
Latch Clk XTAL:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 XTAL
0.000 0.000 tCL RR 1 IOR17[A] XTAL_IN_ibuf/I
0.844 0.844 tINS RR 29 IOR17[A] XTAL_IN_ibuf/O
1.029 0.185 tNET RR 1 R14C31[0][A] counter_13_s0/CLK
1.362 0.333 tC2Q RR 6 R14C31[0][A] counter_13_s0/Q
1.367 0.005 tNET RR 1 R14C31[0][A] n81_s1/I0
1.739 0.372 tINS RF 1 R14C31[0][A] n81_s1/F
1.739 0.000 tNET FF 1 R14C31[0][A] counter_13_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 XTAL
0.000 0.000 tCL RR 1 IOR17[A] XTAL_IN_ibuf/I
0.844 0.844 tINS RR 29 IOR17[A] XTAL_IN_ibuf/O
1.029 0.185 tNET RR 1 R14C31[0][A] counter_13_s0/CLK
1.059 0.030 tUnc counter_13_s0
1.059 0.000 tHld 1 R14C31[0][A] counter_13_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.844, 82.061%; route: 0.185, 17.939%
Arrival Data Path Delay cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945%
Required Clock Path Delay cell: 0.844, 82.061%; route: 0.185, 17.939%

Path16

Path Summary:

Slack 0.711
Data Arrival Time 0.896
Data Required Time 0.185
From D1/LineCount_4_s1
To D1/LineCount_4_s1
Launch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
0.000 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
0.185 0.185 tNET RR 1 R13C14[0][A] D1/LineCount_4_s1/CLK
0.518 0.333 tC2Q RR 6 R13C14[0][A] D1/LineCount_4_s1/Q
0.524 0.006 tNET RR 1 R13C14[0][A] D1/n62_s1/I0
0.896 0.372 tINS RF 1 R13C14[0][A] D1/n62_s1/F
0.896 0.000 tNET FF 1 R13C14[0][A] D1/LineCount_4_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
0.000 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
0.185 0.185 tNET RR 1 R13C14[0][A] D1/LineCount_4_s1/CLK
0.215 0.030 tUnc D1/LineCount_4_s1
0.215 0.000 tHld 1 R13C14[0][A] D1/LineCount_4_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay cell: 0.372, 52.303%; route: 0.006, 0.830%; tC2Q: 0.333, 46.867%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.185, 100.000%

Path17

Path Summary:

Slack 0.711
Data Arrival Time 1.740
Data Required Time 1.029
From counter_11_s0
To counter_11_s0
Launch Clk XTAL:[R]
Latch Clk XTAL:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 XTAL
0.000 0.000 tCL RR 1 IOR17[A] XTAL_IN_ibuf/I
0.844 0.844 tINS RR 29 IOR17[A] XTAL_IN_ibuf/O
1.029 0.185 tNET RR 1 R13C30[0][A] counter_11_s0/CLK
1.362 0.333 tC2Q RR 5 R13C30[0][A] counter_11_s0/Q
1.368 0.006 tNET RR 1 R13C30[0][A] n83_s1/I2
1.740 0.372 tINS RF 1 R13C30[0][A] n83_s1/F
1.740 0.000 tNET FF 1 R13C30[0][A] counter_11_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 XTAL
0.000 0.000 tCL RR 1 IOR17[A] XTAL_IN_ibuf/I
0.844 0.844 tINS RR 29 IOR17[A] XTAL_IN_ibuf/O
1.029 0.185 tNET RR 1 R13C30[0][A] counter_11_s0/CLK
1.059 0.030 tUnc counter_11_s0
1.059 0.000 tHld 1 R13C30[0][A] counter_11_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.844, 82.061%; route: 0.185, 17.939%
Arrival Data Path Delay cell: 0.372, 52.303%; route: 0.006, 0.830%; tC2Q: 0.333, 46.867%
Required Clock Path Delay cell: 0.844, 82.061%; route: 0.185, 17.939%

Path18

Path Summary:

Slack 0.711
Data Arrival Time 1.740
Data Required Time 1.029
From counter_17_s0
To counter_17_s0
Launch Clk XTAL:[R]
Latch Clk XTAL:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 XTAL
0.000 0.000 tCL RR 1 IOR17[A] XTAL_IN_ibuf/I
0.844 0.844 tINS RR 29 IOR17[A] XTAL_IN_ibuf/O
1.029 0.185 tNET RR 1 R14C32[1][A] counter_17_s0/CLK
1.362 0.333 tC2Q RR 6 R14C32[1][A] counter_17_s0/Q
1.368 0.006 tNET RR 1 R14C32[1][A] n77_s1/I2
1.740 0.372 tINS RF 1 R14C32[1][A] n77_s1/F
1.740 0.000 tNET FF 1 R14C32[1][A] counter_17_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 XTAL
0.000 0.000 tCL RR 1 IOR17[A] XTAL_IN_ibuf/I
0.844 0.844 tINS RR 29 IOR17[A] XTAL_IN_ibuf/O
1.029 0.185 tNET RR 1 R14C32[1][A] counter_17_s0/CLK
1.059 0.030 tUnc counter_17_s0
1.059 0.000 tHld 1 R14C32[1][A] counter_17_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.844, 82.061%; route: 0.185, 17.939%
Arrival Data Path Delay cell: 0.372, 52.303%; route: 0.006, 0.830%; tC2Q: 0.333, 46.867%
Required Clock Path Delay cell: 0.844, 82.061%; route: 0.185, 17.939%

Path19

Path Summary:

Slack 0.714
Data Arrival Time 0.898
Data Required Time 0.185
From D1/PixelCount_8_s0
To D1/PixelCount_8_s0
Launch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
0.000 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
0.185 0.185 tNET RR 1 R14C15[0][A] D1/PixelCount_8_s0/CLK
0.518 0.333 tC2Q RR 22 R14C15[0][A] D1/PixelCount_8_s0/Q
0.526 0.008 tNET RR 1 R14C15[0][A] D1/n90_s1/I3
0.898 0.372 tINS RF 1 R14C15[0][A] D1/n90_s1/F
0.898 0.000 tNET FF 1 R14C15[0][A] D1/PixelCount_8_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
0.000 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
0.185 0.185 tNET RR 1 R14C15[0][A] D1/PixelCount_8_s0/CLK
0.215 0.030 tUnc D1/PixelCount_8_s0
0.215 0.000 tHld 1 R14C15[0][A] D1/PixelCount_8_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay cell: 0.372, 52.130%; route: 0.008, 1.158%; tC2Q: 0.333, 46.712%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.185, 100.000%

Path20

Path Summary:

Slack 0.715
Data Arrival Time 0.899
Data Required Time 0.185
From D1/PixelCount_3_s0
To D1/PixelCount_3_s0
Launch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
0.000 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
0.185 0.185 tNET RR 1 R13C19[0][A] D1/PixelCount_3_s0/CLK
0.518 0.333 tC2Q RR 23 R13C19[0][A] D1/PixelCount_3_s0/Q
0.527 0.009 tNET RR 1 R13C19[0][A] D1/n95_s1/I1
0.899 0.372 tINS RF 1 R13C19[0][A] D1/n95_s1/F
0.899 0.000 tNET FF 1 R13C19[0][A] D1/PixelCount_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
0.000 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
0.185 0.185 tNET RR 1 R13C19[0][A] D1/PixelCount_3_s0/CLK
0.215 0.030 tUnc D1/PixelCount_3_s0
0.215 0.000 tHld 1 R13C19[0][A] D1/PixelCount_3_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay cell: 0.372, 52.044%; route: 0.009, 1.321%; tC2Q: 0.333, 46.635%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.185, 100.000%

Path21

Path Summary:

Slack 0.722
Data Arrival Time 0.906
Data Required Time 0.185
From D1/PixelCount_1_s0
To D1/PixelCount_1_s0
Launch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
0.000 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
0.185 0.185 tNET RR 1 R12C21[0][A] D1/PixelCount_1_s0/CLK
0.518 0.333 tC2Q RR 23 R12C21[0][A] D1/PixelCount_1_s0/Q
0.534 0.017 tNET RR 1 R12C21[0][A] D1/n97_s1/I2
0.906 0.372 tINS RF 1 R12C21[0][A] D1/n97_s1/F
0.906 0.000 tNET FF 1 R12C21[0][A] D1/PixelCount_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
0.000 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
0.185 0.185 tNET RR 1 R12C21[0][A] D1/PixelCount_1_s0/CLK
0.215 0.030 tUnc D1/PixelCount_1_s0
0.215 0.000 tHld 1 R12C21[0][A] D1/PixelCount_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay cell: 0.372, 51.533%; route: 0.017, 2.290%; tC2Q: 0.333, 46.177%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.185, 100.000%

Path22

Path Summary:

Slack 0.835
Data Arrival Time 1.864
Data Required Time 1.029
From LED_5_s2
To LED_0_s1
Launch Clk XTAL:[R]
Latch Clk XTAL:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 XTAL
0.000 0.000 tCL RR 1 IOR17[A] XTAL_IN_ibuf/I
0.844 0.844 tINS RR 29 IOR17[A] XTAL_IN_ibuf/O
1.029 0.185 tNET RR 1 R14C30[0][A] LED_5_s2/CLK
1.362 0.333 tC2Q RR 2 R14C30[0][A] LED_5_s2/Q
1.864 0.501 tNET RR 1 R14C29[2][B] LED_0_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 XTAL
0.000 0.000 tCL RR 1 IOR17[A] XTAL_IN_ibuf/I
0.844 0.844 tINS RR 29 IOR17[A] XTAL_IN_ibuf/O
1.029 0.185 tNET RR 1 R14C29[2][B] LED_0_s1/CLK
1.059 0.030 tUnc LED_0_s1
1.059 0.000 tHld 1 R14C29[2][B] LED_0_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.844, 82.061%; route: 0.185, 17.939%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.501, 60.063%; tC2Q: 0.333, 39.937%
Required Clock Path Delay cell: 0.844, 82.061%; route: 0.185, 17.939%

Path23

Path Summary:

Slack 0.835
Data Arrival Time 1.864
Data Required Time 1.029
From LED_3_s1
To LED_4_s1
Launch Clk XTAL:[R]
Latch Clk XTAL:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 XTAL
0.000 0.000 tCL RR 1 IOR17[A] XTAL_IN_ibuf/I
0.844 0.844 tINS RR 29 IOR17[A] XTAL_IN_ibuf/O
1.029 0.185 tNET RR 1 R14C29[0][A] LED_3_s1/CLK
1.362 0.333 tC2Q RR 2 R14C29[0][A] LED_3_s1/Q
1.864 0.501 tNET RR 1 R14C30[0][B] LED_4_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 XTAL
0.000 0.000 tCL RR 1 IOR17[A] XTAL_IN_ibuf/I
0.844 0.844 tINS RR 29 IOR17[A] XTAL_IN_ibuf/O
1.029 0.185 tNET RR 1 R14C30[0][B] LED_4_s1/CLK
1.059 0.030 tUnc LED_4_s1
1.059 0.000 tHld 1 R14C30[0][B] LED_4_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.844, 82.061%; route: 0.185, 17.939%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.501, 60.063%; tC2Q: 0.333, 39.937%
Required Clock Path Delay cell: 0.844, 82.061%; route: 0.185, 17.939%

Path24

Path Summary:

Slack 0.892
Data Arrival Time 1.921
Data Required Time 1.029
From counter_21_s0
To counter_21_s0
Launch Clk XTAL:[R]
Latch Clk XTAL:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 XTAL
0.000 0.000 tCL RR 1 IOR17[A] XTAL_IN_ibuf/I
0.844 0.844 tINS RR 29 IOR17[A] XTAL_IN_ibuf/O
1.029 0.185 tNET RR 1 R13C32[2][A] counter_21_s0/CLK
1.362 0.333 tC2Q RR 2 R13C32[2][A] counter_21_s0/Q
1.365 0.002 tNET RR 1 R13C32[2][A] n73_s1/I2
1.921 0.556 tINS RR 1 R13C32[2][A] n73_s1/F
1.921 0.000 tNET RR 1 R13C32[2][A] counter_21_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 XTAL
0.000 0.000 tCL RR 1 IOR17[A] XTAL_IN_ibuf/I
0.844 0.844 tINS RR 29 IOR17[A] XTAL_IN_ibuf/O
1.029 0.185 tNET RR 1 R13C32[2][A] counter_21_s0/CLK
1.059 0.030 tUnc counter_21_s0
1.059 0.000 tHld 1 R13C32[2][A] counter_21_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.844, 82.061%; route: 0.185, 17.939%
Arrival Data Path Delay cell: 0.556, 62.353%; route: 0.002, 0.265%; tC2Q: 0.333, 37.382%
Required Clock Path Delay cell: 0.844, 82.061%; route: 0.185, 17.939%

Path25

Path Summary:

Slack 0.893
Data Arrival Time 1.077
Data Required Time 0.185
From D1/LineCount_2_s1
To D1/LineCount_2_s1
Launch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]
Latch Clk chip_pll/rpll_inst/CLKOUTD.default_gen_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
0.000 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
0.185 0.185 tNET RR 1 R15C13[2][A] D1/LineCount_2_s1/CLK
0.518 0.333 tC2Q RR 6 R15C13[2][A] D1/LineCount_2_s1/Q
0.521 0.004 tNET RR 1 R15C13[2][A] D1/n64_s3/I0
1.077 0.556 tINS RR 1 R15C13[2][A] D1/n64_s3/F
1.077 0.000 tNET RR 1 R15C13[2][A] D1/LineCount_2_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
0.000 0.000 tCL RR 28 PLL_R chip_pll/rpll_inst/CLKOUTD
0.185 0.185 tNET RR 1 R15C13[2][A] D1/LineCount_2_s1/CLK
0.215 0.030 tUnc D1/LineCount_2_s1
0.215 0.000 tHld 1 R15C13[2][A] D1/LineCount_2_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.185, 100.000%
Arrival Data Path Delay cell: 0.556, 62.271%; route: 0.004, 0.397%; tC2Q: 0.333, 37.333%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.185, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

No recovery paths to report!

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

No removal paths to report!

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 14.104
Actual Width: 15.354
Required Width: 1.250
Type: Low Pulse Width
Clock: chip_pll/rpll_inst/CLKOUTD.default_gen_clk
Objects: D1/PixelCount_10_s0

Late clock Path:

AT DELAY TYPE RF NODE
15.432 0.000 active clock edge time
15.432 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
15.432 0.000 tCL FF chip_pll/rpll_inst/CLKOUTD
15.695 0.262 tNET FF D1/PixelCount_10_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
30.864 0.000 active clock edge time
30.864 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
30.864 0.000 tCL RR chip_pll/rpll_inst/CLKOUTD
31.049 0.185 tNET RR D1/PixelCount_10_s0/CLK

MPW2

MPW Summary:

Slack: 14.104
Actual Width: 15.354
Required Width: 1.250
Type: Low Pulse Width
Clock: chip_pll/rpll_inst/CLKOUTD.default_gen_clk
Objects: D1/PixelCount_9_s0

Late clock Path:

AT DELAY TYPE RF NODE
15.432 0.000 active clock edge time
15.432 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
15.432 0.000 tCL FF chip_pll/rpll_inst/CLKOUTD
15.695 0.262 tNET FF D1/PixelCount_9_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
30.864 0.000 active clock edge time
30.864 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
30.864 0.000 tCL RR chip_pll/rpll_inst/CLKOUTD
31.049 0.185 tNET RR D1/PixelCount_9_s0/CLK

MPW3

MPW Summary:

Slack: 14.104
Actual Width: 15.354
Required Width: 1.250
Type: Low Pulse Width
Clock: chip_pll/rpll_inst/CLKOUTD.default_gen_clk
Objects: D1/PixelCount_8_s0

Late clock Path:

AT DELAY TYPE RF NODE
15.432 0.000 active clock edge time
15.432 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
15.432 0.000 tCL FF chip_pll/rpll_inst/CLKOUTD
15.695 0.262 tNET FF D1/PixelCount_8_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
30.864 0.000 active clock edge time
30.864 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
30.864 0.000 tCL RR chip_pll/rpll_inst/CLKOUTD
31.049 0.185 tNET RR D1/PixelCount_8_s0/CLK

MPW4

MPW Summary:

Slack: 14.104
Actual Width: 15.354
Required Width: 1.250
Type: Low Pulse Width
Clock: chip_pll/rpll_inst/CLKOUTD.default_gen_clk
Objects: D1/LineCount_6_s1

Late clock Path:

AT DELAY TYPE RF NODE
15.432 0.000 active clock edge time
15.432 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
15.432 0.000 tCL FF chip_pll/rpll_inst/CLKOUTD
15.695 0.262 tNET FF D1/LineCount_6_s1/CLK

Early clock Path:

AT DELAY TYPE RF NODE
30.864 0.000 active clock edge time
30.864 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
30.864 0.000 tCL RR chip_pll/rpll_inst/CLKOUTD
31.049 0.185 tNET RR D1/LineCount_6_s1/CLK

MPW5

MPW Summary:

Slack: 14.104
Actual Width: 15.354
Required Width: 1.250
Type: Low Pulse Width
Clock: chip_pll/rpll_inst/CLKOUTD.default_gen_clk
Objects: D1/LineCount_2_s1

Late clock Path:

AT DELAY TYPE RF NODE
15.432 0.000 active clock edge time
15.432 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
15.432 0.000 tCL FF chip_pll/rpll_inst/CLKOUTD
15.695 0.262 tNET FF D1/LineCount_2_s1/CLK

Early clock Path:

AT DELAY TYPE RF NODE
30.864 0.000 active clock edge time
30.864 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
30.864 0.000 tCL RR chip_pll/rpll_inst/CLKOUTD
31.049 0.185 tNET RR D1/LineCount_2_s1/CLK

MPW6

MPW Summary:

Slack: 14.104
Actual Width: 15.354
Required Width: 1.250
Type: Low Pulse Width
Clock: chip_pll/rpll_inst/CLKOUTD.default_gen_clk
Objects: D1/LineCount_0_s1

Late clock Path:

AT DELAY TYPE RF NODE
15.432 0.000 active clock edge time
15.432 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
15.432 0.000 tCL FF chip_pll/rpll_inst/CLKOUTD
15.695 0.262 tNET FF D1/LineCount_0_s1/CLK

Early clock Path:

AT DELAY TYPE RF NODE
30.864 0.000 active clock edge time
30.864 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
30.864 0.000 tCL RR chip_pll/rpll_inst/CLKOUTD
31.049 0.185 tNET RR D1/LineCount_0_s1/CLK

MPW7

MPW Summary:

Slack: 14.104
Actual Width: 15.354
Required Width: 1.250
Type: Low Pulse Width
Clock: chip_pll/rpll_inst/CLKOUTD.default_gen_clk
Objects: D1/LineCount_15_s1

Late clock Path:

AT DELAY TYPE RF NODE
15.432 0.000 active clock edge time
15.432 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
15.432 0.000 tCL FF chip_pll/rpll_inst/CLKOUTD
15.695 0.262 tNET FF D1/LineCount_15_s1/CLK

Early clock Path:

AT DELAY TYPE RF NODE
30.864 0.000 active clock edge time
30.864 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
30.864 0.000 tCL RR chip_pll/rpll_inst/CLKOUTD
31.049 0.185 tNET RR D1/LineCount_15_s1/CLK

MPW8

MPW Summary:

Slack: 14.104
Actual Width: 15.354
Required Width: 1.250
Type: Low Pulse Width
Clock: chip_pll/rpll_inst/CLKOUTD.default_gen_clk
Objects: D1/LineCount_1_s1

Late clock Path:

AT DELAY TYPE RF NODE
15.432 0.000 active clock edge time
15.432 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
15.432 0.000 tCL FF chip_pll/rpll_inst/CLKOUTD
15.695 0.262 tNET FF D1/LineCount_1_s1/CLK

Early clock Path:

AT DELAY TYPE RF NODE
30.864 0.000 active clock edge time
30.864 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
30.864 0.000 tCL RR chip_pll/rpll_inst/CLKOUTD
31.049 0.185 tNET RR D1/LineCount_1_s1/CLK

MPW9

MPW Summary:

Slack: 14.104
Actual Width: 15.354
Required Width: 1.250
Type: Low Pulse Width
Clock: chip_pll/rpll_inst/CLKOUTD.default_gen_clk
Objects: D1/LineCount_5_s1

Late clock Path:

AT DELAY TYPE RF NODE
15.432 0.000 active clock edge time
15.432 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
15.432 0.000 tCL FF chip_pll/rpll_inst/CLKOUTD
15.695 0.262 tNET FF D1/LineCount_5_s1/CLK

Early clock Path:

AT DELAY TYPE RF NODE
30.864 0.000 active clock edge time
30.864 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
30.864 0.000 tCL RR chip_pll/rpll_inst/CLKOUTD
31.049 0.185 tNET RR D1/LineCount_5_s1/CLK

MPW10

MPW Summary:

Slack: 14.104
Actual Width: 15.354
Required Width: 1.250
Type: Low Pulse Width
Clock: chip_pll/rpll_inst/CLKOUTD.default_gen_clk
Objects: D1/LineCount_4_s1

Late clock Path:

AT DELAY TYPE RF NODE
15.432 0.000 active clock edge time
15.432 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
15.432 0.000 tCL FF chip_pll/rpll_inst/CLKOUTD
15.695 0.262 tNET FF D1/LineCount_4_s1/CLK

Early clock Path:

AT DELAY TYPE RF NODE
30.864 0.000 active clock edge time
30.864 0.000 chip_pll/rpll_inst/CLKOUTD.default_gen_clk
30.864 0.000 tCL RR chip_pll/rpll_inst/CLKOUTD
31.049 0.185 tNET RR D1/LineCount_4_s1/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
29 XTAL_IN_d 28.868 0.262
28 LCD_CLK_d 21.662 0.661
27 LineCount_14_8 21.662 1.678
25 PixelCount_0[6] 23.224 1.516
24 PixelCount_0[7] 22.619 2.956
23 PixelCount_0[0] 21.899 1.998
23 PixelCount_0[1] 21.662 2.001
23 PixelCount_0[3] 22.836 2.137
23 PixelCount_0[4] 21.986 2.004
23 PixelCount_0[5] 22.952 2.315

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R19C23 48.61%
R15C20 47.22%
R14C15 45.83%
R13C18 45.83%
R13C19 45.83%
R19C20 43.06%
R19C29 43.06%
R19C5 43.06%
R19C14 43.06%
R19C32 41.67%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command
TC_CLOCK Actived create_clock -name XTAL -period 37.037 -waveform {0 18.518} [get_ports {XTAL_IN}] -add
TC_CLOCK Actived create_clock -name LCD_CLK -period 30.03 -waveform {0 15.015} [get_ports {LCD_CLK}] -add