Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | E:\FPGA\Tang_nano_9K_LCD\src\TOP.v E:\FPGA\Tang_nano_9K_LCD\src\VGAMod.v E:\FPGA\Tang_nano_9K_LCD\src\gowin_osc\gowin_osc.v E:\FPGA\Tang_nano_9K_LCD\src\gowin_rpll\gowin_rpll.v |
| GowinSynthesis Constraints File | --- |
| GowinSynthesis Verision | GowinSynthesis V1.9.6.02Beta |
| Created Time | Mon Jan 10 14:33:46 2022 |
| Legal Announcement | Copyright (C)2014-2020 Gowin Semiconductor Corporation. ALL rights reserved. |
Design Settings
| Top Level Module: | TOP |
| Part Number: | GW1NR-LV9QN88PC6/I5 |
Resource
Resource Usage Summary
| I/OPORT Usage: | 29 |
| I/OBUF Usage: | 28 |
| IBUF | 2 |
| OBUF | 26 |
| REG Usage: | 55 |
| DFFPE | 5 |
| DFFC | 33 |
| DFFCE | 17 |
| LUT Usage: | 207 |
| LUT2 | 21 |
| LUT3 | 40 |
| LUT4 | 146 |
| ALU Usage: | 186 |
| ALU | 186 |
| INV Usage: | 1 |
| INV | 1 |
| DSP Usage: | 17 |
| MULT9X9 | 1 |
| MULT18X18 | 16 |
| CLOCK Usage: | 1 |
| rPLL | 1 |
Resource Utilization Summary
Target Device: GW1NR-9C-QFN88P| CFU Logics | 394(208 LUTs, 186 ALUs) / 8640 | 5% |
| Registers | 55 / 6771 | 1% |
| BSRAMs | 0 / 26 | 0% |
| DSP Macros | 9 / (5*2) | 90% |
Timing
Clock Summary:
| Clock | Type | Frequency | Period | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| XTAL_IN.default_clk | Base | 27.0 MHz | 37.037 | 0.000 | 18.519 | XTAL_IN_ibuf/I | ||
| chip_pll/rpll_inst/CLKOUT.default_gen_clk | Generated | 129.6 MHz | 7.716 | 0.000 | 3.858 | XTAL_IN_ibuf/I | XTAL_IN.default_clk | chip_pll/rpll_inst/CLKOUT |
| chip_pll/rpll_inst/CLKOUTP.default_gen_clk | Generated | 129.6 MHz | 7.716 | 0.000 | 3.858 | XTAL_IN_ibuf/I | XTAL_IN.default_clk | chip_pll/rpll_inst/CLKOUTP |
| chip_pll/rpll_inst/CLKOUTD.default_gen_clk | Generated | 32.4 MHz | 30.864 | 0.000 | 15.432 | XTAL_IN_ibuf/I | XTAL_IN.default_clk | chip_pll/rpll_inst/CLKOUTD |
| chip_pll/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 43.2 MHz | 23.148 | 0.000 | 11.574 | XTAL_IN_ibuf/I | XTAL_IN.default_clk | chip_pll/rpll_inst/CLKOUTD3 |
Timing Report:
| Top View: | TOP |
| Requested Frequency: | 27.0 MHz |
| Paths Requested: | 5 |
| Constraint File(ignored): |
Performance Summary:
Worst Slack in Design: 29.482| Start Clock | Slack | Requested Frequency | Estimated Frequency | Requested Period | Estimated Period | Clock Type |
|---|---|---|---|---|---|---|
| XTAL_IN.default_clk | 29.482 | 27.0 MHz | 132.4 MHz | 37.037 | 7.555 | Base |
| chip_pll/rpll_inst/CLKOUTD.default_gen_clk | 23.452 | 32.4 MHz | 134.9 MHz | 30.864 | 7.412 | Generated |
Detail Timing Paths Information
Path information for path number 1 :| Clock Skew: | 0.000 |
| Setup Relationship: | 30.864 |
| Slack(critical): | 23.452 |
| Data Arrival Time: | 7.340 |
| Data Required Time: | 30.792 |
| Number of Logic Level: | 5 |
| Starting Point: | chip_pll/rpll_inst |
| Ending Point: | D1/PixelCount_0_s0 |
| The Start Point Is Clocked By: | chip_pll/rpll_inst/CLKOUTD.default_gen_clk[rising] |
| The End Point Is Clocked By: | chip_pll/rpll_inst/CLKOUTD.default_gen_clk[rising] |
| Instance/Net Name | Type | Pin Name | Pin Dir | Delay | Arrival Time | Fanout |
|---|---|---|---|---|---|---|
| \chip_pll/rpll_inst | rPLL | CLKOUTD | Out | 0.000 | 0.000 | - |
| LCD_CLK_d | Net | - | - | 0.363 | - | 28 |
| \D1/LineCount_5_s1 | DFFCE | CLK | In | - | 0.363 | - |
| \D1/LineCount_5_s1 | DFFCE | Q | Out | 0.458 | 0.821 | - |
| LineCount[5] | Net | - | - | 0.480 | - | 4 |
| \D1/LineCount_14_s9 | LUT4 | I1 | In | - | 1.301 | - |
| \D1/LineCount_14_s9 | LUT4 | F | Out | 1.099 | 2.400 | - |
| LineCount_14 | Net | - | - | 0.480 | - | 2 |
| \D1/LineCount_14_s5 | LUT3 | I2 | In | - | 2.880 | - |
| \D1/LineCount_14_s5 | LUT3 | F | Out | 0.822 | 3.702 | - |
| LineCount_14 | Net | - | - | 0.480 | - | 1 |
| \D1/LineCount_14_s3 | LUT4 | I1 | In | - | 4.182 | - |
| \D1/LineCount_14_s3 | LUT4 | F | Out | 1.099 | 5.281 | - |
| LineCount_14 | Net | - | - | 0.480 | - | 27 |
| \D1/n98_s1 | LUT2 | I1 | In | - | 5.761 | - |
| \D1/n98_s1 | LUT2 | F | Out | 1.099 | 6.860 | - |
| n98_5 | Net | - | - | 0.480 | - | 1 |
| \D1/PixelCount_0_s0 | DFFC | D | In | - | 7.340 | - |
Total Path Delay: 7.340
Logic Delay: 4.577(62.4%)
Route Delay: 2.763(37.6%)
Path information for path number 2 :
| Clock Skew: | 0.000 |
| Setup Relationship: | 30.864 |
| Slack(non-critical): | 23.519 |
| Data Arrival Time: | 7.273 |
| Data Required Time: | 30.792 |
| Number of Logic Level: | 5 |
| Starting Point: | chip_pll/rpll_inst |
| Ending Point: | D1/PixelCount_4_s0 |
| The Start Point Is Clocked By: | chip_pll/rpll_inst/CLKOUTD.default_gen_clk[rising] |
| The End Point Is Clocked By: | chip_pll/rpll_inst/CLKOUTD.default_gen_clk[rising] |
| Instance/Net Name | Type | Pin Name | Pin Dir | Delay | Arrival Time | Fanout |
|---|---|---|---|---|---|---|
| \chip_pll/rpll_inst | rPLL | CLKOUTD | Out | 0.000 | 0.000 | - |
| LCD_CLK_d | Net | - | - | 0.363 | - | 28 |
| \D1/LineCount_5_s1 | DFFCE | CLK | In | - | 0.363 | - |
| \D1/LineCount_5_s1 | DFFCE | Q | Out | 0.458 | 0.821 | - |
| LineCount[5] | Net | - | - | 0.480 | - | 4 |
| \D1/LineCount_14_s9 | LUT4 | I1 | In | - | 1.301 | - |
| \D1/LineCount_14_s9 | LUT4 | F | Out | 1.099 | 2.400 | - |
| LineCount_14 | Net | - | - | 0.480 | - | 2 |
| \D1/LineCount_14_s5 | LUT3 | I2 | In | - | 2.880 | - |
| \D1/LineCount_14_s5 | LUT3 | F | Out | 0.822 | 3.702 | - |
| LineCount_14 | Net | - | - | 0.480 | - | 1 |
| \D1/LineCount_14_s3 | LUT4 | I1 | In | - | 4.182 | - |
| \D1/LineCount_14_s3 | LUT4 | F | Out | 1.099 | 5.281 | - |
| LineCount_14 | Net | - | - | 0.480 | - | 27 |
| \D1/n94_s1 | LUT3 | I0 | In | - | 5.761 | - |
| \D1/n94_s1 | LUT3 | F | Out | 1.032 | 6.793 | - |
| n94_5 | Net | - | - | 0.480 | - | 1 |
| \D1/PixelCount_4_s0 | DFFC | D | In | - | 7.273 | - |
Total Path Delay: 7.273
Logic Delay: 4.510(62.0%)
Route Delay: 2.763(38.0%)
Path information for path number 3 :
| Clock Skew: | 0.000 |
| Setup Relationship: | 30.864 |
| Slack(non-critical): | 23.519 |
| Data Arrival Time: | 7.273 |
| Data Required Time: | 30.792 |
| Number of Logic Level: | 5 |
| Starting Point: | chip_pll/rpll_inst |
| Ending Point: | D1/PixelCount_1_s0 |
| The Start Point Is Clocked By: | chip_pll/rpll_inst/CLKOUTD.default_gen_clk[rising] |
| The End Point Is Clocked By: | chip_pll/rpll_inst/CLKOUTD.default_gen_clk[rising] |
| Instance/Net Name | Type | Pin Name | Pin Dir | Delay | Arrival Time | Fanout |
|---|---|---|---|---|---|---|
| \chip_pll/rpll_inst | rPLL | CLKOUTD | Out | 0.000 | 0.000 | - |
| LCD_CLK_d | Net | - | - | 0.363 | - | 28 |
| \D1/LineCount_5_s1 | DFFCE | CLK | In | - | 0.363 | - |
| \D1/LineCount_5_s1 | DFFCE | Q | Out | 0.458 | 0.821 | - |
| LineCount[5] | Net | - | - | 0.480 | - | 4 |
| \D1/LineCount_14_s9 | LUT4 | I1 | In | - | 1.301 | - |
| \D1/LineCount_14_s9 | LUT4 | F | Out | 1.099 | 2.400 | - |
| LineCount_14 | Net | - | - | 0.480 | - | 2 |
| \D1/LineCount_14_s5 | LUT3 | I2 | In | - | 2.880 | - |
| \D1/LineCount_14_s5 | LUT3 | F | Out | 0.822 | 3.702 | - |
| LineCount_14 | Net | - | - | 0.480 | - | 1 |
| \D1/LineCount_14_s3 | LUT4 | I1 | In | - | 4.182 | - |
| \D1/LineCount_14_s3 | LUT4 | F | Out | 1.099 | 5.281 | - |
| LineCount_14 | Net | - | - | 0.480 | - | 27 |
| \D1/n97_s1 | LUT3 | I0 | In | - | 5.761 | - |
| \D1/n97_s1 | LUT3 | F | Out | 1.032 | 6.793 | - |
| n97_5 | Net | - | - | 0.480 | - | 1 |
| \D1/PixelCount_1_s0 | DFFC | D | In | - | 7.273 | - |
Total Path Delay: 7.273
Logic Delay: 4.510(62.0%)
Route Delay: 2.763(38.0%)
Path information for path number 4 :
| Clock Skew: | 0.000 |
| Setup Relationship: | 30.864 |
| Slack(non-critical): | 23.519 |
| Data Arrival Time: | 7.273 |
| Data Required Time: | 30.792 |
| Number of Logic Level: | 5 |
| Starting Point: | chip_pll/rpll_inst |
| Ending Point: | D1/PixelCount_3_s0 |
| The Start Point Is Clocked By: | chip_pll/rpll_inst/CLKOUTD.default_gen_clk[rising] |
| The End Point Is Clocked By: | chip_pll/rpll_inst/CLKOUTD.default_gen_clk[rising] |
| Instance/Net Name | Type | Pin Name | Pin Dir | Delay | Arrival Time | Fanout |
|---|---|---|---|---|---|---|
| \chip_pll/rpll_inst | rPLL | CLKOUTD | Out | 0.000 | 0.000 | - |
| LCD_CLK_d | Net | - | - | 0.363 | - | 28 |
| \D1/LineCount_5_s1 | DFFCE | CLK | In | - | 0.363 | - |
| \D1/LineCount_5_s1 | DFFCE | Q | Out | 0.458 | 0.821 | - |
| LineCount[5] | Net | - | - | 0.480 | - | 4 |
| \D1/LineCount_14_s9 | LUT4 | I1 | In | - | 1.301 | - |
| \D1/LineCount_14_s9 | LUT4 | F | Out | 1.099 | 2.400 | - |
| LineCount_14 | Net | - | - | 0.480 | - | 2 |
| \D1/LineCount_14_s5 | LUT3 | I2 | In | - | 2.880 | - |
| \D1/LineCount_14_s5 | LUT3 | F | Out | 0.822 | 3.702 | - |
| LineCount_14 | Net | - | - | 0.480 | - | 1 |
| \D1/LineCount_14_s3 | LUT4 | I1 | In | - | 4.182 | - |
| \D1/LineCount_14_s3 | LUT4 | F | Out | 1.099 | 5.281 | - |
| LineCount_14 | Net | - | - | 0.480 | - | 27 |
| \D1/n95_s1 | LUT3 | I0 | In | - | 5.761 | - |
| \D1/n95_s1 | LUT3 | F | Out | 1.032 | 6.793 | - |
| n95_5 | Net | - | - | 0.480 | - | 1 |
| \D1/PixelCount_3_s0 | DFFC | D | In | - | 7.273 | - |
Total Path Delay: 7.273
Logic Delay: 4.510(62.0%)
Route Delay: 2.763(38.0%)
Path information for path number 5 :
| Clock Skew: | 0.000 |
| Setup Relationship: | 30.864 |
| Slack(non-critical): | 23.519 |
| Data Arrival Time: | 7.273 |
| Data Required Time: | 30.792 |
| Number of Logic Level: | 5 |
| Starting Point: | chip_pll/rpll_inst |
| Ending Point: | D1/PixelCount_6_s0 |
| The Start Point Is Clocked By: | chip_pll/rpll_inst/CLKOUTD.default_gen_clk[rising] |
| The End Point Is Clocked By: | chip_pll/rpll_inst/CLKOUTD.default_gen_clk[rising] |
| Instance/Net Name | Type | Pin Name | Pin Dir | Delay | Arrival Time | Fanout |
|---|---|---|---|---|---|---|
| \chip_pll/rpll_inst | rPLL | CLKOUTD | Out | 0.000 | 0.000 | - |
| LCD_CLK_d | Net | - | - | 0.363 | - | 28 |
| \D1/LineCount_5_s1 | DFFCE | CLK | In | - | 0.363 | - |
| \D1/LineCount_5_s1 | DFFCE | Q | Out | 0.458 | 0.821 | - |
| LineCount[5] | Net | - | - | 0.480 | - | 4 |
| \D1/LineCount_14_s9 | LUT4 | I1 | In | - | 1.301 | - |
| \D1/LineCount_14_s9 | LUT4 | F | Out | 1.099 | 2.400 | - |
| LineCount_14 | Net | - | - | 0.480 | - | 2 |
| \D1/LineCount_14_s5 | LUT3 | I2 | In | - | 2.880 | - |
| \D1/LineCount_14_s5 | LUT3 | F | Out | 0.822 | 3.702 | - |
| LineCount_14 | Net | - | - | 0.480 | - | 1 |
| \D1/LineCount_14_s3 | LUT4 | I1 | In | - | 4.182 | - |
| \D1/LineCount_14_s3 | LUT4 | F | Out | 1.099 | 5.281 | - |
| LineCount_14 | Net | - | - | 0.480 | - | 27 |
| \D1/n92_s1 | LUT3 | I0 | In | - | 5.761 | - |
| \D1/n92_s1 | LUT3 | F | Out | 1.032 | 6.793 | - |
| n92_5 | Net | - | - | 0.480 | - | 1 |
| \D1/PixelCount_6_s0 | DFFC | D | In | - | 7.273 | - |
Total Path Delay: 7.273
Logic Delay: 4.510(62.0%)
Route Delay: 2.763(38.0%)
Summary
| Total Warnings: | 1 |
| Total Informations: | 25 |
Synthesis completed successfully!
Process took 0h:0m:2s realtime, 0h:0m:2s cputime
Memory peak: 59.8MB