Report Title |
Gowin Power Analysis Report |
Design File |
E:\FPGA\Tang_nano_9K_LCD\impl\gwsynthesis\Tang_nano_9K_LCD.vg |
Physical Constraints File |
E:\FPGA\Tang_nano_9K_LCD\src\Tang_nano_9K_LCD.cst |
Timing Constraints File |
E:\FPGA\Tang_nano_9K_LCD\src\Tang_nano_9K_LCD.sdc |
GOWIN Version |
V1.9.6.02Beta |
Part Number |
GW1NR-LV9QN88PC6/I5 |
Created Time |
Mon Jan 10 14:33:50 2022
|
Legal Announcement |
Copyright (C)2014-2020 Gowin Semiconductor Corporation. All rights reserved. |
Total Power (mW) |
13.168 |
Quiescent Power (mW) |
4.507 |
Dynamic Power (mW) |
8.662 |
Psram Power (mW) |
86.000 |
Junction Temperature |
25.135 |
Theta JA |
10.500 |
Max Allowed Ambient Temperature |
84.862 |
Default IO Toggle Rate |
0.125 |
Default Remain Toggle Rate |
0.125 |
Use Vectorless Estimation |
false |
Filter Glitches |
false |
Related Vcd File |
|
Related Saif File |
|
Use Custom Theta JA |
false |
Air Flow |
LFM_0 |
Heat Sink |
None |
Use Custom Theta SA |
false |
Board Thermal Model |
None |
Use Custom Theta JB |
false |
Ambient Temperature |
25.000
|
Voltage Source |
Voltage |
Dynamic Current(mA) |
Quiescent Current(mA) |
Power(mW) |
VCC |
1.200 |
6.304 |
2.464 |
10.522 |
VCCX |
2.500 |
0.195 |
0.284 |
1.198 |
VCCO18 |
1.800 |
0.024 |
0.064 |
0.158 |
VCCO33 |
3.300 |
0.171 |
0.219 |
1.290 |
Block Type |
Total Power(mW) |
Static Power(mW) |
Average Toggle Rate(millions of transitions/sec) |
Logic |
0.825 |
NA |
3.923 |
IO |
3.221
| 1.890
| 4.725
|
PLL |
3.014
| NA |
NA |
Hierarchy Entity |
Total Power(mW) |
Block Dynamic Power(mW) |
Routing Dynamic Power(mW) |
TOP |
7.328 |
3.838(3.718) |
3.490(2.830) |
TOP/D1/ |
3.514 |
0.704(0.000) |
2.810(0.000) |
TOP/chip_pll/ |
3.033 |
3.014(0.000) |
0.019(0.000) |
Clock Domain |
Clock Frequency(Mhz) |
Total Dynamic Power(mW) |
chip_pll/rpll_inst/CLKOUTD.default_gen_clk |
32.400 |
3.988 |
XTAL |
27.000 |
3.342 |
NO CLOCK DOMAIN |
0.000 |
0.000 |