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15 lines
692 B
15 lines
692 B
<?xml version="1" encoding="UTF-8"?> |
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<!DOCTYPE gowin-fpga-project> |
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<Project> |
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<Template>FPGA</Template> |
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<Version>5</Version> |
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<Device name="GW2AR-18C" pn="GW2AR-LV18QN88C8/I7">gw2ar18c-000</Device> |
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<FileList> |
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<File path="src/audio_drive.v" type="file.verilog" enable="1"/> |
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<File path="src/gowin_clkdiv/gowin_clkdiv.v" type="file.verilog" enable="1"/> |
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<File path="src/gowin_rpll/gowin_rpll.v" type="file.verilog" enable="1"/> |
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<File path="src/rom_wave_sine.v" type="file.verilog" enable="1"/> |
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<File path="src/top.v" type="file.verilog" enable="1"/> |
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<File path="src/audio.cst" type="file.cst" enable="1"/> |
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</FileList> |
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</Project>
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