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TangNano-20K-example
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update tang_nano_20k led examples

pull/1/head
wonderfullook 2 years ago
parent
d7827efb83
commit
93a129789d
20 changed files with 3190 additions and 22 deletions
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  1. 1
      .gitignore
  2. 8
      audio/src/top.v
  3. 1378
      led/blink_led/blink_led.fs
  4. 12
      led/blink_led/blink_led.gprj
  5. 86
      led/blink_led/impl/project_process_config.json
  6. 6
      led/blink_led/src/blink_led.cst
  7. 2
      led/blink_led/src/blink_led.sdc
  8. 30
      led/blink_led/src/blink_led.v
  9. 1378
      led/blink_leds/blink_leds.fs
  10. 12
      led/blink_leds/blink_leds.gprj
  11. 86
      led/blink_leds/impl/project_process_config.json
  12. 15
      led/blink_leds/src/blink_leds.cst
  13. 2
      led/blink_leds/src/blink_leds.sdc
  14. 34
      led/blink_leds/src/blink_leds.v
  15. 12
      led/flow_led/flow_led.gprj
  16. 86
      led/flow_led/impl/project_process_config.json
  17. 15
      led/flow_led/src/flow_led.cst
  18. 2
      led/flow_led/src/flow_led.sdc
  19. 34
      led/flow_led/src/flow_led.v
  20. 13
      rgb_lcd/lcd_800_400/color_bar/Tang_nano_20K_LCD.gprj.user

1
.gitignore vendored
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@ -1 +0,0 @@ @@ -1 +0,0 @@
/test

8
audio/src/top.v
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@ -15,7 +15,6 @@ module top( @@ -15,7 +15,6 @@ module top(
output reg led
);
wire clk_6m_w;//6MHz,为产生1.5MHz
wire clk_1p5m_w;//1.536MHz近似时钟
@ -26,7 +25,6 @@ reg [9:0] addr_r;//rom地址 @@ -26,7 +25,6 @@ reg [9:0] addr_r;//rom地址
assign PA_EN = 1'b1;//PA常开
always@(posedge clk_1p5m_w or negedge rst_n)
if(!rst_n)
addr_r <= 10'd0;
@ -47,7 +45,6 @@ Gowin_CLKDIV clk_div4( @@ -47,7 +45,6 @@ Gowin_CLKDIV clk_div4(
.resetn(rst_n) //input resetn
);
rom_save_sin rom_save_sin_inst(
.clk(clk),
.rst_n(rst_n),
@ -68,9 +65,6 @@ audio_drive u_audio_drive_0( @@ -68,9 +65,6 @@ audio_drive u_audio_drive_0(
.HP_DIN (HP_DIN)//dac串行数据输入信号
);
reg [23:0] counter; //定义一个变量来计数
always @(posedge clk or negedge rst_n) begin // Counter block
@ -89,6 +83,4 @@ always @(posedge clk or negedge rst_n) begin // Toggle LED @@ -89,6 +83,4 @@ always @(posedge clk or negedge rst_n) begin // Toggle LED
led <= ~led; // ToggleLED
end
endmodule

1378
led/blink_led/blink_led.fs
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12
led/blink_led/blink_led.gprj
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@ -0,0 +1,12 @@ @@ -0,0 +1,12 @@
<?xml version="1" encoding="UTF-8"?>
<!DOCTYPE gowin-fpga-project>
<Project>
<Template>FPGA</Template>
<Version>5</Version>
<Device name="GW2AR-18C" pn="GW2AR-LV18QN88C8/I7">gw2ar18c-000</Device>
<FileList>
<File path="src/blink_led.v" type="file.verilog" enable="1"/>
<File path="src/blink_led.cst" type="file.cst" enable="1"/>
<File path="src/blink_led.sdc" type="file.sdc" enable="1"/>
</FileList>
</Project>

86
led/blink_led/impl/project_process_config.json
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@ -0,0 +1,86 @@ @@ -0,0 +1,86 @@
{
"Allow_Duplicate_Modules" : false,
"Annotated_Properties_for_Analyst" : true,
"BACKGROUND_PROGRAMMING" : "off",
"COMPRESS" : false,
"CRC_CHECK" : true,
"Clock_Conversion" : true,
"Clock_Route_Order" : 0,
"Correct_Hold_Violation" : true,
"DONE" : false,
"DOWNLOAD_SPEED" : "default",
"Default_Enum_Encoding" : "default",
"Disable_Insert_Pad" : false,
"ENCRYPTION_KEY" : false,
"ENCRYPTION_KEY_TEXT" : "00000000000000000000000000000000",
"FORMAT" : "binary",
"FSM Compiler" : true,
"Fanout_Guide" : 10000,
"Frequency" : "Auto",
"Generate_Constraint_File_of_Ports" : false,
"Generate_IBIS_File" : false,
"Generate_Plain_Text_Timing_Report" : false,
"Generate_Post_PNR_Simulation_Model_File" : false,
"Generate_Post_Place_File" : false,
"Generate_SDF_File" : false,
"Generate_VHDL_Post_PNR_Simulation_Model_File" : false,
"GwSyn_Loop_Limit" : 2000,
"HOTBOOT" : false,
"I2C" : false,
"I2C_SLAVE_ADDR" : "00",
"Implicit_Initial_Value_Support" : false,
"IncludePath" : [
],
"Incremental_Compile" : "",
"Initialize_Primitives" : false,
"JTAG" : false,
"MODE_IO" : false,
"MSPI" : false,
"Multiple_File_Compilation_Unit" : true,
"Number_of_Critical_Paths" : "",
"Number_of_Start/End_Points" : "",
"OUTPUT_BASE_NAME" : "blink_led",
"POWER_ON_RESET_MONITOR" : true,
"PRINT_BSRAM_VALUE" : true,
"PROGRAM_DONE_BYPASS" : false,
"Pipelining" : true,
"PlaceInRegToIob" : true,
"PlaceIoRegToIob" : true,
"PlaceOutRegToIob" : true,
"Place_Option" : "0",
"Process_Configuration_Verion" : "1.0",
"Promote_Physical_Constraint_Warning_to_Error" : true,
"Push_Tristates" : true,
"READY" : false,
"RECONFIG_N" : false,
"Ram_RW_Check" : true,
"Report_Auto-Placed_Io_Information" : false,
"Resolve_Mixed_Drivers" : false,
"Resource_Sharing" : true,
"Retiming" : false,
"Route_Maxfan" : "23",
"Route_Option" : "0",
"Run_Timing_Driven" : true,
"SECURE_MODE" : false,
"SECURITY_BIT" : true,
"SPI_FLASH_ADDR" : "00000000",
"SSPI" : false,
"Show_All_Warnings" : false,
"Synthesis On/Off Implemented as Translate On/Off" : false,
"Synthesize_tool" : "GowinSyn",
"TclPre" : "",
"TopModule" : "",
"USERCODE" : "default",
"Unused_Pin" : "As_input_tri_stated_with_pull_up",
"Update_Compile_Point_Timing_Data" : false,
"Use_Clock_Period_for_Unconstrainted IO" : false,
"VCCAUX" : "3.3",
"VHDL_Standard" : "VHDL_Std_1993",
"Verilog_Standard" : "Vlg_Std_2001",
"WAKE_UP" : "0",
"Write_Vendor_Constraint_File" : true,
"dsp_balance" : false,
"show_all_warnings" : false,
"turn_off_bg" : false
}

6
led/blink_led/src/blink_led.cst
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@ -0,0 +1,6 @@ @@ -0,0 +1,6 @@
IO_LOC "led" 15;
IO_PORT "led" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "clk" 4;
IO_PORT "clk" PULL_MODE=UP BANK_VCCIO=1.8;

2
led/blink_led/src/blink_led.sdc
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@ -0,0 +1,2 @@ @@ -0,0 +1,2 @@
create_clock -name clk_27M -period 37.037 -waveform {0 18.518} [get_ports {clk}]

30
led/blink_led/src/blink_led.v
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@ -0,0 +1,30 @@ @@ -0,0 +1,30 @@
module top(
input clk,
output led
);
reg count_1s_flag;
reg [23:0] count_1s = 'd0;
always @(posedge clk ) begin
if( count_1s < 27000000/2 ) begin
count_1s <= count_1s + 'd1;
count_1s_flag <= 'd0;
end
else begin
count_1s <= 'd0;
count_1s_flag <= 'd1;
end
end
reg led_value = 'd1;
always @(posedge clk ) begin
if( count_1s_flag ) begin
led_value <= ~led_value;
end
end
assign led = led_value;
endmodule

1378
led/blink_leds/blink_leds.fs
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12
led/blink_leds/blink_leds.gprj
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@ -0,0 +1,12 @@ @@ -0,0 +1,12 @@
<?xml version="1" encoding="UTF-8"?>
<!DOCTYPE gowin-fpga-project>
<Project>
<Template>FPGA</Template>
<Version>5</Version>
<Device name="GW2AR-18C" pn="GW2AR-LV18QN88C8/I7">gw2ar18c-000</Device>
<FileList>
<File path="src/blink_leds.v" type="file.verilog" enable="1"/>
<File path="src/blink_leds.cst" type="file.cst" enable="1"/>
<File path="src/blink_leds.sdc" type="file.sdc" enable="1"/>
</FileList>
</Project>

86
led/blink_leds/impl/project_process_config.json
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@ -0,0 +1,86 @@ @@ -0,0 +1,86 @@
{
"Allow_Duplicate_Modules" : false,
"Annotated_Properties_for_Analyst" : true,
"BACKGROUND_PROGRAMMING" : "off",
"COMPRESS" : false,
"CRC_CHECK" : true,
"Clock_Conversion" : true,
"Clock_Route_Order" : 0,
"Correct_Hold_Violation" : true,
"DONE" : false,
"DOWNLOAD_SPEED" : "default",
"Default_Enum_Encoding" : "default",
"Disable_Insert_Pad" : false,
"ENCRYPTION_KEY" : false,
"ENCRYPTION_KEY_TEXT" : "00000000000000000000000000000000",
"FORMAT" : "binary",
"FSM Compiler" : true,
"Fanout_Guide" : 10000,
"Frequency" : "Auto",
"Generate_Constraint_File_of_Ports" : false,
"Generate_IBIS_File" : false,
"Generate_Plain_Text_Timing_Report" : false,
"Generate_Post_PNR_Simulation_Model_File" : false,
"Generate_Post_Place_File" : false,
"Generate_SDF_File" : false,
"Generate_VHDL_Post_PNR_Simulation_Model_File" : false,
"GwSyn_Loop_Limit" : 2000,
"HOTBOOT" : false,
"I2C" : false,
"I2C_SLAVE_ADDR" : "00",
"Implicit_Initial_Value_Support" : false,
"IncludePath" : [
],
"Incremental_Compile" : "",
"Initialize_Primitives" : false,
"JTAG" : false,
"MODE_IO" : false,
"MSPI" : false,
"Multiple_File_Compilation_Unit" : true,
"Number_of_Critical_Paths" : "",
"Number_of_Start/End_Points" : "",
"OUTPUT_BASE_NAME" : "blink_leds",
"POWER_ON_RESET_MONITOR" : true,
"PRINT_BSRAM_VALUE" : true,
"PROGRAM_DONE_BYPASS" : false,
"Pipelining" : true,
"PlaceInRegToIob" : true,
"PlaceIoRegToIob" : true,
"PlaceOutRegToIob" : true,
"Place_Option" : "0",
"Process_Configuration_Verion" : "1.0",
"Promote_Physical_Constraint_Warning_to_Error" : true,
"Push_Tristates" : true,
"READY" : false,
"RECONFIG_N" : false,
"Ram_RW_Check" : true,
"Report_Auto-Placed_Io_Information" : false,
"Resolve_Mixed_Drivers" : false,
"Resource_Sharing" : true,
"Retiming" : false,
"Route_Maxfan" : "23",
"Route_Option" : "0",
"Run_Timing_Driven" : true,
"SECURE_MODE" : false,
"SECURITY_BIT" : true,
"SPI_FLASH_ADDR" : "00000000",
"SSPI" : false,
"Show_All_Warnings" : false,
"Synthesis On/Off Implemented as Translate On/Off" : false,
"Synthesize_tool" : "GowinSyn",
"TclPre" : "",
"TopModule" : "",
"USERCODE" : "default",
"Unused_Pin" : "As_input_tri_stated_with_pull_up",
"Update_Compile_Point_Timing_Data" : false,
"Use_Clock_Period_for_Unconstrainted IO" : false,
"VCCAUX" : "3.3",
"VHDL_Standard" : "VHDL_Std_1993",
"Verilog_Standard" : "Vlg_Std_2001",
"WAKE_UP" : "0",
"Write_Vendor_Constraint_File" : true,
"dsp_balance" : false,
"show_all_warnings" : false,
"turn_off_bg" : false
}

15
led/blink_leds/src/blink_leds.cst
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@ -0,0 +1,15 @@ @@ -0,0 +1,15 @@
IO_LOC "leds[5]" 20;
IO_PORT "leds[5]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[4]" 19;
IO_PORT "leds[4]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[3]" 18;
IO_PORT "leds[3]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[2]" 17;
IO_PORT "leds[2]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[1]" 16;
IO_PORT "leds[1]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[0]" 15;
IO_PORT "leds[0]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "clk" 4;
IO_PORT "clk" PULL_MODE=UP BANK_VCCIO=1.8;

2
led/blink_leds/src/blink_leds.sdc
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@ -0,0 +1,2 @@ @@ -0,0 +1,2 @@
create_clock -name clk_27M -period 37.037 -waveform {0 18.518} [get_ports {clk}]

34
led/blink_leds/src/blink_leds.v
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@ -0,0 +1,34 @@ @@ -0,0 +1,34 @@
module top#(
parameter led_number = 6
)
(
input clk,
output [ led_number-1 :0] leds
);
reg count_1s_flag;
reg [23:0] count_1s = 'd0;
always @(posedge clk ) begin
if( count_1s < 27000000/2 ) begin
count_1s <= count_1s + 'd1;
count_1s_flag <= 'd0;
end
else begin
count_1s <= 'd0;
count_1s_flag <= 'd1;
end
end
reg [5:0] leds_value = 'd0;
always @(posedge clk ) begin
if( count_1s_flag ) begin
leds_value[ led_number-1 :0] <= ~ leds_value[ led_number-1 :0];
end
end
assign leds = ~leds_value;
endmodule

12
led/flow_led/flow_led.gprj
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@ -0,0 +1,12 @@ @@ -0,0 +1,12 @@
<?xml version="1" encoding="UTF-8"?>
<!DOCTYPE gowin-fpga-project>
<Project>
<Template>FPGA</Template>
<Version>5</Version>
<Device name="GW2AR-18C" pn="GW2AR-LV18QN88C8/I7">gw2ar18c-000</Device>
<FileList>
<File path="src/flow_led.v" type="file.verilog" enable="1"/>
<File path="src/flow_led.cst" type="file.cst" enable="1"/>
<File path="src/flow_led.sdc" type="file.sdc" enable="1"/>
</FileList>
</Project>

86
led/flow_led/impl/project_process_config.json
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@ -0,0 +1,86 @@ @@ -0,0 +1,86 @@
{
"Allow_Duplicate_Modules" : false,
"Annotated_Properties_for_Analyst" : true,
"BACKGROUND_PROGRAMMING" : "off",
"COMPRESS" : false,
"CRC_CHECK" : true,
"Clock_Conversion" : true,
"Clock_Route_Order" : 0,
"Correct_Hold_Violation" : true,
"DONE" : false,
"DOWNLOAD_SPEED" : "default",
"Default_Enum_Encoding" : "default",
"Disable_Insert_Pad" : false,
"ENCRYPTION_KEY" : false,
"ENCRYPTION_KEY_TEXT" : "00000000000000000000000000000000",
"FORMAT" : "binary",
"FSM Compiler" : true,
"Fanout_Guide" : 10000,
"Frequency" : "Auto",
"Generate_Constraint_File_of_Ports" : false,
"Generate_IBIS_File" : false,
"Generate_Plain_Text_Timing_Report" : false,
"Generate_Post_PNR_Simulation_Model_File" : false,
"Generate_Post_Place_File" : false,
"Generate_SDF_File" : false,
"Generate_VHDL_Post_PNR_Simulation_Model_File" : false,
"GwSyn_Loop_Limit" : 2000,
"HOTBOOT" : false,
"I2C" : false,
"I2C_SLAVE_ADDR" : "00",
"Implicit_Initial_Value_Support" : false,
"IncludePath" : [
],
"Incremental_Compile" : "",
"Initialize_Primitives" : false,
"JTAG" : false,
"MODE_IO" : false,
"MSPI" : false,
"Multiple_File_Compilation_Unit" : true,
"Number_of_Critical_Paths" : "",
"Number_of_Start/End_Points" : "",
"OUTPUT_BASE_NAME" : "flow_led",
"POWER_ON_RESET_MONITOR" : true,
"PRINT_BSRAM_VALUE" : true,
"PROGRAM_DONE_BYPASS" : false,
"Pipelining" : true,
"PlaceInRegToIob" : true,
"PlaceIoRegToIob" : true,
"PlaceOutRegToIob" : true,
"Place_Option" : "0",
"Process_Configuration_Verion" : "1.0",
"Promote_Physical_Constraint_Warning_to_Error" : true,
"Push_Tristates" : true,
"READY" : false,
"RECONFIG_N" : false,
"Ram_RW_Check" : true,
"Report_Auto-Placed_Io_Information" : false,
"Resolve_Mixed_Drivers" : false,
"Resource_Sharing" : true,
"Retiming" : false,
"Route_Maxfan" : "23",
"Route_Option" : "0",
"Run_Timing_Driven" : true,
"SECURE_MODE" : false,
"SECURITY_BIT" : true,
"SPI_FLASH_ADDR" : "00000000",
"SSPI" : false,
"Show_All_Warnings" : false,
"Synthesis On/Off Implemented as Translate On/Off" : false,
"Synthesize_tool" : "GowinSyn",
"TclPre" : "",
"TopModule" : "",
"USERCODE" : "default",
"Unused_Pin" : "As_input_tri_stated_with_pull_up",
"Update_Compile_Point_Timing_Data" : false,
"Use_Clock_Period_for_Unconstrainted IO" : false,
"VCCAUX" : "3.3",
"VHDL_Standard" : "VHDL_Std_1993",
"Verilog_Standard" : "Vlg_Std_2001",
"WAKE_UP" : "0",
"Write_Vendor_Constraint_File" : true,
"dsp_balance" : false,
"show_all_warnings" : false,
"turn_off_bg" : false
}

15
led/flow_led/src/flow_led.cst
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@ -0,0 +1,15 @@ @@ -0,0 +1,15 @@
IO_LOC "leds[5]" 20;
IO_PORT "leds[5]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[4]" 19;
IO_PORT "leds[4]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[3]" 18;
IO_PORT "leds[3]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[2]" 17;
IO_PORT "leds[2]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[1]" 16;
IO_PORT "leds[1]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[0]" 15;
IO_PORT "leds[0]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "clk" 4;
IO_PORT "clk" PULL_MODE=UP BANK_VCCIO=1.8;

2
led/flow_led/src/flow_led.sdc
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@ -0,0 +1,2 @@ @@ -0,0 +1,2 @@
create_clock -name clk_27M -period 37.037 -waveform {0 18.518} [get_ports {clk}]

34
led/flow_led/src/flow_led.v
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@ -0,0 +1,34 @@ @@ -0,0 +1,34 @@
module top#(
parameter led_number = 6
)
(
input clk,
output [ led_number-1 :0] leds
);
reg count_1s_flag;
reg [23:0] count_1s = 'd0;
always @(posedge clk ) begin
if( count_1s < 27000000/2 ) begin
count_1s <= count_1s + 'd1;
count_1s_flag <= 'd0;
end
else begin
count_1s <= 'd0;
count_1s_flag <= 'd1;
end
end
reg [5:0] leds_value = 'd1;
always @(posedge clk ) begin
if( count_1s_flag ) begin
leds_value[ led_number-1 :0] <= {leds_value[ led_number-2 :0] , leds_value[ led_number-1 ] };
end
end
assign leds = ~leds_value;
endmodule

13
rgb_lcd/lcd_800_400/color_bar/Tang_nano_20K_LCD.gprj.user
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@ -1,13 +0,0 @@ @@ -1,13 +0,0 @@
<?xml version="1" encoding="UTF-8"?>
<!DOCTYPE ProjectUserData>
<UserConfig>
<Version>1.0</Version>
<FlowState>
<Process ID="Synthesis" State="0"/>
<Process ID="Pnr" State="0"/>
<Process ID="Gao" State="0"/>
<Process ID="Rtl_Gao" State="0"/>
</FlowState>
<ResultFileList/>
<Ui>000000ff00000001fd00000002000000000000025b0000031efc0200000001fc0000004c0000031e0000000000fffffffaffffffff0200000003fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000000000000000fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000000000000000fb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff0000000000000000000000030000072000000181fc0100000001fc00000000000007200000000000fffffffaffffffff0100000002fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000000000000000fb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff0000000000000000000004bf0000031e00000004000000040000000800000008fc000000010000000200000003000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e004500640069007401000000a0ffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c00730100000164ffffffff0000000000000000</Ui>
</UserConfig>
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