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remove useless file

pull/1/head
wonderfullook 2 years ago
parent
b7fe4678f4
commit
25f9cf7c3b
11 changed files with 1 additions and 3082 deletions
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  1. 2
      hdmi/hdmi.fs
  2. 21
      hdmi/src/dvi_tx/temp/DviTx/DviTx.prj
  3. 41
      hdmi/src/dvi_tx/temp/DviTx/dvi_tx.log
  4. 1097
      hdmi/src/dvi_tx/temp/DviTx/dvi_tx.vg
  5. 2
      hdmi/src/dvi_tx/temp/DviTx/dvi_tx_defines.v
  6. 1844
      hdmi/src/dvi_tx/temp/DviTx/dvi_tx_syn.rpt.html
  7. 44
      hdmi/src/dvi_tx/temp/DviTx/dvi_tx_syn_resource.html
  8. 2
      hdmi/src/dvi_tx/temp/DviTx/dvi_tx_syn_rsc.xml
  9. 28
      hdmi/src/dvi_tx/temp/DviTx/dvi_tx_tmp.v
  10. 1
      hdmi/src/dvi_tx/temp/DviTx/project.ini
  11. 1
      hdmi/src/dvi_tx/temp/DviTx/top_define.v

2
hdmi/hdmi.fs
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@ -15,7 +15,7 @@ @@ -15,7 +15,7 @@
//SecurityBit: ON
//SecureMode: OFF
//JTAGAsRegularIO: OFF
//Created Time: Tue Mar 21 16:31:12 2023
//Created Time: Tue Mar 21 17:39:41 2023
1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111
1111111111111111
1010010111000011

21
hdmi/src/dvi_tx/temp/DviTx/DviTx.prj
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@ -1,21 +0,0 @@ @@ -1,21 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE gowin-synthesis-project>
<Project>
<Version>beta</Version>
<Device id="GW2AR-18C" package="QFN88" speed="8" partNumber="GW2AR-LV18QN88C8/I7"/>
<FileList>
<File path="Z:/Gowin_V1.9.8.09_win/Gowin/Gowin_V1.9.8.09/IDE/ipcore/DVI_TX/data/dvi_tx_top.v" type="verilog"/>
<File path="Z:/Gowin_V1.9.8.09_win/Gowin/Gowin_V1.9.8.09/IDE/ipcore/DVI_TX/data/rgb2dvi.vp" type="verilog"/>
</FileList>
<OptionList>
<Option type="disable_insert_pad" value="1"/>
<Option type="dsp_balance" value="1"/>
<Option type="include_path" value="Z:/Gowin_V1.9.8.09_win/Gowin/Gowin_V1.9.8.09/IDE/ipcore/DVI_TX/data"/>
<Option type="include_path" value="Z:/20k_nano/hdmi/src/dvi_tx/temp/DviTx"/>
<Option type="output_file" value="dvi_tx.vg"/>
<Option type="output_template" value="dvi_tx_tmp.v"/>
<Option type="ram_balance" value="1"/>
<Option type="ram_rw_check" value="1"/>
<Option type="verilog_language" value="sysv-2017"/>
</OptionList>
</Project>

41
hdmi/src/dvi_tx/temp/DviTx/dvi_tx.log
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@ -1,41 +0,0 @@ @@ -1,41 +0,0 @@
GowinSynthesis start
Running parser ...
Analyzing Verilog file 'Z:\Gowin_V1.9.8.09_win\Gowin\Gowin_V1.9.8.09\IDE\ipcore\DVI_TX\data\dvi_tx_top.v'
Analyzing included file 'top_define.v'("Z:\Gowin_V1.9.8.09_win\Gowin\Gowin_V1.9.8.09\IDE\ipcore\DVI_TX\data\dvi_tx_top.v":26)
Back to file 'Z:\Gowin_V1.9.8.09_win\Gowin\Gowin_V1.9.8.09\IDE\ipcore\DVI_TX\data\dvi_tx_top.v'("Z:\Gowin_V1.9.8.09_win\Gowin\Gowin_V1.9.8.09\IDE\ipcore\DVI_TX\data\dvi_tx_top.v":26)
Analyzing included file 'Z:\Gowin_V1.9.8.09_win\Gowin\Gowin_V1.9.8.09\IDE\ipcore\DVI_TX\data\static_macro_define.v'("Z:\Gowin_V1.9.8.09_win\Gowin\Gowin_V1.9.8.09\IDE\ipcore\DVI_TX\data\dvi_tx_top.v":27)
Back to file 'Z:\Gowin_V1.9.8.09_win\Gowin\Gowin_V1.9.8.09\IDE\ipcore\DVI_TX\data\dvi_tx_top.v'("Z:\Gowin_V1.9.8.09_win\Gowin\Gowin_V1.9.8.09\IDE\ipcore\DVI_TX\data\dvi_tx_top.v":27)
Analyzing included file 'dvi_tx_defines.v'("Z:\Gowin_V1.9.8.09_win\Gowin\Gowin_V1.9.8.09\IDE\ipcore\DVI_TX\data\dvi_tx_top.v":28)
Back to file 'Z:\Gowin_V1.9.8.09_win\Gowin\Gowin_V1.9.8.09\IDE\ipcore\DVI_TX\data\dvi_tx_top.v'("Z:\Gowin_V1.9.8.09_win\Gowin\Gowin_V1.9.8.09\IDE\ipcore\DVI_TX\data\dvi_tx_top.v":28)
Analyzing Verilog file 'Z:\Gowin_V1.9.8.09_win\Gowin\Gowin_V1.9.8.09\IDE\ipcore\DVI_TX\data\rgb2dvi.vp'
Analyzing included file 'top_define.v'("Z:\Gowin_V1.9.8.09_win\Gowin\Gowin_V1.9.8.09\IDE\ipcore\DVI_TX\data\rgb2dvi.vp":352)
Back to file 'Z:\Gowin_V1.9.8.09_win\Gowin\Gowin_V1.9.8.09\IDE\ipcore\DVI_TX\data\rgb2dvi.vp'("Z:\Gowin_V1.9.8.09_win\Gowin\Gowin_V1.9.8.09\IDE\ipcore\DVI_TX\data\rgb2dvi.vp":352)
Analyzing included file 'Z:\Gowin_V1.9.8.09_win\Gowin\Gowin_V1.9.8.09\IDE\ipcore\DVI_TX\data\static_macro_define.v'("Z:\Gowin_V1.9.8.09_win\Gowin\Gowin_V1.9.8.09\IDE\ipcore\DVI_TX\data\rgb2dvi.vp":352)
Back to file 'Z:\Gowin_V1.9.8.09_win\Gowin\Gowin_V1.9.8.09\IDE\ipcore\DVI_TX\data\rgb2dvi.vp'("Z:\Gowin_V1.9.8.09_win\Gowin\Gowin_V1.9.8.09\IDE\ipcore\DVI_TX\data\rgb2dvi.vp":352)
Analyzing included file 'dvi_tx_defines.v'("Z:\Gowin_V1.9.8.09_win\Gowin\Gowin_V1.9.8.09\IDE\ipcore\DVI_TX\data\rgb2dvi.vp":352)
Back to file 'Z:\Gowin_V1.9.8.09_win\Gowin\Gowin_V1.9.8.09\IDE\ipcore\DVI_TX\data\rgb2dvi.vp'("Z:\Gowin_V1.9.8.09_win\Gowin\Gowin_V1.9.8.09\IDE\ipcore\DVI_TX\data\rgb2dvi.vp":352)
Compiling module 'DVI_TX_Top'("Z:\Gowin_V1.9.8.09_win\Gowin\Gowin_V1.9.8.09\IDE\ipcore\DVI_TX\data\dvi_tx_top.v":30)
Compiling module '**'("Z:\Gowin_V1.9.8.09_win\Gowin\Gowin_V1.9.8.09\IDE\ipcore\DVI_TX\data\rgb2dvi.vp":0)
Compiling module '**'("Z:\Gowin_V1.9.8.09_win\Gowin\Gowin_V1.9.8.09\IDE\ipcore\DVI_TX\data\rgb2dvi.vp":0)
WARN (EX3791) : Expression size ** truncated to fit in target size **("Z:\Gowin_V1.9.8.09_win\Gowin\Gowin_V1.9.8.09\IDE\ipcore\DVI_TX\data\rgb2dvi.vp":0)
NOTE (EX0101) : Current top module is "DVI_TX_Top"
[5%] Running netlist conversion ...
Running device independent optimization ...
[10%] Optimizing Phase 0 completed
[15%] Optimizing Phase 1 completed
[25%] Optimizing Phase 2 completed
Running inference ...
[30%] Inferring Phase 0 completed
[40%] Inferring Phase 1 completed
[50%] Inferring Phase 2 completed
[55%] Inferring Phase 3 completed
Running technical mapping ...
[60%] Tech-Mapping Phase 0 completed
[65%] Tech-Mapping Phase 1 completed
[75%] Tech-Mapping Phase 2 completed
[80%] Tech-Mapping Phase 3 completed
[90%] Tech-Mapping Phase 4 completed
[95%] Generate netlist file "Z:\20k_nano\hdmi\src\dvi_tx\temp\DviTx\dvi_tx.vg" completed
Generate template file "Z:\20k_nano\hdmi\src\dvi_tx\temp\DviTx\dvi_tx_tmp.v" completed
[100%] Generate report file "Z:\20k_nano\hdmi\src\dvi_tx\temp\DviTx\dvi_tx_syn.rpt.html" completed
GowinSynthesis finish

1097
hdmi/src/dvi_tx/temp/DviTx/dvi_tx.vg
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2
hdmi/src/dvi_tx/temp/DviTx/dvi_tx_defines.v
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@ -1,2 +0,0 @@ @@ -1,2 +0,0 @@
`define TX_USE_EXTERNAL_CLK
`define USE_ELVDS_OBUF

1844
hdmi/src/dvi_tx/temp/DviTx/dvi_tx_syn.rpt.html
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44
hdmi/src/dvi_tx/temp/DviTx/dvi_tx_syn_resource.html
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@ -1,44 +0,0 @@ @@ -1,44 +0,0 @@
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html>
<head>
<title>Hierarchy Module Resource</title>
<style type="text/css">
body { font-family: Verdana, Arial, sans-serif; font-size: 14px; }
div#main_wrapper{ width: 100%; }
h1 {text-align: center; }
h1 {margin-top: 36px; }
table, th, td { border: 1px solid #aaa; }
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
th, td { align = "center"; padding: 5px 2px 5px 5px; }
th { color: #fff; font-weight: bold; background-color: #0084ff; }
table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-color: #dee8f4; }
</style>
</head>
<body>
<div id="main_wrapper">
<div id="content">
<h1>Hierarchy Module Resource</h1>
<table>
<tr>
<th class="label">MODULE NAME</th>
<th class="label">REG NUMBER</th>
<th class="label">ALU NUMBER</th>
<th class="label">LUT NUMBER</th>
<th class="label">DSP NUMBER</th>
<th class="label">BSRAM NUMBER</th>
<th class="label">SSRAM NUMBER</th>
</tr>
<tr>
<td class="label">DVI_TX_Top (Z:/Gowin_V1.9.8.09_win/Gowin/Gowin_V1.9.8.09/IDE/ipcore/DVI_TX/data/dvi_tx_top.v)</td>
<td align = "center">73</td>
<td align = "center">68</td>
<td align = "center">217</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
</tr>
</table>
</div><!-- content -->
</div><!-- main_wrapper -->
</body>
</html>

2
hdmi/src/dvi_tx/temp/DviTx/dvi_tx_syn_rsc.xml
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@ -1,2 +0,0 @@ @@ -1,2 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<Module name="DVI_TX_Top" Register="73" Alu="68" Lut="217"/>

28
hdmi/src/dvi_tx/temp/DviTx/dvi_tx_tmp.v
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@ -1,28 +0,0 @@ @@ -1,28 +0,0 @@
//Copyright (C)2014-2022 Gowin Semiconductor Corporation.
//All rights reserved.
//File Title: Template file for instantiation
//GOWIN Version: GowinSynthesis V1.9.8.09
//Part Number: GW2AR-LV18QN88C8/I7
//Device: GW2AR-18C
//Created Time: Wed Jan 11 17:04:11 2023
//Change the instance name and port connections to the signal names
//--------Copy here to design--------
DVI_TX_Top your_instance_name(
.I_rst_n(I_rst_n_i), //input I_rst_n
.I_serial_clk(I_serial_clk_i), //input I_serial_clk
.I_rgb_clk(I_rgb_clk_i), //input I_rgb_clk
.I_rgb_vs(I_rgb_vs_i), //input I_rgb_vs
.I_rgb_hs(I_rgb_hs_i), //input I_rgb_hs
.I_rgb_de(I_rgb_de_i), //input I_rgb_de
.I_rgb_r(I_rgb_r_i), //input [7:0] I_rgb_r
.I_rgb_g(I_rgb_g_i), //input [7:0] I_rgb_g
.I_rgb_b(I_rgb_b_i), //input [7:0] I_rgb_b
.O_tmds_clk_p(O_tmds_clk_p_o), //output O_tmds_clk_p
.O_tmds_clk_n(O_tmds_clk_n_o), //output O_tmds_clk_n
.O_tmds_data_p(O_tmds_data_p_o), //output [2:0] O_tmds_data_p
.O_tmds_data_n(O_tmds_data_n_o) //output [2:0] O_tmds_data_n
);
//--------Copy end-------------------

1
hdmi/src/dvi_tx/temp/DviTx/project.ini
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RESOURCE_CHECK=false

1
hdmi/src/dvi_tx/temp/DviTx/top_define.v
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@ -1 +0,0 @@ @@ -1 +0,0 @@
`define module_name DVI_TX_Top
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